OpenRAM

Commit Graph

Author	SHA1	Message	Date
Michael Timothy Grimes	64e7ed5b5e	Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.	2018-01-09 13:39:42 -08:00

Author

SHA1

Message

Date

Michael Timothy Grimes

64e7ed5b5e

Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports

Adding 04_pbitcell_test.py: The benchtest for pbitcell

Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read
transistors and their corresponding vias. Then several drc corrections need to be made.

2018-01-09 13:39:42 -08:00

1 Commits