OpenRAM

Commit Graph

Author	SHA1	Message	Date
mrg	e1967dc548	Draft local and global arrays. Ensure rows before cols in usage.	2020-07-23 14:43:14 -07:00
mrg	5514996708	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
mrg	0880c393fd	Fix base bitcell syntax error. Remove some unused imports.	2020-01-30 01:58:30 +00:00
Bastian Koppelmann	dd1afe0313	Bitcell arrays: Allow mirroring on the y axis this allows for bitcells that need to be mirrored on the y axis, like thin cells. However, the portdata elements also need to be mirrored on the y axis. Otherwise the router will fail horribly when connecting bitlines. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>	2020-01-28 15:51:21 +01:00
Bastian Koppelmann	3fb2b9c1c3	Bitcell arrays: Create abstract base class a lot of functions of dummy- and bitcell-array are either copy-pasted or have just slight differences. Merge all of those into an abstract base class such that we don't have too much duplicate code. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>	2020-01-28 10:59:58 +01:00
Matt Guthaus	ed28b4983b	Clean up and generalize layer rules. Convert metalN to mN. Generalize helper constants in modules for space, width, enclose, etc. Use layer stacks whever possible. Try to remove drc() calls in liu of helper constants.	2019-12-17 11:03:36 -08:00
Matt Guthaus	ad35f8745e	Add direction to pins of all modules	2019-08-06 14:14:09 -07:00
mrg	e550d6ff10	Port name maps between bank and replica array working.	2019-07-15 11:29:29 -07:00
mrg	d72691f6c2	Make mirror optional argument	2019-07-12 11:14:47 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	4523a7b9f6	Replica bitcell array working	2019-06-19 16:03:21 -07:00

11 Commits