9 Commits

Author	SHA1	Message	Date
Hunter Nichols	d8617acff2	Merged with dev	2019-05-15 18:48:00 -07:00
Hunter Nichols	d54074d68e	Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.	2019-05-07 00:52:27 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Hunter Nichols	e292767166	Added graph creation and functions in base class and lower level modules.	2019-04-24 14:23:22 -07:00
Matt Guthaus	a418431a42	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
Hunter Nichols	8957c556db	Added sense amp enable delay calculation.	2018-11-08 23:54:18 -08:00
Matt Guthaus	1fe767343e	Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.	2018-11-07 11:31:44 -08:00
Hunter Nichols	b00fc040a3	Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.	2018-11-01 12:29:49 -07:00