16 Commits

Author	SHA1	Message	Date
Hunter Nichols	ad229b1504	Altered indexing of objects in SRAM factory to remove duplications of items using OPTS names. Added smarter bitline name checking.	2019-05-28 16:55:09 -07:00
Hunter Nichols	d08181455c	Added multiport bitcell support for storage node checks	2019-05-20 22:50:03 -07:00
Hunter Nichols	d8617acff2	Merged with dev	2019-05-15 18:48:00 -07:00
Hunter Nichols	d54074d68e	Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.	2019-05-07 00:52:27 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Hunter Nichols	e292767166	Added graph creation and functions in base class and lower level modules.	2019-04-24 14:23:22 -07:00
Hunter Nichols	a500d7ee3d	Adjusted bitcell analytical delays for multiport cells.	2019-04-09 02:49:52 -07:00
Hunter Nichols	80a325fe32	Added corner information for analytical power estimation.	2019-03-04 19:27:53 -08:00
Hunter Nichols	0e96648211	Added linear corner factors in analytical delay model.	2019-03-04 00:42:18 -08:00
Matt Guthaus	a418431a42	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
Hunter Nichols	8957c556db	Added sense amp enable delay calculation.	2018-11-08 23:54:18 -08:00
Matt Guthaus	1fe767343e	Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.	2018-11-07 11:31:44 -08:00
Hunter Nichols	6efe0f56c2	Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.	2018-10-26 00:08:13 -07:00
Hunter Nichols	8e243258e4	Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.	2018-10-26 00:08:12 -07:00
Hunter Nichols	53cb4e7f5e	Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.	2018-10-22 23:33:01 -07:00