8 Commits

Author	SHA1	Message	Date
Matt Guthaus	58da8af619	Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.	2018-01-31 10:04:28 -08:00
Matt Guthaus	1dc7752429	Fix 6T and replica cell contact spacing issues with Magic DRC. ... DRC/LVS passing for all parameterized gates. Magic and GDS match for SCMOS rules again.	2018-01-26 12:39:00 -08:00
Matt Guthaus	490a70dee9	Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.	2018-01-19 16:38:19 -08:00
Matt Guthaus	95f1a24f72	Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).	2017-11-09 11:13:44 -08:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
Matt Guthaus	20d8c0bc45	Improved characterizer.	2017-07-06 08:42:25 -07:00
Matt Guthaus	34e180b901	Analytical delay model from Bin Wu. Unit test not passing.	2017-05-30 12:50:07 -07:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00