9 Commits

Author	SHA1	Message	Date
Matt Guthaus	ad35f8745e	Add direction to pins of all modules	2019-08-06 14:14:09 -07:00
Hunter Nichols	24b1fa38a0	Added graph fixes to handmade multiport cells.	2019-07-30 20:31:32 -07:00
Matt Guthaus	fb60b51c72	Add check bits. Clean up logic. Move read/write bit check to next cycle.	2019-07-24 16:57:04 -07:00
Hunter Nichols	9696401f34	Added graph exclusions to replica column to reduce s_en paths.	2019-07-16 23:47:34 -07:00
mrg	e550d6ff10	Port name maps between bank and replica array working.	2019-07-15 11:29:29 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	b9d993c88b	Add dummy bitcell module. ... Modify bitcell logic to guess if bitcell is not "bitcell" No longer need to specify replica (and dummy) bitcell explicitly Add support for 1 or 2 port replica array.	2019-07-05 12:58:52 -07:00
mrg	4523a7b9f6	Replica bitcell array working	2019-06-19 16:03:21 -07:00
mrg	b67f06a65a	Add replica column for inclusion in replica bitcell array	2019-06-14 12:15:16 -07:00