luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,833 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

4 Commits

Author SHA1 Message Date
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
Matt Guthaus f914ab0ece Re-enable replica tests 2019-07-03 14:57:47 -07:00
mrg 70c83f20b6 Fixes to pass unit tests. 
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
 2019-07-03 13:37:56 -07:00
mrg b67f06a65a Add replica column for inclusion in replica bitcell array 2019-06-14 12:15:16 -07:00