4 Commits

Author	SHA1	Message	Date
Hadir Khan	9d6052b86c	fix for matching the layout vs verilog port names for rom	2023-12-20 15:30:07 -08:00
Gary Mejia	9a36cce7ae	Fixed formatting on all files	2023-06-14 12:28:36 -07:00
Gary Mejia	a3284e8b47	Fixed module from writing syntax issues	2023-06-13 17:30:38 -07:00
Gary Mejia	692acd2066	Verilog ROM model created for testing	2023-06-12 15:35:54 -07:00