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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
937 Commits 5 Branches 63 Tags
93ae7ebd0082acad9aa3fb5168bc479f38eba4c0
Commit Graph
10 Commits
Author SHA1 Message Date
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Matt Guthaus 9e38b8aca1 Deleted old images. 2018-02-12 17:08:24 -08:00
Matt Guthaus bad24f9c8a Update timing to be from NEGATIVE edge in docs. Update sense amplifier to have PMOS for bitline isolation. 2018-02-12 17:08:01 -08:00
Matt Guthaus 72b3072e3f Updated column mux section. Removed some old, unused, or bad images. 2018-02-12 16:37:49 -08:00
Matt Guthaus 93c66ec45d Update precharge section. 2018-02-12 15:38:53 -08:00
Matt Guthaus 21967fccde Update bitcell and array section. 2018-02-12 15:30:38 -08:00
Matt Guthaus d2ed35526a Updates to intro and overview. Some edits to tech and DRC/LVS section. 2018-02-12 15:07:16 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC.
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
2018-01-26 12:39:00 -08:00
Matt Guthaus 10ced33127 Fixed command line arguments to take priority over config file. Any option can be specified in config file now. 2018-01-21 11:21:09 -08:00
Matt Guthaus c80a55c13d Adding old documentation. Partially updated intro and overview. It is very outdated. 2018-01-19 17:31:17 -08:00
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