Hunter Nichols
4e08e2da87
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
Matt Guthaus
6e044b776f
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
Matt Guthaus
a234b0af88
Fix space before comment
2019-06-14 08:43:41 -07:00
mrg
fc12ea24e9
Add boundary to every module and pgate for visual debug.
2019-06-03 15:27:37 -07:00
Hunter Nichols
d8617acff2
Merged with dev
2019-05-15 18:48:00 -07:00
Hunter Nichols
d54074d68e
Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.
2019-05-07 00:52:27 -07:00
Matt Guthaus
0f03553689
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
Matt Guthaus
3f9a987e51
Update copyright. Add header to all OpenRAM files.
2019-04-26 12:33:53 -07:00
Matt Guthaus
05ad4285af
Cleanup pgate code.
...
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
2019-04-26 12:30:42 -07:00
Matt Guthaus
25bc3a66ed
Add far left option for contact placement in pgates.
2019-04-17 13:41:35 -07:00
Matt Guthaus
be20408fb2
Rewrite add_contact to use layer directions.
2019-04-15 18:00:36 -07:00
Matt Guthaus
5192a01f2d
Convert pgates to use ptx through the factory
2019-01-16 16:30:31 -08:00
Matt Guthaus
a418431a42
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
Matt Guthaus
ce8c2d983d
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
Matt Guthaus
4932d83afc
Add design rules classes for complex design rules
2018-10-12 09:44:36 -07:00
Matt Guthaus
6963a1092f
Make bitcell width/height not static. Update modules to use it for pbitcell.
2018-09-04 11:55:22 -07:00
Matt Guthaus
97c08bce95
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
...
Shift s_en buffers even with other cells.
2018-03-23 08:14:09 -07:00
Matt Guthaus
7100d6f904
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00