3 Commits

Author	SHA1	Message	Date
mrg	87419bd640	Fix bitcell and pbitcell with different cell names	2020-11-03 11:30:40 -08:00
Aditi Sinha	c39c0efd39	Updated spare col tests	2020-06-08 16:38:18 +00:00
Aditi Sinha	eb0c595dbe	SRAM layout and functional tests with spare cols	2020-06-03 12:31:30 +00:00