luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,526 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Matt Guthaus 84c798d9e4 Move last few modules to base dir 2018-02-09 10:29:37 -08:00