15 Commits

Author	SHA1	Message	Date
Matt Guthaus	6080b59058	Fix nand input ordering to correct netgen LVS error of wordline driver.	2018-01-29 15:36:37 -08:00
Matt Guthaus	1dc7752429	Fix 6T and replica cell contact spacing issues with Magic DRC. ... DRC/LVS passing for all parameterized gates. Magic and GDS match for SCMOS rules again.	2018-01-26 12:39:00 -08:00
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. ... Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00
Matt Guthaus	107cad15a1	Change layout function names to be consistent.	2017-11-30 12:01:04 -08:00
Matt Guthaus	0214cfb48e	Fix single finger ptx bugs.	2017-11-30 11:56:40 -08:00
Matt Guthaus	7ff82a2aed	Improved ptx code but removed internal active/poly positions.	2017-11-28 18:13:32 -08:00
Matt Guthaus	95f1a24f72	Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).	2017-11-09 11:13:44 -08:00
mguthaus	5c10aebc0f	Fix bug in multifinger ptx. Replace LEF file with new snapped layout.	2017-10-06 16:23:23 -07:00
Matt Guthaus	10a8531813	Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function.	2017-10-06 15:30:15 -07:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
Matt Guthaus	20d8c0bc45	Improved characterizer.	2017-07-06 08:42:25 -07:00
mguthaus	f32912f07c	Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.	2017-06-02 11:11:57 -07:00
Matt Guthaus	34e180b901	Analytical delay model from Bin Wu. Unit test not passing.	2017-05-30 12:50:07 -07:00
Matt Guthaus	e1c3d77a5d	Removed import cell since cell is removed from simplified txt file	2016-11-09 12:20:52 -08:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00