8 Commits

Author	SHA1	Message	Date
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. ... Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00
Matt Guthaus	10a8531813	Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function.	2017-10-06 15:30:15 -07:00
Matt Guthaus	a9797d12ab	Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins.	2017-10-05 17:35:05 -07:00
Matt Guthaus	e06e1691c8	Two bank SRAMs working in both technologies.	2017-09-29 16:22:13 -07:00
Matt Guthaus	d29dd03373	SRAM single bank passing DRC/LVS.	2017-09-13 15:46:41 -07:00
Matt Guthaus	d17711c394	Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way.	2017-08-24 16:22:14 -07:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00