Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
1,321 Commits 5 Branches 63 Tags
58e41a998fecdf10fd0d6c396086287b40f7b8f8
Commit Graph
11 Commits
Author SHA1 Message Date
Matt Guthaus 43472dfa46 Modify sense amp to cross coupled inverter 2018-11-15 16:55:18 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Matt Guthaus 9e38b8aca1 Deleted old images. 2018-02-12 17:08:24 -08:00
Matt Guthaus bad24f9c8a Update timing to be from NEGATIVE edge in docs. Update sense amplifier to have PMOS for bitline isolation. 2018-02-12 17:08:01 -08:00
Matt Guthaus 72b3072e3f Updated column mux section. Removed some old, unused, or bad images. 2018-02-12 16:37:49 -08:00
Matt Guthaus 93c66ec45d Update precharge section. 2018-02-12 15:38:53 -08:00
Matt Guthaus 21967fccde Update bitcell and array section. 2018-02-12 15:30:38 -08:00
Matt Guthaus d2ed35526a Updates to intro and overview. Some edits to tech and DRC/LVS section. 2018-02-12 15:07:16 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC.
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
2018-01-26 12:39:00 -08:00
Matt Guthaus 10ced33127 Fixed command line arguments to take priority over config file. Any option can be specified in config file now. 2018-01-21 11:21:09 -08:00
Matt Guthaus c80a55c13d Adding old documentation. Partially updated intro and overview. It is very outdated. 2018-01-19 17:31:17 -08:00
Powered by Gitea Version: 1.27.2 Page: 184ms Template: 4ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API