9 Commits

Author	SHA1	Message	Date
Matt Guthaus	490a70dee9	Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.	2018-01-19 16:38:19 -08:00
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
Matt Guthaus	95f1a24f72	Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).	2017-11-09 11:13:44 -08:00
Matt Guthaus	e06e1691c8	Two bank SRAMs working in both technologies.	2017-09-29 16:22:13 -07:00
Matt Guthaus	3ea003c367	Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error.	2017-09-11 14:30:52 -07:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
Matt Guthaus	20d8c0bc45	Improved characterizer.	2017-07-06 08:42:25 -07:00
Matt Guthaus	34e180b901	Analytical delay model from Bin Wu. Unit test not passing.	2017-05-30 12:50:07 -07:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00