14 Commits

Author	SHA1	Message	Date
Matt Guthaus	ee7bf7c5f2	Remove metal3 blanket blockage on library cells.	2017-12-19 09:55:59 -08:00
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. ... Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00
Matt Guthaus	0214cfb48e	Fix single finger ptx bugs.	2017-11-30 11:56:40 -08:00
Matt Guthaus	e06e1691c8	Two bank SRAMs working in both technologies.	2017-09-29 16:22:13 -07:00
Matt Guthaus	d29dd03373	SRAM single bank passing DRC/LVS.	2017-09-13 15:46:41 -07:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
mguthaus	7ca5c0b34f	Added zoom to technology file so labels in each tech are readable size. Made default size.	2017-05-23 16:18:11 -07:00
Matt Guthaus	a31f87bc72	Merge master branch into router	2017-01-09 14:04:37 -08:00
Bin wu	8c4b97753a	not applying snap_to_grid to all vectors	2016-11-20 11:06:53 -08:00
Matt Guthaus	51d7a673bd	Improve debug messages. Remove add_inst for via in wire.	2016-11-18 14:10:30 -08:00
Bin wu	0658cc20e6	move snapt_to_grid to a function in vector class	2016-11-17 17:12:48 -08:00
Bin wu	7bae37c026	apply vector to hierchay_layout and geometry and contact	2016-11-10 17:28:06 -08:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00