OpenRAM

Commit Graph

Author	SHA1	Message	Date
mrg	a305d788d7	Vertical gates need both well contacts.	2020-05-13 16:54:35 -07:00
mrg	617bf302d1	Add option to remove wells. Save area in pgates with redundant wells.	2020-05-13 14:46:42 -07:00
mrg	c96a6d0b9d	Add no well option. Add stack gates vertical option.	2020-05-11 16:22:08 -07:00
mrg	b7c66d7e07	Changes to simplify metal preferred directions and pitches. Changes to allow decoder height to be a 2x multiple of bitcell height. Split of control logic tests. Fixed track spacing in SRAM and channel router PEP8 cleanup.	2020-05-10 11:32:45 -07:00
mrg	dd73afc983	Changes to allow decoder height to be a 2x multiple of bitcell height. Convert to use li layer in pgates. Fix multifinger devices with li layers. Simplify wordline driver input routing. Fix power pin direction option update. PEP8 cleanup Changes to simplify metal preferred directions and pitches. Split of control logic tests.	2020-05-10 06:56:22 -07:00
mrg	fc85dfe29f	Add boundary to all pgates	2020-04-21 15:21:57 -07:00
Matt Guthaus	ed28b4983b	Clean up and generalize layer rules. Convert metalN to mN. Generalize helper constants in modules for space, width, enclose, etc. Use layer stacks whever possible. Try to remove drc() calls in liu of helper constants.	2019-12-17 11:03:36 -08:00
Matt Guthaus	84c7146792	Fix some pep8 errors/warnings in pgate and examples.	2019-10-06 17:30:16 +00:00
jsowash	27ec617315	Fixed M1.5 error in 8mux tests which came from pdriver.	2019-08-22 09:34:53 -07:00
Matt Guthaus	54ab9440db	Use pdriver instead of pinv in pand gates.	2019-08-21 10:18:46 -07:00
Matt Guthaus	275891084b	Add pand3	2019-08-07 16:33:29 -07:00

11 Commits