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luke/OpenRAM
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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
2,188 Commits 5 Branches 63 Tags
233ec010fffecd2f1fe45d4f9bee3f0ec4dbe00a
Commit Graph
8 Commits
Author SHA1 Message Date
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
2019-06-03 15:27:37 -07:00
Matt Guthaus 1a54fd0d1c Remove scn3me_subm since it does not have 4 metal layers 2019-03-11 14:20:02 -07:00
Matt Guthaus 9a6081de0e Remove KP from SCMOS models to get rid of ngspice error. 2018-03-01 11:10:04 -08:00
Matt Guthaus b31f3c18af Change BSIM3 models to version 3.3.0. Add comment about multithreading selection. 2018-02-21 17:50:12 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus ccc8ed2b48 Add slow and fast SCMOS spice models. 2018-02-12 17:16:40 -08:00
mguthaus 6bf4190dde Fix missing tech name in path to spice models. Rename models to p,n. 2018-02-12 10:24:15 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
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