luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

Single bank working except for channel routing error in 4-way case.

Browse Source
This commit is contained in:
Matt Guthaus
2018-07-17 14:40:04 -07:00
parent 7a69fc1bca
commit ffc866ef78
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bank.py
+1 -1
View File
@@ -380,7 +380,7 @@ class bank(design.design):
Create a 2:4 or 3:8 column address decoder.
"""
# Place the col decoder right aligned with row decoder
x_off = -(self.central_bus_width + self.wordline_driver.width)
x_off = -(self.central_bus_width + self.wordline_driver.width + self.col_decoder.width)
y_off = -(self.col_decoder.height + 2*drc["well_to_well"])
self.col_decoder_inst=self.add_inst(name="col_address_decoder",
mod=self.col_decoder,