From ffc866ef78ee0d76b106401bd75667f7ff89dccc Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 17 Jul 2018 14:40:04 -0700 Subject: [PATCH] Single bank working except for channel routing error in 4-way case. --- compiler/modules/bank.py | 2 +- compiler/sram_1bank.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 631e631d..ba8fd268 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -380,7 +380,7 @@ class bank(design.design): Create a 2:4 or 3:8 column address decoder. """ # Place the col decoder right aligned with row decoder - x_off = -(self.central_bus_width + self.wordline_driver.width) + x_off = -(self.central_bus_width + self.wordline_driver.width + self.col_decoder.width) y_off = -(self.col_decoder.height + 2*drc["well_to_well"]) self.col_decoder_inst=self.add_inst(name="col_address_decoder", mod=self.col_decoder, diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index afa174fc..cc40a707 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -154,7 +154,7 @@ class sram_1bank(sram_base): def route_col_addr_dff(self): """ Connect the output of the row flops to the bank pins """ - bus_names = ["A[{}]".format(x) for x in range(self.word_size)] + bus_names = ["A[{}]".format(x) for x in range(self.col_addr_size)] col_addr_bus_offsets = self.create_horizontal_bus(layer="metal1", pitch=self.m1_pitch, offset=self.col_addr_dff_inst.ul() + vector(0, self.m1_pitch),