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Add port option to precharge array

This commit is contained in:
mrg 2020-06-02 11:44:22 -07:00
parent f1b7b91b1a
commit fdf51c5a00
1 changed files with 3 additions and 2 deletions
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5
compiler/modules/precharge_array.py
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@ -19,13 +19,14 @@ class precharge_array(design.design):
of bit line columns, height is the height of the bit-cell array. of bit line columns, height is the height of the bit-cell array.
""" """
def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br"): def __init__(self, name, columns, port, size=1, bitcell_bl="bl", bitcell_br="br"):
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name)) debug.info(1, "Creating {0}".format(self.name))
self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br)) self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br))
self.columns = columns self.columns = columns
self.size = size self.size = size
self.port = port
self.bitcell_bl = bitcell_bl self.bitcell_bl = bitcell_bl
self.bitcell_br = bitcell_br self.bitcell_br = bitcell_br
@ -106,7 +107,7 @@ class precharge_array(design.design):
xoffset = 0 xoffset = 0
for i in range(self.columns): for i in range(self.columns):
tempx = xoffset tempx = xoffset
if cell_properties.bitcell.mirror.y and (i + 1) % 2: if cell_properties.bitcell.mirror.y and (i + 1 + self.port) % 2:
mirror = "MY" mirror = "MY"
tempx = tempx + self.pc_cell.width tempx = tempx + self.pc_cell.width
else: else: