From fdf51c5a00ca61f8601ae344ee7997be8bd2a5a6 Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Tue, 2 Jun 2020 11:44:22 -0700
Subject: [PATCH] Add port option to precharge array

---
 compiler/modules/precharge_array.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py
index af612af4..3c64e85f 100644
--- a/compiler/modules/precharge_array.py
+++ b/compiler/modules/precharge_array.py
@@ -19,13 +19,14 @@ class precharge_array(design.design):
     of bit line columns, height is the height of the bit-cell array.
     """
 
-    def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br"):
+    def __init__(self, name, columns, port, size=1, bitcell_bl="bl", bitcell_br="br"):
         design.design.__init__(self, name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br))
         
         self.columns = columns
         self.size = size
+        self.port = port 
         self.bitcell_bl = bitcell_bl
         self.bitcell_br = bitcell_br
 
@@ -106,7 +107,7 @@ class precharge_array(design.design):
         xoffset = 0
         for i in range(self.columns):
             tempx = xoffset
-            if cell_properties.bitcell.mirror.y and (i + 1) % 2:
+            if cell_properties.bitcell.mirror.y and (i + 1 + self.port) % 2:
                 mirror = "MY"
                 tempx = tempx + self.pc_cell.width
             else: