Use library imports globally

__init__.py

@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 import os
-import sys
 
 # Attempt to add the source code to the PYTHONPATH here before running globals.init_openram().
 try:
@@ -17,8 +16,12 @@ except:
 if not os.path.isdir(OPENRAM_HOME):
     assert False
 
-if OPENRAM_HOME not in sys.path:
-    sys.path.insert(0, OPENRAM_HOME)
+# Make sure that OPENRAM_HOME is an environment variable just in case
+if "OPENRAM_HOME" not in os.environ.keys():
+    os.environ["OPENRAM_HOME"] = OPENRAM_HOME
 
-# Export everything in globals.py as part of "openram"
-from globals import *
+# Prepend $OPENRAM_HOME to __path__ so that openram will use those modules
+__path__.insert(0, OPENRAM_HOME)
+
+# Import everything in globals.py
+from .globals import *

compiler/base/channel_route.py

@@ -6,8 +6,8 @@
 # All rights reserved.
 #
 import collections
-import debug
-from tech import drc
+from openram import debug
+from openram.tech import drc
 from .vector import vector
 from .design import design
 
@@ -405,4 +405,3 @@ class channel_route(design):
                                       to_layer=self.horizontal_layer,
                                       offset=pin_pos)
 
-

compiler/base/contact.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.tech import drc, layer, preferred_directions
+from openram.tech import layer as tech_layers
 from .hierarchy_design import hierarchy_design
 from .vector import vector
-from tech import drc, layer, preferred_directions
-from tech import layer as tech_layers
 
 
 class contact(hierarchy_design):

compiler/base/delay_data.py

@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class delay_data():
     """
     This is the delay class to represent the delay information
@@ -38,7 +37,3 @@ class delay_data():
         assert isinstance(other, delay_data)
         return delay_data(other.delay + self.delay,
                           self.slew)
-
-
-
-

compiler/base/design.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import GDS, layer
-from tech import preferred_directions
-from tech import cell_properties as props
-from globals import OPTS
+from openram import debug
+from openram.tech import GDS, layer
+from openram.tech import preferred_directions
+from openram.tech import cell_properties as props
+from openram import OPTS
 from . import utils
 from .hierarchy_design import hierarchy_design
 
@@ -67,7 +67,7 @@ class design(hierarchy_design):
         self.setup_multiport_constants()
 
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             self.supply_stack = power_grid
         except ImportError:
             # if no power_grid is specified by tech we use sensible defaults

compiler/base/geometry.py

@@ -8,14 +8,14 @@
 """
 This provides a set of useful generic types for the gdsMill interface.
 """
-import debug
-from .vector import vector
-import tech
 import math
 import copy
 import numpy as np
-from globals import OPTS
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .utils import round_to_grid
+from .vector import vector
 
 
 class geometry:

compiler/base/hierarchy_design.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import os
+from openram import debug
+from openram import OPTS
 from .hierarchy_layout import layout
 from .hierarchy_spice import spice
-import debug
-import os
-from globals import OPTS
 
 
 class hierarchy_design(spice, layout):
@@ -49,7 +49,7 @@ class hierarchy_design(spice, layout):
 
     def DRC_LVS(self, final_verification=False, force_check=False):
         """Checks both DRC and LVS for a module"""
-        import verify
+        from openram import verify
 
         # No layout to check
         if OPTS.netlist_only:
@@ -82,7 +82,7 @@ class hierarchy_design(spice, layout):
 
     def DRC(self, final_verification=False):
         """Checks DRC for a module"""
-        import verify
+        from openram import verify
 
         # Unit tests will check themselves.
         # Do not run if disabled in options.
@@ -102,7 +102,7 @@ class hierarchy_design(spice, layout):
 
     def LVS(self, final_verification=False):
         """Checks LVS for a module"""
-        import verify
+        from openram import verify
 
         # Unit tests will check themselves.
         # Do not run if disabled in options.

compiler/base/hierarchy_layout.py

@@ -5,28 +5,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os
 import sys
+import os
 import re
 from math import sqrt
-import debug
-from gdsMill import gdsMill
-import tech
-from tech import drc, GDS
-from tech import layer as tech_layer
-from tech import layer_indices as tech_layer_indices
-from tech import preferred_directions
-from tech import layer_stacks as tech_layer_stacks
-from tech import active_stack as tech_active_stack
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.gdsMill import gdsMill
+from openram import tech
+from openram.tech import drc, GDS
+from openram.tech import layer as tech_layer
+from openram.tech import layer_indices as tech_layer_indices
+from openram.tech import preferred_directions
+from openram.tech import layer_stacks as tech_layer_stacks
+from openram.tech import active_stack as tech_active_stack
+from openram.sram_factory import factory
+from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
 from .utils import round_to_grid
 from . import geometry
 
 try:
-    from tech import special_purposes
+    from openram.tech import special_purposes
 except ImportError:
     special_purposes = {}
 
@@ -171,7 +171,7 @@ class layout():
         in many places in the compiler.
         """
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             layout.pwr_grid_layers = [power_grid[0], power_grid[2]]
         except ImportError:
             layout.pwr_grid_layers = ["m3", "m4"]
@@ -1253,7 +1253,7 @@ class layout():
 
     def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None):
         """ Add a three layer via structure. """
-        from sram_factory import factory
+        from openram.sram_factory import factory
         via = factory.create(module_type="contact",
                              layer_stack=layers,
                              dimensions=size,
@@ -1272,7 +1272,7 @@ class layout():
         Add a three layer via structure by the center coordinate
         accounting for mirroring and rotation.
         """
-        from sram_factory import factory
+        from openram.sram_factory import factory
         via = factory.create(module_type="contact",
                              layer_stack=layers,
                              dimensions=size,
@@ -1379,10 +1379,10 @@ class layout():
 
     def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
         """Adds a ptx module to the design."""
-        import ptx
-        mos = ptx.ptx(width=width,
-                      mults=mults,
-                      tx_type=tx_type)
+        from openram.modules import ptx
+        mos = ptx(width=width,
+                  mults=mults,
+                  tx_type=tx_type)
         inst = self.add_inst(name=mos.name,
                              mod=mos,
                              offset=offset,
@@ -2176,7 +2176,7 @@ class layout():
 
         # Find the number of vias for this pitch
         supply_vias = 1
-        from sram_factory import factory
+        from openram.sram_factory import factory
         while True:
             c = factory.create(module_type="contact",
                                layer_stack=self.m1_stack,
@@ -2289,7 +2289,7 @@ class layout():
 
         # Find the number of vias for this pitch
         self.supply_vias = 1
-        from sram_factory import factory
+        from openram.sram_factory import factory
         while True:
             c = factory.create(module_type="contact",
                                layer_stack=self.m1_stack,

compiler/base/hierarchy_spice.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-import re
 import os
+import re
 import math
-import tech
-from globals import OPTS
 from pprint import pformat
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .delay_data import delay_data
 from .wire_spice_model import wire_spice_model
 from .power_data import power_data
@@ -37,7 +37,7 @@ class spice():
         # If we have a separate lvs directory, then all the lvs files
         # should be in there (all or nothing!)
         try:
-            from tech import lvs_name
+            from openram.tech import lvs_name
             lvs_dir = OPTS.openram_tech + lvs_name + "_lvs_lib/"
         except ImportError:
             lvs_dir = OPTS.openram_tech + "lvs_lib/"

compiler/base/lef.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import pin_layout
-from tech import layer_names
 import os
 import shutil
-from globals import OPTS
+from openram import debug
+from openram.base import vector
+from openram.base import pin_layout
+from openram.tech import layer_names
+from openram import OPTS
 
 
 class lef:
@@ -64,7 +64,7 @@ class lef:
         f.write('puts "Finished writing LEF cell {}"\n'.format(self.name))
         f.close()
         os.system("chmod u+x {}".format(run_file))
-        from run_script import run_script
+        from openram.verify.run_script import run_script
         (outfile, errfile, resultsfile) = run_script(self.name, "lef")
 
     def lef_write(self, lef_name):

compiler/base/logical_effort.py

@@ -5,8 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import parameter
+from openram import debug
+from openram.tech import parameter
+
 
 class logical_effort():
     """

compiler/base/pin_layout.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import GDS, drc
-from .vector import vector
-from tech import layer, layer_indices
 import math
+from openram import debug
+from openram.tech import GDS, drc
+from openram.tech import layer, layer_indices
+from .vector import vector
 
 
 class pin_layout:
@@ -48,8 +48,8 @@ class pin_layout:
 
             else:
                 try:
-                    from tech import layer_override
-                    from tech import layer_override_name
+                    from openram.tech import layer_override
+                    from openram.tech import layer_override_name
                     if layer_override[name]:
                        self.lpp = layer_override[name]
                        self.layer = "pwellp"
@@ -406,15 +406,15 @@ class pin_layout:
         # Try to use a global pin purpose if it exists,
         # otherwise, use the regular purpose
         try:
-            from tech import pin_purpose as global_pin_purpose
+            from openram.tech import pin_purpose as global_pin_purpose
             pin_purpose = global_pin_purpose
         except ImportError:
             pass
 
         try:
-            from tech import label_purpose
+            from openram.tech import label_purpose
             try:
-                from tech import layer_override_purpose
+                from openram.tech import layer_override_purpose
                 if pin_layer_num in layer_override_purpose:
                     layer_num = layer_override_purpose[pin_layer_num][0]
                     label_purpose = layer_override_purpose[pin_layer_num][1]

compiler/base/route.py

@@ -5,13 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from itertools import tee
+from openram import debug
+from openram.sram_factory import factory
+from openram.tech import drc
 from .design import design
 from .vector import vector
 from .vector3d import vector3d
-from tech import drc
-from itertools import tee
-from sram_factory import factory
+
 
 class route(design):
     """

compiler/base/timing_graph.py

@@ -1,6 +1,6 @@
 import copy
 from collections import defaultdict
-import debug
+from openram import debug
 
 
 class timing_graph():

compiler/base/utils.py

@@ -4,21 +4,19 @@
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
-
+#
 import os
 import math
-
-from gdsMill import gdsMill
-import tech
-import globals
-import debug
+from openram import debug
+from openram import tech
+from openram.gdsMill import gdsMill
+from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
 try:
-    from tech import special_purposes
+    from openram.tech import special_purposes
 except ImportError:
     special_purposes = {}
-OPTS = globals.OPTS
 
 
 def ceil(decimal):
@@ -159,7 +157,7 @@ def get_gds_pins(pin_names, name, gds_filename, units):
                     # may have must-connect pins
                     if isinstance(lpp[1], list):
                         try:
-                            from tech import layer_override
+                            from openram.tech import layer_override
                             if layer_override[pin_name]:
                                 lpp = layer_override[pin_name.textString]
                         except:

compiler/base/vector.py

@@ -5,9 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
 import math
-import tech
+from openram import tech
 
 
 class vector():

compiler/base/verilog.py

@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 import math
-from tech import spice
+from openram.tech import spice
 
 
 class verilog:

compiler/base/wire.py

@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from tech import drc
+from openram.tech import drc
+from openram.sram_factory import factory
 from .wire_path import wire_path
-from sram_factory import factory
 
 
 class wire(wire_path):
@@ -71,7 +71,7 @@ class wire(wire_path):
 
         # This is here for the unit tests which may not have
         # initialized the static parts of the layout class yet.
-        from base import layout
+        from openram.base import layout
         layout("fake", "fake")
 
         (layer1, via, layer2) = layer_stack

compiler/base/wire_path.py

@@ -5,11 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .vector import vector
-from .utils import snap_to_grid
+from openram.tech import drc
+from openram.tech import layer as techlayer
 from .design import design
-from tech import drc
-from tech import layer as techlayer
+from .utils import snap_to_grid
+from .vector import vector
+
 
 def create_rectilinear_route(my_list):
     """ Add intermediate nodes if it isn't rectilinear. Also skip

compiler/base/wire_spice_model.py

@@ -16,14 +16,14 @@ class wire_spice_model():
         self.wire_r = self.cal_wire_r(wire_length, wire_width) # r in each segment
 
     def cal_wire_c(self, wire_length, wire_width):
-        from tech import spice
+        from openram.tech import spice
         # Convert the F/um^2 to fF/um^2 then multiple by width and length
         total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width
         wire_c = total_c / self.lump_num
         return wire_c
 
     def cal_wire_r(self, wire_length, wire_width):
-        from tech import spice
+        from openram.tech import spice
         total_r = spice["wire_unit_r"] * wire_length / wire_width
         wire_r = total_r / self.lump_num
         return wire_r

compiler/characterizer/__init__.py

@@ -6,8 +6,8 @@
 # All rights reserved.
 #
 import os
-import debug
-from globals import OPTS, find_exe, get_tool
+from openram import debug
+from openram import OPTS, find_exe, get_tool
 from .lib import *
 from .delay import *
 from .elmore import *
@@ -56,4 +56,3 @@ if not OPTS.analytical_delay:
 else:
     debug.info(1, "Analytical model enabled.")
 
-

compiler/characterizer/analytical_util.py

@@ -4,13 +4,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-import debug
-
+import os
 import csv
 import math
 import numpy as np
-import os
+from openram import debug
+
 
 process_transform = {'SS':0.0, 'TT': 0.5, 'FF':1.0}
 

compiler/characterizer/cacti.py

@@ -5,13 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .simulation import simulation
-from globals import OPTS
-import debug
-import tech
-
 import math
+from openram import debug
+from openram import tech
+from openram import OPTS
+from .simulation import simulation
+
 
 class cacti(simulation):
     """

compiler/characterizer/charutils.py

@@ -7,8 +7,8 @@
 #
 import os
 import re
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 
 
 def relative_compare(value1, value2, error_tolerance=0.001):

compiler/characterizer/delay.py

@@ -5,16 +5,16 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import shutil
-import debug
-import tech
 import math
+import shutil
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .stimuli import *
 from .trim_spice import *
 from .charutils import *
 from .sram_op import *
 from .bit_polarity import *
-from globals import OPTS
 from .simulation import simulation
 from .measurements import *
 

compiler/characterizer/elmore.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
+from openram import debug
+from openram import OPTS
 from .simulation import simulation
-from globals import OPTS
-import debug
+
 
 class elmore(simulation):
     """

compiler/characterizer/functional.py

@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import collections
-import debug
-import random
 import math
+import random
+import collections
 from numpy import binary_repr
+from openram import debug
+from openram import OPTS
 from .stimuli import *
 from .charutils import *
-from globals import OPTS
 from .simulation import simulation
 
 

compiler/characterizer/lib.py

@@ -5,17 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os,sys,re
+import os, sys, re
 import time
-import debug
 import datetime
+import numpy as np
+from openram import debug
+from openram import tech
+from openram.tech import spice
+from openram import OPTS
 from .setup_hold import *
 from .delay import *
 from .charutils import *
-import tech
-import numpy as np
-from globals import OPTS
-from tech import spice
 
 
 class lib:

compiler/characterizer/linear_regression.py

@@ -5,13 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .regression_model import regression_model
 from sklearn.linear_model import Ridge
-from globals import OPTS
-import debug
-
 from sklearn.linear_model import LinearRegression
+from openram import debug
+from openram import OPTS
+from .regression_model import regression_model
 
 
 class linear_regression(regression_model):

compiler/characterizer/measurements.py

@@ -5,12 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import drc, parameter, spice
 from abc import ABC, abstractmethod
+from openram import debug
+from openram.tech import drc, parameter, spice
 from .stimuli import *
 from .charutils import *
 
+
 class spice_measurement(ABC):
     """Base class for spice stimulus measurements."""
     def __init__(self, measure_name, measure_scale=None, has_port=True):

compiler/characterizer/model_check.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-import tech
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .stimuli import *
 from .trim_spice import *
 from .charutils import *
-from globals import OPTS
 from .delay import delay
 from .measurements import *
 

compiler/characterizer/neural_network.py

@@ -5,11 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .regression_model import regression_model
-from globals import OPTS
-import debug
 from sklearn.neural_network import MLPRegressor
+from openram import debug
+from openram import OPTS
+from .regression_model import regression_model
 
 
 class neural_network(regression_model):

compiler/characterizer/regression_model.py

@@ -5,13 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
+import math
+from openram import debug
+from openram import OPTS
 from .analytical_util import *
 from .simulation import simulation
-from globals import OPTS
-import debug
 
-import math
 
 relative_data_path = "sim_data"
 data_file = "sim_data.csv"

compiler/characterizer/setup_hold.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import tech
+from openram import debug
+from openram.sram_factory import factory
+from openram import tech
+from openram import OPTS
 from .stimuli import *
-import debug
 from .charutils import *
-from globals import OPTS
-from sram_factory import factory
 
 
 class setup_hold():

compiler/characterizer/simulation.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
 import math
-import tech
-from globals import OPTS
-from sram_factory import factory
-from base import timing_graph
+from openram import debug
+from openram.base import timing_graph
+from openram.sram_factory import factory
+from openram import tech
+from openram import OPTS
 
 
 class simulation():

compiler/characterizer/stimuli.py

@@ -11,12 +11,12 @@ various functions that can be be used to generate stimulus for other
 simulations as well.
 """
 
-import tech
-import debug
-import subprocess
 import os
+import subprocess
 import numpy as np
-from globals import OPTS
+from openram import debug
+from openram import tech
+from openram import OPTS
 
 
 class stimuli():

compiler/characterizer/trim_spice.py

@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from math import log,ceil
 import re
+from math import log, ceil
+from openram import debug
 
 
 class trim_spice():

compiler/datasheet/add_db.py

@@ -5,10 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from pathlib import Path
-import glob
-import os
 import sys
+import os
+import glob
+from pathlib import Path
+
 
 # This is the path to the directory you would like to search
 # This directory is searched recursively for .html files

compiler/datasheet/datasheet.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .table_gen import *
 import os
 import base64
-from globals import OPTS
+from openram import OPTS
+from .table_gen import *
 
 
 class datasheet():

compiler/datasheet/datasheet_gen.py

@@ -15,10 +15,10 @@ a web friendly html datasheet.
 # Improve css
 
 
-from globals import OPTS
 import os
 import math
 import csv
+from openram import OPTS
 from .datasheet import datasheet
 from .table_gen import table_gen
 

compiler/datasheet/table_gen.py

@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class table_gen:
     """small library of functions to generate the html tables"""
 

compiler/debug.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os
-import inspect
-import globals
 import sys
+import os
 import pdb
+import inspect
+from openram import globals
 
 # the debug levels:
 # 0 = minimum output (default)
@@ -96,7 +96,7 @@ log.create_file = True
 
 
 def info(lev, str):
-    from globals import OPTS
+    from openram.globals import OPTS
     # 99 is a special never print level
     if lev == 99:
         return
@@ -114,7 +114,7 @@ def info(lev, str):
 
 
 def archive():
-    from globals import OPTS
+    from openram.globals import OPTS
     try:
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
     except:

compiler/drc/custom_layer_properties.py

@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class _bank:
     def __init__(self, stack, pitch):
         # bank

compiler/drc/design_rules.py

@@ -5,7 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
 from .drc_value import *
 from .drc_lut import *
 

compiler/drc/drc_lut.py

@@ -5,7 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
 
 
 class drc_lut():

compiler/drc/drc_value.py

@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class drc_value():
     """
     A single DRC value.

compiler/gdsMill/gdsMill/pdfLayout.py

@@ -1,8 +1,8 @@
-import pyx
 import math
-from numpy import matrix
-from gdsPrimitives import *
 import random
+from numpy import matrix
+from openram.gdsMill import pyx
+from .gdsPrimitives import *
 
 class pdfLayout:
     """Class representing a view for a layout as a PDF"""

compiler/gdsMill/gdsMill/vlsiLayout.py

@@ -1,8 +1,8 @@
-from .gdsPrimitives import *
+import math
 from datetime import *
 import numpy as np
-import math
-import debug
+from openram import debug
+from .gdsPrimitives import *
 
 
 class VlsiLayout:
@@ -774,7 +774,7 @@ class VlsiLayout:
             else:
                 label_text = label.textString
             try:
-                from tech import layer_override
+                from openram.tech import layer_override
                 if layer_override[label_text]:
                     shapes = self.getAllShapes((layer_override[label_text][0], None))
                     if not shapes:

compiler/globals.py

@@ -9,17 +9,17 @@
 This is called globals.py, but it actually parses all the arguments
 and performs the global OpenRAM setup as well.
 """
+import sys
 import os
-import debug
+import re
 import shutil
 import optparse
-import options
-import sys
-import re
 import copy
 import importlib
 import getpass
 import subprocess
+from openram import debug
+from openram import options
 
 
 VERSION = "1.2.0"
@@ -202,7 +202,7 @@ def init_openram(config_file, is_unit_test=False):
 
     init_paths()
 
-    from sram_factory import factory
+    from openram.sram_factory import factory
     factory.reset()
 
     global OPTS
@@ -222,8 +222,8 @@ def init_openram(config_file, is_unit_test=False):
     setup_bitcell()
 
     # Import these to find the executables for checkpointing
-    import characterizer
-    import verify
+    from openram import characterizer
+    from openram import verify
     # Make a checkpoint of the options so we can restore
     # after each unit test
     if not CHECKPOINT_OPTS:
@@ -249,7 +249,7 @@ def setup_bitcell():
 
     # See if bitcell exists
     try:
-        c = importlib.import_module("modules." + OPTS.bitcell)
+        c = importlib.import_module("openram.modules." + OPTS.bitcell)
         mod = getattr(c, OPTS.bitcell)
     except ImportError:
         # Use the pbitcell if we couldn't find a custom bitcell
@@ -385,7 +385,7 @@ def end_openram():
     cleanup_paths()
 
     if OPTS.check_lvsdrc:
-        import verify
+        from openram import verify
         verify.print_drc_stats()
         verify.print_lvs_stats()
         verify.print_pex_stats()
@@ -429,24 +429,9 @@ def setup_paths():
 
     global OPTS
 
-    # If $OPENRAM_HOME is defined, use that path for the source code.
-    # Otherwise, use the openram package.
-    try:
-        OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
-    except:
-        import openram
-        OPENRAM_HOME = os.path.dirname(openram.__file__) + "/compiler"
-        # Add this directory to os.environ here
-        os.environ["OPENRAM_HOME"] = OPENRAM_HOME
-
-    debug.check(os.path.isdir(OPENRAM_HOME),
-                "$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME))
+    from openram import OPENRAM_HOME
     debug.info(1, "OpenRAM source code found in {}".format(OPENRAM_HOME))
 
-    if OPENRAM_HOME not in sys.path:
-        sys.path.insert(0, OPENRAM_HOME)
-        debug.info(2, "Adding source code to PYTHONPATH.")
-
     # Use a unique temp subdirectory if multithreaded
     if OPTS.num_threads > 1 or OPTS.openram_temp == "/tmp":
 
@@ -515,7 +500,7 @@ def init_paths():
 def set_default_corner():
     """ Set the default corner. """
 
-    import tech
+    from openram import tech
     # Set some default options now based on the technology...
     if (OPTS.process_corners == ""):
         if OPTS.nominal_corner_only:
@@ -548,8 +533,7 @@ def import_tech():
     """ Dynamically adds the tech directory to the path and imports it. """
     global OPTS
 
-    debug.info(2,
-               "Importing technology: " + OPTS.tech_name)
+    debug.info(2, "Importing technology: " + OPTS.tech_name)
 
     OPENRAM_TECH = ""
 
@@ -591,18 +575,23 @@ def import_tech():
 
     OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/"
 
-    # Prepend the tech directory so it is sourced FIRST
+    # Append tech_path to openram.__path__ to import it from openram
     tech_path = OPTS.openram_tech
-    sys.path.insert(0, tech_path)
+    openram.__path__.append(tech_path)
     try:
-        import tech
+        from openram import tech
     except ImportError:
         debug.error("Could not load tech module.", -1)
 
-    # Prepend custom modules of the technology to the path, if they exist
-    custom_mod_path = os.path.join(tech_path, "modules/")
+    # Remove OPENRAM_TECH from sys.path because we should be done with those
+    for tech_path in OPENRAM_TECH.split(":"):
+        sys.path.remove(tech_path)
+
+    # Add the custom modules to "tech"
+    custom_mod_path = os.path.join(tech_path, "custom/")
     if os.path.exists(custom_mod_path):
-        sys.path.insert(0, custom_mod_path)
+        from openram import tech
+        tech.__path__.append(custom_mod_path)
 
 
 def print_time(name, now_time, last_time=None, indentation=2):

compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 10
 num_words = 64
 words_per_row = 4

compiler/model_configs/sram_128b_1024_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 128
 num_words = 1024
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 12
 num_words = 128
 words_per_row = 4

compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 12
 num_words = 16
 words_per_row = 1

compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 12
 num_words = 256
 words_per_row = 16

compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 12
 num_words = 256
 words_per_row = 8

compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 14
 num_words = 32
 words_per_row = 2

compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 15
 num_words = 512
 words_per_row = 8

compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 16
 num_words = 1024
 words_per_row = 16

compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 17
 num_words = 1024
 words_per_row = 16

compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 17
 num_words = 256
 words_per_row = 16

compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 18
 num_words = 128
 words_per_row = 2

compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 18
 num_words = 32
 words_per_row = 1

compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 21
 num_words = 1024
 words_per_row = 4

compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 22
 num_words = 512
 words_per_row = 16

compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 23
 num_words = 1024
 words_per_row = 16

compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 26
 num_words = 64
 words_per_row = 4

compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 27
 num_words = 1024
 words_per_row = 4

compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 27
 num_words = 256
 words_per_row = 8

compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 27
 num_words = 512
 words_per_row = 4

compiler/model_configs/sram_32b_2048_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 32
 num_words = 2048
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_256_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 32
 num_words = 256
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 32
 num_words = 32
 words_per_row = 1

compiler/model_configs/sram_32b_512_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 32
 num_words = 512
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 4
 num_words = 16
 words_per_row = 1

compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 4
 num_words = 32
 words_per_row = 2

compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 4
 num_words = 64
 words_per_row = 4

compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 5
 num_words = 256
 words_per_row = 16

compiler/model_configs/sram_64b_1024_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 64
 num_words = 1024
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_64b_512_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 64
 num_words = 512
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 6
 num_words = 16
 words_per_row = 1

compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 7
 num_words = 256
 words_per_row = 4

compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 7
 num_words = 64
 words_per_row = 2

compiler/model_configs/sram_8b_1024_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 8
 num_words = 1024
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_8b_256_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 8
 num_words = 256
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 8
 num_words = 256
 words_per_row = 1

compiler/model_configs/sram_8b_512_1rw.py

@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 8
 num_words = 512
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 9
 num_words = 1024
 words_per_row = 4

compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 9
 num_words = 128
 words_per_row = 1

compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py

@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 9
 num_words = 256
 words_per_row = 4

compiler/modules/and2_dec.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import design
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import vector
+from openram.base import design
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and2_dec(design):

compiler/modules/and3_dec.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and3_dec(design):

compiler/modules/and4_dec.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and4_dec(design):

compiler/modules/bank.py

@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
 from math import log, ceil, floor
-from tech import drc
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class bank(design):

compiler/modules/bitcell_1port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/bitcell_2port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/bitcell_array.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.tech import drc, spice
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from globals import OPTS
-from sram_factory import factory
 
 
 class bitcell_array(bitcell_base_array):

compiler/modules/bitcell_base.py

@@ -5,12 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-import debug
-from base import design
-from globals import OPTS
-from base import logical_effort
-from tech import parameter, drc, layer, spice
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import parameter, drc, layer, spice
+from openram import OPTS
 
 
 class bitcell_base(design):
@@ -46,7 +45,7 @@ class bitcell_base(design):
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
+        from openram.tech import spice
         leakage = spice["bitcell_leakage"]
         # FIXME
         dynamic = 0

compiler/modules/bitcell_base_array.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class bitcell_base_array(design):

compiler/modules/col_cap_array.py

@@ -3,9 +3,9 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class col_cap_array(bitcell_base_array):

compiler/modules/col_cap_bitcell_1port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base