diff --git a/__init__.py b/__init__.py
index 413d84e6..4345fc4a 100644
--- a/__init__.py
+++ b/__init__.py
@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 import os
-import sys
 
 # Attempt to add the source code to the PYTHONPATH here before running globals.init_openram().
 try:
@@ -17,8 +16,12 @@ except:
 if not os.path.isdir(OPENRAM_HOME):
     assert False
 
-if OPENRAM_HOME not in sys.path:
-    sys.path.insert(0, OPENRAM_HOME)
+# Make sure that OPENRAM_HOME is an environment variable just in case
+if "OPENRAM_HOME" not in os.environ.keys():
+    os.environ["OPENRAM_HOME"] = OPENRAM_HOME
 
-# Export everything in globals.py as part of "openram"
-from globals import *
+# Prepend $OPENRAM_HOME to __path__ so that openram will use those modules
+__path__.insert(0, OPENRAM_HOME)
+
+# Import everything in globals.py
+from .globals import *
diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py
index 7cd1fb53..de700769 100644
--- a/compiler/base/channel_route.py
+++ b/compiler/base/channel_route.py
@@ -6,8 +6,8 @@
 # All rights reserved.
 #
 import collections
-import debug
-from tech import drc
+from openram import debug
+from openram.tech import drc
 from .vector import vector
 from .design import design
 
@@ -405,4 +405,3 @@ class channel_route(design):
                                       to_layer=self.horizontal_layer,
                                       offset=pin_pos)
 
-
diff --git a/compiler/base/contact.py b/compiler/base/contact.py
index 5f2f41d0..4e13b77d 100644
--- a/compiler/base/contact.py
+++ b/compiler/base/contact.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.tech import drc, layer, preferred_directions
+from openram.tech import layer as tech_layers
 from .hierarchy_design import hierarchy_design
 from .vector import vector
-from tech import drc, layer, preferred_directions
-from tech import layer as tech_layers
 
 
 class contact(hierarchy_design):
diff --git a/compiler/base/delay_data.py b/compiler/base/delay_data.py
index 9e963265..128c65b8 100644
--- a/compiler/base/delay_data.py
+++ b/compiler/base/delay_data.py
@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class delay_data():
     """
     This is the delay class to represent the delay information
@@ -38,7 +37,3 @@ class delay_data():
         assert isinstance(other, delay_data)
         return delay_data(other.delay + self.delay,
                           self.slew)
-
-
-
-
diff --git a/compiler/base/design.py b/compiler/base/design.py
index 89f7ba82..227e08a4 100644
--- a/compiler/base/design.py
+++ b/compiler/base/design.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import GDS, layer
-from tech import preferred_directions
-from tech import cell_properties as props
-from globals import OPTS
+from openram import debug
+from openram.tech import GDS, layer
+from openram.tech import preferred_directions
+from openram.tech import cell_properties as props
+from openram import OPTS
 from . import utils
 from .hierarchy_design import hierarchy_design
 
@@ -67,7 +67,7 @@ class design(hierarchy_design):
         self.setup_multiport_constants()
 
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             self.supply_stack = power_grid
         except ImportError:
             # if no power_grid is specified by tech we use sensible defaults
diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py
index 7451d465..7114d5ae 100644
--- a/compiler/base/geometry.py
+++ b/compiler/base/geometry.py
@@ -8,14 +8,14 @@
 """
 This provides a set of useful generic types for the gdsMill interface.
 """
-import debug
-from .vector import vector
-import tech
 import math
 import copy
 import numpy as np
-from globals import OPTS
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .utils import round_to_grid
+from .vector import vector
 
 
 class geometry:
diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index c25864f9..be533235 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import os
+from openram import debug
+from openram import OPTS
 from .hierarchy_layout import layout
 from .hierarchy_spice import spice
-import debug
-import os
-from globals import OPTS
 
 
 class hierarchy_design(spice, layout):
@@ -49,7 +49,7 @@ class hierarchy_design(spice, layout):
 
     def DRC_LVS(self, final_verification=False, force_check=False):
         """Checks both DRC and LVS for a module"""
-        import verify
+        from openram import verify
 
         # No layout to check
         if OPTS.netlist_only:
@@ -82,7 +82,7 @@ class hierarchy_design(spice, layout):
 
     def DRC(self, final_verification=False):
         """Checks DRC for a module"""
-        import verify
+        from openram import verify
 
         # Unit tests will check themselves.
         # Do not run if disabled in options.
@@ -102,7 +102,7 @@ class hierarchy_design(spice, layout):
 
     def LVS(self, final_verification=False):
         """Checks LVS for a module"""
-        import verify
+        from openram import verify
 
         # Unit tests will check themselves.
         # Do not run if disabled in options.
diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index c0da0244..0ec24657 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -5,28 +5,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os
 import sys
+import os
 import re
 from math import sqrt
-import debug
-from gdsMill import gdsMill
-import tech
-from tech import drc, GDS
-from tech import layer as tech_layer
-from tech import layer_indices as tech_layer_indices
-from tech import preferred_directions
-from tech import layer_stacks as tech_layer_stacks
-from tech import active_stack as tech_active_stack
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.gdsMill import gdsMill
+from openram import tech
+from openram.tech import drc, GDS
+from openram.tech import layer as tech_layer
+from openram.tech import layer_indices as tech_layer_indices
+from openram.tech import preferred_directions
+from openram.tech import layer_stacks as tech_layer_stacks
+from openram.tech import active_stack as tech_active_stack
+from openram.sram_factory import factory
+from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
 from .utils import round_to_grid
 from . import geometry
 
 try:
-    from tech import special_purposes
+    from openram.tech import special_purposes
 except ImportError:
     special_purposes = {}
 
@@ -171,7 +171,7 @@ class layout():
         in many places in the compiler.
         """
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             layout.pwr_grid_layers = [power_grid[0], power_grid[2]]
         except ImportError:
             layout.pwr_grid_layers = ["m3", "m4"]
@@ -1253,7 +1253,7 @@ class layout():
 
     def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None):
         """ Add a three layer via structure. """
-        from sram_factory import factory
+        from openram.sram_factory import factory
         via = factory.create(module_type="contact",
                              layer_stack=layers,
                              dimensions=size,
@@ -1272,7 +1272,7 @@ class layout():
         Add a three layer via structure by the center coordinate
         accounting for mirroring and rotation.
         """
-        from sram_factory import factory
+        from openram.sram_factory import factory
         via = factory.create(module_type="contact",
                              layer_stack=layers,
                              dimensions=size,
@@ -1379,10 +1379,10 @@ class layout():
 
     def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
         """Adds a ptx module to the design."""
-        import ptx
-        mos = ptx.ptx(width=width,
-                      mults=mults,
-                      tx_type=tx_type)
+        from openram.modules import ptx
+        mos = ptx(width=width,
+                  mults=mults,
+                  tx_type=tx_type)
         inst = self.add_inst(name=mos.name,
                              mod=mos,
                              offset=offset,
@@ -2176,7 +2176,7 @@ class layout():
 
         # Find the number of vias for this pitch
         supply_vias = 1
-        from sram_factory import factory
+        from openram.sram_factory import factory
         while True:
             c = factory.create(module_type="contact",
                                layer_stack=self.m1_stack,
@@ -2289,7 +2289,7 @@ class layout():
 
         # Find the number of vias for this pitch
         self.supply_vias = 1
-        from sram_factory import factory
+        from openram.sram_factory import factory
         while True:
             c = factory.create(module_type="contact",
                                layer_stack=self.m1_stack,
diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py
index 1216edc5..874042e4 100644
--- a/compiler/base/hierarchy_spice.py
+++ b/compiler/base/hierarchy_spice.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-import re
 import os
+import re
 import math
-import tech
-from globals import OPTS
 from pprint import pformat
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .delay_data import delay_data
 from .wire_spice_model import wire_spice_model
 from .power_data import power_data
@@ -37,7 +37,7 @@ class spice():
         # If we have a separate lvs directory, then all the lvs files
         # should be in there (all or nothing!)
         try:
-            from tech import lvs_name
+            from openram.tech import lvs_name
             lvs_dir = OPTS.openram_tech + lvs_name + "_lvs_lib/"
         except ImportError:
             lvs_dir = OPTS.openram_tech + "lvs_lib/"
diff --git a/compiler/base/lef.py b/compiler/base/lef.py
index 9ebd823d..df8ea0ad 100644
--- a/compiler/base/lef.py
+++ b/compiler/base/lef.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import pin_layout
-from tech import layer_names
 import os
 import shutil
-from globals import OPTS
+from openram import debug
+from openram.base import vector
+from openram.base import pin_layout
+from openram.tech import layer_names
+from openram import OPTS
 
 
 class lef:
@@ -64,7 +64,7 @@ class lef:
         f.write('puts "Finished writing LEF cell {}"\n'.format(self.name))
         f.close()
         os.system("chmod u+x {}".format(run_file))
-        from run_script import run_script
+        from openram.verify.run_script import run_script
         (outfile, errfile, resultsfile) = run_script(self.name, "lef")
 
     def lef_write(self, lef_name):
diff --git a/compiler/base/logical_effort.py b/compiler/base/logical_effort.py
index 15f2b209..e000e812 100644
--- a/compiler/base/logical_effort.py
+++ b/compiler/base/logical_effort.py
@@ -5,8 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import parameter
+from openram import debug
+from openram.tech import parameter
+
 
 class logical_effort():
     """
diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py
index 4021a8b5..c8377b19 100644
--- a/compiler/base/pin_layout.py
+++ b/compiler/base/pin_layout.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import GDS, drc
-from .vector import vector
-from tech import layer, layer_indices
 import math
+from openram import debug
+from openram.tech import GDS, drc
+from openram.tech import layer, layer_indices
+from .vector import vector
 
 
 class pin_layout:
@@ -48,8 +48,8 @@ class pin_layout:
 
             else:
                 try:
-                    from tech import layer_override
-                    from tech import layer_override_name
+                    from openram.tech import layer_override
+                    from openram.tech import layer_override_name
                     if layer_override[name]:
                        self.lpp = layer_override[name]
                        self.layer = "pwellp"
@@ -406,15 +406,15 @@ class pin_layout:
         # Try to use a global pin purpose if it exists,
         # otherwise, use the regular purpose
         try:
-            from tech import pin_purpose as global_pin_purpose
+            from openram.tech import pin_purpose as global_pin_purpose
             pin_purpose = global_pin_purpose
         except ImportError:
             pass
 
         try:
-            from tech import label_purpose
+            from openram.tech import label_purpose
             try:
-                from tech import layer_override_purpose
+                from openram.tech import layer_override_purpose
                 if pin_layer_num in layer_override_purpose:
                     layer_num = layer_override_purpose[pin_layer_num][0]
                     label_purpose = layer_override_purpose[pin_layer_num][1]
diff --git a/compiler/base/route.py b/compiler/base/route.py
index 2a6376e3..faef9486 100644
--- a/compiler/base/route.py
+++ b/compiler/base/route.py
@@ -5,13 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from itertools import tee
+from openram import debug
+from openram.sram_factory import factory
+from openram.tech import drc
 from .design import design
 from .vector import vector
 from .vector3d import vector3d
-from tech import drc
-from itertools import tee
-from sram_factory import factory
+
 
 class route(design):
     """
diff --git a/compiler/base/timing_graph.py b/compiler/base/timing_graph.py
index 46d7b518..e645bd05 100644
--- a/compiler/base/timing_graph.py
+++ b/compiler/base/timing_graph.py
@@ -1,6 +1,6 @@
 import copy
 from collections import defaultdict
-import debug
+from openram import debug
 
 
 class timing_graph():
diff --git a/compiler/base/utils.py b/compiler/base/utils.py
index 082caf21..396d4eaf 100644
--- a/compiler/base/utils.py
+++ b/compiler/base/utils.py
@@ -4,21 +4,19 @@
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
-
+#
 import os
 import math
-
-from gdsMill import gdsMill
-import tech
-import globals
-import debug
+from openram import debug
+from openram import tech
+from openram.gdsMill import gdsMill
+from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
 try:
-    from tech import special_purposes
+    from openram.tech import special_purposes
 except ImportError:
     special_purposes = {}
-OPTS = globals.OPTS
 
 
 def ceil(decimal):
@@ -159,7 +157,7 @@ def get_gds_pins(pin_names, name, gds_filename, units):
                     # may have must-connect pins
                     if isinstance(lpp[1], list):
                         try:
-                            from tech import layer_override
+                            from openram.tech import layer_override
                             if layer_override[pin_name]:
                                 lpp = layer_override[pin_name.textString]
                         except:
diff --git a/compiler/base/vector.py b/compiler/base/vector.py
index 5d011a09..0d76f377 100644
--- a/compiler/base/vector.py
+++ b/compiler/base/vector.py
@@ -5,9 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
 import math
-import tech
+from openram import tech
 
 
 class vector():
diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py
index b93b52e9..6732525a 100644
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 import math
-from tech import spice
+from openram.tech import spice
 
 
 class verilog:
diff --git a/compiler/base/wire.py b/compiler/base/wire.py
index a276c035..2372aa9e 100644
--- a/compiler/base/wire.py
+++ b/compiler/base/wire.py
@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from tech import drc
+from openram.tech import drc
+from openram.sram_factory import factory
 from .wire_path import wire_path
-from sram_factory import factory
 
 
 class wire(wire_path):
@@ -71,7 +71,7 @@ class wire(wire_path):
 
         # This is here for the unit tests which may not have
         # initialized the static parts of the layout class yet.
-        from base import layout
+        from openram.base import layout
         layout("fake", "fake")
 
         (layer1, via, layer2) = layer_stack
diff --git a/compiler/base/wire_path.py b/compiler/base/wire_path.py
index 363a41f3..ae633fd4 100644
--- a/compiler/base/wire_path.py
+++ b/compiler/base/wire_path.py
@@ -5,11 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .vector import vector
-from .utils import snap_to_grid
+from openram.tech import drc
+from openram.tech import layer as techlayer
 from .design import design
-from tech import drc
-from tech import layer as techlayer
+from .utils import snap_to_grid
+from .vector import vector
+
 
 def create_rectilinear_route(my_list):
     """ Add intermediate nodes if it isn't rectilinear. Also skip
diff --git a/compiler/base/wire_spice_model.py b/compiler/base/wire_spice_model.py
index 5e84b64b..8834c36f 100644
--- a/compiler/base/wire_spice_model.py
+++ b/compiler/base/wire_spice_model.py
@@ -16,14 +16,14 @@ class wire_spice_model():
         self.wire_r = self.cal_wire_r(wire_length, wire_width) # r in each segment
 
     def cal_wire_c(self, wire_length, wire_width):
-        from tech import spice
+        from openram.tech import spice
         # Convert the F/um^2 to fF/um^2 then multiple by width and length
         total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width
         wire_c = total_c / self.lump_num
         return wire_c
 
     def cal_wire_r(self, wire_length, wire_width):
-        from tech import spice
+        from openram.tech import spice
         total_r = spice["wire_unit_r"] * wire_length / wire_width
         wire_r = total_r / self.lump_num
         return wire_r
diff --git a/compiler/characterizer/__init__.py b/compiler/characterizer/__init__.py
index c052a0a0..1b8ec0bf 100644
--- a/compiler/characterizer/__init__.py
+++ b/compiler/characterizer/__init__.py
@@ -6,8 +6,8 @@
 # All rights reserved.
 #
 import os
-import debug
-from globals import OPTS, find_exe, get_tool
+from openram import debug
+from openram import OPTS, find_exe, get_tool
 from .lib import *
 from .delay import *
 from .elmore import *
@@ -56,4 +56,3 @@ if not OPTS.analytical_delay:
 else:
     debug.info(1, "Analytical model enabled.")
 
-
diff --git a/compiler/characterizer/analytical_util.py b/compiler/characterizer/analytical_util.py
index 11e58f73..a8610f59 100644
--- a/compiler/characterizer/analytical_util.py
+++ b/compiler/characterizer/analytical_util.py
@@ -4,13 +4,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-import debug
-
+import os
 import csv
 import math
 import numpy as np
-import os
+from openram import debug
+
 
 process_transform = {'SS':0.0, 'TT': 0.5, 'FF':1.0}
 
diff --git a/compiler/characterizer/cacti.py b/compiler/characterizer/cacti.py
index f1af8fbd..62371e7a 100644
--- a/compiler/characterizer/cacti.py
+++ b/compiler/characterizer/cacti.py
@@ -5,13 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .simulation import simulation
-from globals import OPTS
-import debug
-import tech
-
 import math
+from openram import debug
+from openram import tech
+from openram import OPTS
+from .simulation import simulation
+
 
 class cacti(simulation):
     """
diff --git a/compiler/characterizer/charutils.py b/compiler/characterizer/charutils.py
index 70f80774..17b0352a 100644
--- a/compiler/characterizer/charutils.py
+++ b/compiler/characterizer/charutils.py
@@ -7,8 +7,8 @@
 #
 import os
 import re
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 
 
 def relative_compare(value1, value2, error_tolerance=0.001):
diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 8d0aa536..8f2c4289 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -5,16 +5,16 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import shutil
-import debug
-import tech
 import math
+import shutil
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .stimuli import *
 from .trim_spice import *
 from .charutils import *
 from .sram_op import *
 from .bit_polarity import *
-from globals import OPTS
 from .simulation import simulation
 from .measurements import *
 
diff --git a/compiler/characterizer/elmore.py b/compiler/characterizer/elmore.py
index 5f9eabfd..9bee833e 100644
--- a/compiler/characterizer/elmore.py
+++ b/compiler/characterizer/elmore.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
+from openram import debug
+from openram import OPTS
 from .simulation import simulation
-from globals import OPTS
-import debug
+
 
 class elmore(simulation):
     """
diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py
index 0aa9ebcd..70ebb194 100644
--- a/compiler/characterizer/functional.py
+++ b/compiler/characterizer/functional.py
@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import collections
-import debug
-import random
 import math
+import random
+import collections
 from numpy import binary_repr
+from openram import debug
+from openram import OPTS
 from .stimuli import *
 from .charutils import *
-from globals import OPTS
 from .simulation import simulation
 
 
diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 8d8674b9..c1b5e429 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -5,17 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os,sys,re
+import os, sys, re
 import time
-import debug
 import datetime
+import numpy as np
+from openram import debug
+from openram import tech
+from openram.tech import spice
+from openram import OPTS
 from .setup_hold import *
 from .delay import *
 from .charutils import *
-import tech
-import numpy as np
-from globals import OPTS
-from tech import spice
 
 
 class lib:
diff --git a/compiler/characterizer/linear_regression.py b/compiler/characterizer/linear_regression.py
index 68921e2c..ed6555c2 100644
--- a/compiler/characterizer/linear_regression.py
+++ b/compiler/characterizer/linear_regression.py
@@ -5,13 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .regression_model import regression_model
 from sklearn.linear_model import Ridge
-from globals import OPTS
-import debug
-
 from sklearn.linear_model import LinearRegression
+from openram import debug
+from openram import OPTS
+from .regression_model import regression_model
 
 
 class linear_regression(regression_model):
diff --git a/compiler/characterizer/measurements.py b/compiler/characterizer/measurements.py
index fcbb562f..8bb83350 100644
--- a/compiler/characterizer/measurements.py
+++ b/compiler/characterizer/measurements.py
@@ -5,12 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import drc, parameter, spice
 from abc import ABC, abstractmethod
+from openram import debug
+from openram.tech import drc, parameter, spice
 from .stimuli import *
 from .charutils import *
 
+
 class spice_measurement(ABC):
     """Base class for spice stimulus measurements."""
     def __init__(self, measure_name, measure_scale=None, has_port=True):
diff --git a/compiler/characterizer/model_check.py b/compiler/characterizer/model_check.py
index 9ef48b1c..ed7a852d 100644
--- a/compiler/characterizer/model_check.py
+++ b/compiler/characterizer/model_check.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-import tech
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .stimuli import *
 from .trim_spice import *
 from .charutils import *
-from globals import OPTS
 from .delay import delay
 from .measurements import *
 
diff --git a/compiler/characterizer/neural_network.py b/compiler/characterizer/neural_network.py
index ae65b26d..5147cd1b 100644
--- a/compiler/characterizer/neural_network.py
+++ b/compiler/characterizer/neural_network.py
@@ -5,11 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .regression_model import regression_model
-from globals import OPTS
-import debug
 from sklearn.neural_network import MLPRegressor
+from openram import debug
+from openram import OPTS
+from .regression_model import regression_model
 
 
 class neural_network(regression_model):
diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py
index e9b4ec4d..1bc31c7c 100644
--- a/compiler/characterizer/regression_model.py
+++ b/compiler/characterizer/regression_model.py
@@ -5,13 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
+import math
+from openram import debug
+from openram import OPTS
 from .analytical_util import *
 from .simulation import simulation
-from globals import OPTS
-import debug
 
-import math
 
 relative_data_path = "sim_data"
 data_file = "sim_data.csv"
diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py
index ec1a9e5e..ff852e46 100644
--- a/compiler/characterizer/setup_hold.py
+++ b/compiler/characterizer/setup_hold.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import tech
+from openram import debug
+from openram.sram_factory import factory
+from openram import tech
+from openram import OPTS
 from .stimuli import *
-import debug
 from .charutils import *
-from globals import OPTS
-from sram_factory import factory
 
 
 class setup_hold():
diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py
index 5649099c..123323fe 100644
--- a/compiler/characterizer/simulation.py
+++ b/compiler/characterizer/simulation.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
 import math
-import tech
-from globals import OPTS
-from sram_factory import factory
-from base import timing_graph
+from openram import debug
+from openram.base import timing_graph
+from openram.sram_factory import factory
+from openram import tech
+from openram import OPTS
 
 
 class simulation():
diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py
index b9e4b3c7..335e1b0d 100644
--- a/compiler/characterizer/stimuli.py
+++ b/compiler/characterizer/stimuli.py
@@ -11,12 +11,12 @@ various functions that can be be used to generate stimulus for other
 simulations as well.
 """
 
-import tech
-import debug
-import subprocess
 import os
+import subprocess
 import numpy as np
-from globals import OPTS
+from openram import debug
+from openram import tech
+from openram import OPTS
 
 
 class stimuli():
diff --git a/compiler/characterizer/trim_spice.py b/compiler/characterizer/trim_spice.py
index affba296..b541c5a8 100644
--- a/compiler/characterizer/trim_spice.py
+++ b/compiler/characterizer/trim_spice.py
@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from math import log,ceil
 import re
+from math import log, ceil
+from openram import debug
 
 
 class trim_spice():
diff --git a/compiler/datasheet/add_db.py b/compiler/datasheet/add_db.py
index 7d689f4c..764bb311 100644
--- a/compiler/datasheet/add_db.py
+++ b/compiler/datasheet/add_db.py
@@ -5,10 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from pathlib import Path
-import glob
-import os
 import sys
+import os
+import glob
+from pathlib import Path
+
 
 # This is the path to the directory you would like to search
 # This directory is searched recursively for .html files
diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py
index e7551cd3..53f389dd 100644
--- a/compiler/datasheet/datasheet.py
+++ b/compiler/datasheet/datasheet.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .table_gen import *
 import os
 import base64
-from globals import OPTS
+from openram import OPTS
+from .table_gen import *
 
 
 class datasheet():
diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py
index f77458b4..fe38b087 100644
--- a/compiler/datasheet/datasheet_gen.py
+++ b/compiler/datasheet/datasheet_gen.py
@@ -15,10 +15,10 @@ a web friendly html datasheet.
 # Improve css
 
 
-from globals import OPTS
 import os
 import math
 import csv
+from openram import OPTS
 from .datasheet import datasheet
 from .table_gen import table_gen
 
diff --git a/compiler/datasheet/table_gen.py b/compiler/datasheet/table_gen.py
index 99e70411..76fafff0 100644
--- a/compiler/datasheet/table_gen.py
+++ b/compiler/datasheet/table_gen.py
@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class table_gen:
     """small library of functions to generate the html tables"""
 
diff --git a/compiler/debug.py b/compiler/debug.py
index 8e970cca..713bb5e2 100644
--- a/compiler/debug.py
+++ b/compiler/debug.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os
-import inspect
-import globals
 import sys
+import os
 import pdb
+import inspect
+from openram import globals
 
 # the debug levels:
 # 0 = minimum output (default)
@@ -96,7 +96,7 @@ log.create_file = True
 
 
 def info(lev, str):
-    from globals import OPTS
+    from openram.globals import OPTS
     # 99 is a special never print level
     if lev == 99:
         return
@@ -114,7 +114,7 @@ def info(lev, str):
 
 
 def archive():
-    from globals import OPTS
+    from openram.globals import OPTS
     try:
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
     except:
diff --git a/compiler/drc/custom_layer_properties.py b/compiler/drc/custom_layer_properties.py
index 8e20d031..0f31d056 100644
--- a/compiler/drc/custom_layer_properties.py
+++ b/compiler/drc/custom_layer_properties.py
@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class _bank:
     def __init__(self, stack, pitch):
         # bank
diff --git a/compiler/drc/design_rules.py b/compiler/drc/design_rules.py
index dfa23c2a..aad2c344 100644
--- a/compiler/drc/design_rules.py
+++ b/compiler/drc/design_rules.py
@@ -5,7 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
 from .drc_value import *
 from .drc_lut import *
 
diff --git a/compiler/drc/drc_lut.py b/compiler/drc/drc_lut.py
index e1b36975..052ede79 100644
--- a/compiler/drc/drc_lut.py
+++ b/compiler/drc/drc_lut.py
@@ -5,7 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
 
 
 class drc_lut():
diff --git a/compiler/drc/drc_value.py b/compiler/drc/drc_value.py
index d4a7cdcc..9d98123b 100644
--- a/compiler/drc/drc_value.py
+++ b/compiler/drc/drc_value.py
@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class drc_value():
     """
     A single DRC value.
diff --git a/compiler/gdsMill/gdsMill/pdfLayout.py b/compiler/gdsMill/gdsMill/pdfLayout.py
index a8996f38..71edf3df 100644
--- a/compiler/gdsMill/gdsMill/pdfLayout.py
+++ b/compiler/gdsMill/gdsMill/pdfLayout.py
@@ -1,8 +1,8 @@
-import pyx
 import math
-from numpy import matrix
-from gdsPrimitives import *
 import random
+from numpy import matrix
+from openram.gdsMill import pyx
+from .gdsPrimitives import *
 
 class pdfLayout:
     """Class representing a view for a layout as a PDF"""
diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py
index 466f4be6..b87aea77 100644
--- a/compiler/gdsMill/gdsMill/vlsiLayout.py
+++ b/compiler/gdsMill/gdsMill/vlsiLayout.py
@@ -1,8 +1,8 @@
-from .gdsPrimitives import *
+import math
 from datetime import *
 import numpy as np
-import math
-import debug
+from openram import debug
+from .gdsPrimitives import *
 
 
 class VlsiLayout:
@@ -774,7 +774,7 @@ class VlsiLayout:
             else:
                 label_text = label.textString
             try:
-                from tech import layer_override
+                from openram.tech import layer_override
                 if layer_override[label_text]:
                     shapes = self.getAllShapes((layer_override[label_text][0], None))
                     if not shapes:
diff --git a/compiler/globals.py b/compiler/globals.py
index 0865d581..30bc705a 100644
--- a/compiler/globals.py
+++ b/compiler/globals.py
@@ -9,17 +9,17 @@
 This is called globals.py, but it actually parses all the arguments
 and performs the global OpenRAM setup as well.
 """
+import sys
 import os
-import debug
+import re
 import shutil
 import optparse
-import options
-import sys
-import re
 import copy
 import importlib
 import getpass
 import subprocess
+from openram import debug
+from openram import options
 
 
 VERSION = "1.2.0"
@@ -202,7 +202,7 @@ def init_openram(config_file, is_unit_test=False):
 
     init_paths()
 
-    from sram_factory import factory
+    from openram.sram_factory import factory
     factory.reset()
 
     global OPTS
@@ -222,8 +222,8 @@ def init_openram(config_file, is_unit_test=False):
     setup_bitcell()
 
     # Import these to find the executables for checkpointing
-    import characterizer
-    import verify
+    from openram import characterizer
+    from openram import verify
     # Make a checkpoint of the options so we can restore
     # after each unit test
     if not CHECKPOINT_OPTS:
@@ -249,7 +249,7 @@ def setup_bitcell():
 
     # See if bitcell exists
     try:
-        c = importlib.import_module("modules." + OPTS.bitcell)
+        c = importlib.import_module("openram.modules." + OPTS.bitcell)
         mod = getattr(c, OPTS.bitcell)
     except ImportError:
         # Use the pbitcell if we couldn't find a custom bitcell
@@ -385,7 +385,7 @@ def end_openram():
     cleanup_paths()
 
     if OPTS.check_lvsdrc:
-        import verify
+        from openram import verify
         verify.print_drc_stats()
         verify.print_lvs_stats()
         verify.print_pex_stats()
@@ -429,24 +429,9 @@ def setup_paths():
 
     global OPTS
 
-    # If $OPENRAM_HOME is defined, use that path for the source code.
-    # Otherwise, use the openram package.
-    try:
-        OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
-    except:
-        import openram
-        OPENRAM_HOME = os.path.dirname(openram.__file__) + "/compiler"
-        # Add this directory to os.environ here
-        os.environ["OPENRAM_HOME"] = OPENRAM_HOME
-
-    debug.check(os.path.isdir(OPENRAM_HOME),
-                "$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME))
+    from openram import OPENRAM_HOME
     debug.info(1, "OpenRAM source code found in {}".format(OPENRAM_HOME))
 
-    if OPENRAM_HOME not in sys.path:
-        sys.path.insert(0, OPENRAM_HOME)
-        debug.info(2, "Adding source code to PYTHONPATH.")
-
     # Use a unique temp subdirectory if multithreaded
     if OPTS.num_threads > 1 or OPTS.openram_temp == "/tmp":
 
@@ -515,7 +500,7 @@ def init_paths():
 def set_default_corner():
     """ Set the default corner. """
 
-    import tech
+    from openram import tech
     # Set some default options now based on the technology...
     if (OPTS.process_corners == ""):
         if OPTS.nominal_corner_only:
@@ -548,8 +533,7 @@ def import_tech():
     """ Dynamically adds the tech directory to the path and imports it. """
     global OPTS
 
-    debug.info(2,
-               "Importing technology: " + OPTS.tech_name)
+    debug.info(2, "Importing technology: " + OPTS.tech_name)
 
     OPENRAM_TECH = ""
 
@@ -591,18 +575,23 @@ def import_tech():
 
     OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/"
 
-    # Prepend the tech directory so it is sourced FIRST
+    # Append tech_path to openram.__path__ to import it from openram
     tech_path = OPTS.openram_tech
-    sys.path.insert(0, tech_path)
+    openram.__path__.append(tech_path)
     try:
-        import tech
+        from openram import tech
     except ImportError:
         debug.error("Could not load tech module.", -1)
 
-    # Prepend custom modules of the technology to the path, if they exist
-    custom_mod_path = os.path.join(tech_path, "modules/")
+    # Remove OPENRAM_TECH from sys.path because we should be done with those
+    for tech_path in OPENRAM_TECH.split(":"):
+        sys.path.remove(tech_path)
+
+    # Add the custom modules to "tech"
+    custom_mod_path = os.path.join(tech_path, "custom/")
     if os.path.exists(custom_mod_path):
-        sys.path.insert(0, custom_mod_path)
+        from openram import tech
+        tech.__path__.append(custom_mod_path)
 
 
 def print_time(name, now_time, last_time=None, indentation=2):
diff --git a/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py b/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py
index cb95031c..5afe983d 100644
--- a/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py
+++ b/compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 10
 num_words = 64
 words_per_row = 4
diff --git a/compiler/model_configs/sram_128b_1024_1rw.py b/compiler/model_configs/sram_128b_1024_1rw.py
index dcefd390..5a50b0b3 100644
--- a/compiler/model_configs/sram_128b_1024_1rw.py
+++ b/compiler/model_configs/sram_128b_1024_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 128
 num_words = 1024
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py b/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py
index a3920fe2..06fa5c5b 100644
--- a/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py
+++ b/compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 12
 num_words = 128
 words_per_row = 4
diff --git a/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py b/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py
index 1d10601b..a5bf474c 100644
--- a/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py
+++ b/compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 12
 num_words = 16
 words_per_row = 1
diff --git a/compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py b/compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py
index 8cb43861..1047fa79 100644
--- a/compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py
+++ b/compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 12
 num_words = 256
 words_per_row = 16
diff --git a/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py b/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py
index 7f09eb55..1ac99b2f 100644
--- a/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py
+++ b/compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 12
 num_words = 256
 words_per_row = 8
diff --git a/compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py b/compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py
index c57fb0f5..92d1f4c4 100644
--- a/compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py
+++ b/compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 14
 num_words = 32
 words_per_row = 2
diff --git a/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py b/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py
index b27f609f..54ed7c33 100644
--- a/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py
+++ b/compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 15
 num_words = 512
 words_per_row = 8
diff --git a/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py b/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py
index 63fd918d..38ab8749 100644
--- a/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py
+++ b/compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 16
 num_words = 1024
 words_per_row = 16
diff --git a/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py b/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py
index 9a1ab061..a02e672d 100644
--- a/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py
+++ b/compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 17
 num_words = 1024
 words_per_row = 16
diff --git a/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py b/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py
index d0479f51..28e45c46 100644
--- a/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py
+++ b/compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 17
 num_words = 256
 words_per_row = 16
diff --git a/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py b/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py
index 65382903..15e3e3bb 100644
--- a/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py
+++ b/compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 18
 num_words = 128
 words_per_row = 2
diff --git a/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py b/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py
index c0d73dfb..18e18445 100644
--- a/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py
+++ b/compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 18
 num_words = 32
 words_per_row = 1
diff --git a/compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py b/compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py
index 5f831189..b26277a9 100644
--- a/compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py
+++ b/compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 21
 num_words = 1024
 words_per_row = 4
diff --git a/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py b/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py
index cbb02b50..62759820 100644
--- a/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py
+++ b/compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 22
 num_words = 512
 words_per_row = 16
diff --git a/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py b/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py
index 1d7227b4..a1075048 100644
--- a/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py
+++ b/compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 23
 num_words = 1024
 words_per_row = 16
diff --git a/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py b/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py
index a8160a1a..ef549e86 100644
--- a/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py
+++ b/compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 26
 num_words = 64
 words_per_row = 4
diff --git a/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py b/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py
index 34c3c56a..96f80422 100644
--- a/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py
+++ b/compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 27
 num_words = 1024
 words_per_row = 4
diff --git a/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py b/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py
index 816f8139..6cb8257c 100644
--- a/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py
+++ b/compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 27
 num_words = 256
 words_per_row = 8
diff --git a/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py b/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py
index eec58a67..fb1533e3 100644
--- a/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py
+++ b/compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 27
 num_words = 512
 words_per_row = 4
diff --git a/compiler/model_configs/sram_32b_2048_1rw.py b/compiler/model_configs/sram_32b_2048_1rw.py
index f7c18aff..2e0b5d41 100644
--- a/compiler/model_configs/sram_32b_2048_1rw.py
+++ b/compiler/model_configs/sram_32b_2048_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 32
 num_words = 2048
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_32b_256_1rw.py b/compiler/model_configs/sram_32b_256_1rw.py
index 998d1db1..4a60dc9a 100644
--- a/compiler/model_configs/sram_32b_256_1rw.py
+++ b/compiler/model_configs/sram_32b_256_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 32
 num_words = 256
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py b/compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py
index 89a61e1d..8b02fcd7 100644
--- a/compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py
+++ b/compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 32
 num_words = 32
 words_per_row = 1
diff --git a/compiler/model_configs/sram_32b_512_1rw.py b/compiler/model_configs/sram_32b_512_1rw.py
index 24bab462..48a5ed26 100644
--- a/compiler/model_configs/sram_32b_512_1rw.py
+++ b/compiler/model_configs/sram_32b_512_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 32
 num_words = 512
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py b/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py
index eabc5206..9877c450 100644
--- a/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py
+++ b/compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 4
 num_words = 16
 words_per_row = 1
diff --git a/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py b/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py
index e7f5bea2..ac8c171e 100644
--- a/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py
+++ b/compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 4
 num_words = 32
 words_per_row = 2
diff --git a/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py b/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py
index f85ad51b..ae317550 100644
--- a/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py
+++ b/compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 4
 num_words = 64
 words_per_row = 4
diff --git a/compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py b/compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py
index 49277e05..d4615fe4 100644
--- a/compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py
+++ b/compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 5
 num_words = 256
 words_per_row = 16
diff --git a/compiler/model_configs/sram_64b_1024_1rw.py b/compiler/model_configs/sram_64b_1024_1rw.py
index 35130d96..c223fa79 100644
--- a/compiler/model_configs/sram_64b_1024_1rw.py
+++ b/compiler/model_configs/sram_64b_1024_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 64
 num_words = 1024
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_64b_512_1rw.py b/compiler/model_configs/sram_64b_512_1rw.py
index 4511604e..06bec60c 100644
--- a/compiler/model_configs/sram_64b_512_1rw.py
+++ b/compiler/model_configs/sram_64b_512_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 64
 num_words = 512
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py b/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py
index 0460c6a9..6ead5650 100644
--- a/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py
+++ b/compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 6
 num_words = 16
 words_per_row = 1
diff --git a/compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py b/compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py
index 3cf12e6e..5841b80b 100644
--- a/compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py
+++ b/compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 7
 num_words = 256
 words_per_row = 4
diff --git a/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py b/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py
index 008e928f..59f3dbc4 100644
--- a/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py
+++ b/compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 7
 num_words = 64
 words_per_row = 2
diff --git a/compiler/model_configs/sram_8b_1024_1rw.py b/compiler/model_configs/sram_8b_1024_1rw.py
index aed46407..5e50cc73 100644
--- a/compiler/model_configs/sram_8b_1024_1rw.py
+++ b/compiler/model_configs/sram_8b_1024_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 8
 num_words = 1024
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_8b_256_1rw.py b/compiler/model_configs/sram_8b_256_1rw.py
index 7c77ce6c..d98a4c10 100644
--- a/compiler/model_configs/sram_8b_256_1rw.py
+++ b/compiler/model_configs/sram_8b_256_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 8
 num_words = 256
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py b/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py
index 3d34aae7..9aa735db 100644
--- a/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py
+++ b/compiler/model_configs/sram_8b_256w_1wpr_1las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 8
 num_words = 256
 words_per_row = 1
diff --git a/compiler/model_configs/sram_8b_512_1rw.py b/compiler/model_configs/sram_8b_512_1rw.py
index f3c5b8fd..f9192207 100644
--- a/compiler/model_configs/sram_8b_512_1rw.py
+++ b/compiler/model_configs/sram_8b_512_1rw.py
@@ -1,8 +1,8 @@
-from shared_config import *
+from .shared_config import *
 word_size = 8
 num_words = 512
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
\ No newline at end of file
+nominal_corner_only = True
diff --git a/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py b/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py
index a0a8f76a..4690cbde 100644
--- a/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py
+++ b/compiler/model_configs/sram_9b_1024w_4wpr_3las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 9
 num_words = 1024
 words_per_row = 4
diff --git a/compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py b/compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py
index 9122ceaa..1277dff8 100644
--- a/compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py
+++ b/compiler/model_configs/sram_9b_128w_1wpr_4las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 9
 num_words = 128
 words_per_row = 1
diff --git a/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py b/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py
index 9a0da00b..7cc73940 100644
--- a/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py
+++ b/compiler/model_configs/sram_9b_256w_4wpr_15las_1rw.py
@@ -1,4 +1,4 @@
-from shared_config import *
+from .shared_config import *
 word_size = 9
 num_words = 256
 words_per_row = 4
diff --git a/compiler/modules/and2_dec.py b/compiler/modules/and2_dec.py
index 8ce10caa..31b68268 100644
--- a/compiler/modules/and2_dec.py
+++ b/compiler/modules/and2_dec.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import design
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import vector
+from openram.base import design
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and2_dec(design):
diff --git a/compiler/modules/and3_dec.py b/compiler/modules/and3_dec.py
index 9c8ee348..44c05983 100644
--- a/compiler/modules/and3_dec.py
+++ b/compiler/modules/and3_dec.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and3_dec(design):
diff --git a/compiler/modules/and4_dec.py b/compiler/modules/and4_dec.py
index 6d75eedd..fc0bd161 100644
--- a/compiler/modules/and4_dec.py
+++ b/compiler/modules/and4_dec.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and4_dec(design):
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index c9279d2a..2f2ef7ff 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
 from math import log, ceil, floor
-from tech import drc
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class bank(design):
diff --git a/compiler/modules/bitcell_1port.py b/compiler/modules/bitcell_1port.py
index a0fdf794..9039dffe 100644
--- a/compiler/modules/bitcell_1port.py
+++ b/compiler/modules/bitcell_1port.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
diff --git a/compiler/modules/bitcell_2port.py b/compiler/modules/bitcell_2port.py
index c346bad6..faddb644 100644
--- a/compiler/modules/bitcell_2port.py
+++ b/compiler/modules/bitcell_2port.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index e50c5b73..f309074b 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.tech import drc, spice
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from globals import OPTS
-from sram_factory import factory
 
 
 class bitcell_array(bitcell_base_array):
diff --git a/compiler/modules/bitcell_base.py b/compiler/modules/bitcell_base.py
index ca41725b..b50006b4 100644
--- a/compiler/modules/bitcell_base.py
+++ b/compiler/modules/bitcell_base.py
@@ -5,12 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-import debug
-from base import design
-from globals import OPTS
-from base import logical_effort
-from tech import parameter, drc, layer, spice
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import parameter, drc, layer, spice
+from openram import OPTS
 
 
 class bitcell_base(design):
@@ -46,7 +45,7 @@ class bitcell_base(design):
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
+        from openram.tech import spice
         leakage = spice["bitcell_leakage"]
         # FIXME
         dynamic = 0
diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py
index 00a80abc..82f0ebad 100644
--- a/compiler/modules/bitcell_base_array.py
+++ b/compiler/modules/bitcell_base_array.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class bitcell_base_array(design):
diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py
index 158cf04b..ea1cf920 100644
--- a/compiler/modules/col_cap_array.py
+++ b/compiler/modules/col_cap_array.py
@@ -3,9 +3,9 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class col_cap_array(bitcell_base_array):
diff --git a/compiler/modules/col_cap_bitcell_1port.py b/compiler/modules/col_cap_bitcell_1port.py
index 35331779..d5687180 100644
--- a/compiler/modules/col_cap_bitcell_1port.py
+++ b/compiler/modules/col_cap_bitcell_1port.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
diff --git a/compiler/modules/col_cap_bitcell_2port.py b/compiler/modules/col_cap_bitcell_2port.py
index 6e5cffa7..f9a1996a 100644
--- a/compiler/modules/col_cap_bitcell_2port.py
+++ b/compiler/modules/col_cap_bitcell_2port.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
diff --git a/compiler/modules/column_decoder.py b/compiler/modules/column_decoder.py
index 2c7199b8..26bc8104 100644
--- a/compiler/modules/column_decoder.py
+++ b/compiler/modules/column_decoder.py
@@ -3,15 +3,15 @@
 # Copyright (c) 2016-2022 Regents of the University of California
 # All rights reserved.
 #
-from tech import drc
-import debug
-from base import design
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import cell_properties
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import cell_properties
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class column_decoder(design):
diff --git a/compiler/modules/column_mux.py b/compiler/modules/column_mux.py
index 67c44894..2a2377a3 100644
--- a/compiler/modules/column_mux.py
+++ b/compiler/modules/column_mux.py
@@ -5,14 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, layer
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pgate import *
-import debug
-from tech import drc, layer
-from base import vector
-from .pgate import *
-from sram_factory import factory
-from tech import cell_properties as cell_props
-from globals import OPTS
 
 
 class column_mux(pgate):
diff --git a/compiler/modules/column_mux_array.py b/compiler/modules/column_mux_array.py
index b8aae4a5..e0a50820 100644
--- a/compiler/modules/column_mux_array.py
+++ b/compiler/modules/column_mux_array.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from tech import layer, preferred_directions
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, preferred_directions
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class column_mux_array(design):
diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index 7d265c9c..7219f0c5 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from sram_factory import factory
 import math
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 from .control_logic_base import control_logic_base
 
 
diff --git a/compiler/modules/control_logic_base.py b/compiler/modules/control_logic_base.py
index decf1f50..4b52c69e 100644
--- a/compiler/modules/control_logic_base.py
+++ b/compiler/modules/control_logic_base.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from sram_factory import factory
 import math
-from base import vector
-from globals import OPTS
-from base import logical_effort
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class control_logic_base(design):
diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py
index c393e280..2b7ab5cb 100644
--- a/compiler/modules/delay_chain.py
+++ b/compiler/modules/delay_chain.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class delay_chain(design):
diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py
index 0f7cb777..494ec2d9 100644
--- a/compiler/modules/dff.py
+++ b/compiler/modules/dff.py
@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import cell_properties as props
-from tech import spice
+from openram.base import design
+from openram.tech import cell_properties as props
+from openram.tech import spice
 
 
 class dff(design):
diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py
index 5a9070c7..44d141c8 100644
--- a/compiler/modules/dff_array.py
+++ b/compiler/modules/dff_array.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_array(design):
diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py
index b0cd619c..80e709e1 100644
--- a/compiler/modules/dff_buf.py
+++ b/compiler/modules/dff_buf.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import layer
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class dff_buf(design):
diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py
index e284b589..305e9d97 100644
--- a/compiler/modules/dff_buf_array.py
+++ b/compiler/modules/dff_buf_array.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_buf_array(design):
diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py
index 4d162c23..425ecdfa 100644
--- a/compiler/modules/dff_inv.py
+++ b/compiler/modules/dff_inv.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_inv(design):
diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py
index 97cbd590..e5e1a3ad 100644
--- a/compiler/modules/dff_inv_array.py
+++ b/compiler/modules/dff_inv_array.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_inv_array(design):
diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py
index 566122e7..20377de5 100644
--- a/compiler/modules/dummy_array.py
+++ b/compiler/modules/dummy_array.py
@@ -3,9 +3,9 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class dummy_array(bitcell_base_array):
diff --git a/compiler/modules/dummy_bitcell_1port.py b/compiler/modules/dummy_bitcell_1port.py
index 3c6f9da6..4f991725 100644
--- a/compiler/modules/dummy_bitcell_1port.py
+++ b/compiler/modules/dummy_bitcell_1port.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
@@ -21,4 +21,3 @@ class dummy_bitcell_1port(bitcell_base):
         super().__init__(name, prop=props.bitcell_1port)
         debug.info(2, "Create dummy bitcell")
 
-
diff --git a/compiler/modules/dummy_bitcell_2port.py b/compiler/modules/dummy_bitcell_2port.py
index 94f99f39..380227ed 100644
--- a/compiler/modules/dummy_bitcell_2port.py
+++ b/compiler/modules/dummy_bitcell_2port.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
@@ -21,4 +21,3 @@ class dummy_bitcell_2port(bitcell_base):
         super().__init__(name, prop=props.bitcell_2port)
         debug.info(2, "Create dummy bitcell 2 port object")
 
-
diff --git a/compiler/modules/dummy_pbitcell.py b/compiler/modules/dummy_pbitcell.py
index 7b099218..661e5365 100644
--- a/compiler/modules/dummy_pbitcell.py
+++ b/compiler/modules/dummy_pbitcell.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dummy_pbitcell(design):
diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py
index b25c37de..c2968bbd 100644
--- a/compiler/modules/global_bitcell_array.py
+++ b/compiler/modules/global_bitcell_array.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .bitcell_base_array import bitcell_base_array
-from globals import OPTS
-from sram_factory import factory
-from base import vector
-import debug
 from numpy import cumsum
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
+from .bitcell_base_array import bitcell_base_array
 
 
 class global_bitcell_array(bitcell_base_array):
diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py
index 3d3c3087..6f09243c 100644
--- a/compiler/modules/hierarchical_decoder.py
+++ b/compiler/modules/hierarchical_decoder.py
@@ -5,16 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import layer_indices
-from tech import layer_stacks
-from tech import layer_properties as layer_props
-from tech import drc
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_indices
+from openram.tech import layer_stacks
+from openram.tech import layer_properties as layer_props
+from openram.tech import drc
+from openram import OPTS
+
 
 class hierarchical_decoder(design):
     """
diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py
index 867b113b..bb58bdbb 100644
--- a/compiler/modules/hierarchical_predecode.py
+++ b/compiler/modules/hierarchical_predecode.py
@@ -5,17 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
 import math
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
-from tech import layer_indices
-from tech import layer_stacks
-from tech import preferred_directions
-from tech import drc
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram.tech import layer_indices
+from openram.tech import layer_stacks
+from openram.tech import preferred_directions
+from openram.tech import drc
+from openram import OPTS
 
 
 class hierarchical_predecode(design):
diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py
index bdd01499..9cfe4463 100644
--- a/compiler/modules/hierarchical_predecode2x4.py
+++ b/compiler/modules/hierarchical_predecode2x4.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode2x4(hierarchical_predecode):
diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py
index dc8e026c..1ffe95ea 100644
--- a/compiler/modules/hierarchical_predecode3x8.py
+++ b/compiler/modules/hierarchical_predecode3x8.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode3x8(hierarchical_predecode):
diff --git a/compiler/modules/hierarchical_predecode4x16.py b/compiler/modules/hierarchical_predecode4x16.py
index 7227bf3b..85391461 100644
--- a/compiler/modules/hierarchical_predecode4x16.py
+++ b/compiler/modules/hierarchical_predecode4x16.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode4x16(hierarchical_predecode):
diff --git a/compiler/modules/internal_base.py b/compiler/modules/internal_base.py
index 70659f0f..3e0ba9f3 100755
--- a/compiler/modules/internal_base.py
+++ b/compiler/modules/internal_base.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram.base import design
 
-from base import design
 
 class internal_base(design):
 
diff --git a/compiler/modules/inv_dec.py b/compiler/modules/inv_dec.py
index 8f143e29..d377938a 100644
--- a/compiler/modules/inv_dec.py
+++ b/compiler/modules/inv_dec.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import logical_effort
-from tech import cell_properties as props
-from tech import spice, parameter
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import spice, parameter
 
 
 class inv_dec(design):
diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py
index 8104e1d2..b2340b4c 100644
--- a/compiler/modules/local_bitcell_array.py
+++ b/compiler/modules/local_bitcell_array.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from globals import OPTS
-from sram_factory import factory
-from base import vector
-import debug
-from tech import layer_properties as layer_props
 
 
 class local_bitcell_array(bitcell_base_array):
diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py
index e5c4bbfc..b2e0c375 100644
--- a/compiler/modules/multibank.py
+++ b/compiler/modules/multibank.py
@@ -6,14 +6,15 @@
 # All rights reserved.
 #
 import sys
-from tech import drc, parameter
-import debug
-from base import design
 import math
-from math import log,sqrt,ceil
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from math import log, sqrt, ceil
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter
+from openram import OPTS
+
 
 class multibank(design):
     """
diff --git a/compiler/modules/nand2_dec.py b/compiler/modules/nand2_dec.py
index c21ac384..68f2a9de 100644
--- a/compiler/modules/nand2_dec.py
+++ b/compiler/modules/nand2_dec.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand2_dec(design):
diff --git a/compiler/modules/nand3_dec.py b/compiler/modules/nand3_dec.py
index 78b6724f..a7d21385 100644
--- a/compiler/modules/nand3_dec.py
+++ b/compiler/modules/nand3_dec.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand3_dec(design):
diff --git a/compiler/modules/nand4_dec.py b/compiler/modules/nand4_dec.py
index f4d507de..7e070b8d 100644
--- a/compiler/modules/nand4_dec.py
+++ b/compiler/modules/nand4_dec.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand4_dec(design):
diff --git a/compiler/modules/orig_bitcell_array.py b/compiler/modules/orig_bitcell_array.py
index 2e3088af..76f01356 100644
--- a/compiler/modules/orig_bitcell_array.py
+++ b/compiler/modules/orig_bitcell_array.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from globals import OPTS
-from sram_factory import factory
 
 
 class bitcell_array(bitcell_base_array):
diff --git a/compiler/modules/pand2.py b/compiler/modules/pand2.py
index 8bd17589..234ace19 100644
--- a/compiler/modules/pand2.py
+++ b/compiler/modules/pand2.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand2(pgate):
diff --git a/compiler/modules/pand3.py b/compiler/modules/pand3.py
index f63b8c41..e61c72e8 100644
--- a/compiler/modules/pand3.py
+++ b/compiler/modules/pand3.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand3(pgate):
diff --git a/compiler/modules/pand4.py b/compiler/modules/pand4.py
index 9b5a31d6..ea852236 100644
--- a/compiler/modules/pand4.py
+++ b/compiler/modules/pand4.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand4(pgate):
diff --git a/compiler/modules/pbitcell.py b/compiler/modules/pbitcell.py
index 516dca3f..9efc3d87 100644
--- a/compiler/modules/pbitcell.py
+++ b/compiler/modules/pbitcell.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import logical_effort
-from base import vector
-from tech import drc, parameter, layer
-from tech import cell_properties as props
-from globals import OPTS
+from openram import debug
+from openram.base import logical_effort
+from openram.base import vector
+from openram.tech import drc, parameter, layer
+from openram.tech import cell_properties as props
+from openram import OPTS
 from .ptx import ptx
 from .bitcell_base import bitcell_base
 
diff --git a/compiler/modules/pbuf.py b/compiler/modules/pbuf.py
index ba44fe2f..7ac419c7 100644
--- a/compiler/modules/pbuf.py
+++ b/compiler/modules/pbuf.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pbuf(pgate):
diff --git a/compiler/modules/pbuf_dec.py b/compiler/modules/pbuf_dec.py
index c04d4922..a910368b 100644
--- a/compiler/modules/pbuf_dec.py
+++ b/compiler/modules/pbuf_dec.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pbuf_dec(pgate):
diff --git a/compiler/modules/pdriver.py b/compiler/modules/pdriver.py
index a9241af5..e0dd1532 100644
--- a/compiler/modules/pdriver.py
+++ b/compiler/modules/pdriver.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from base import vector
-from sram_factory import factory
 
 
 class pdriver(pgate):
diff --git a/compiler/modules/pgate.py b/compiler/modules/pgate.py
index 0ddbc48e..a180e623 100644
--- a/compiler/modules/pgate.py
+++ b/compiler/modules/pgate.py
@@ -5,17 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import vector
-import debug
 import math
 from bisect import bisect_left
-from tech import layer, drc
-from globals import OPTS
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.tech import layer, drc
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 
 if cell_props.ptx.bin_spice_models:
-    from tech import nmos_bins, pmos_bins
+    from openram.tech import nmos_bins, pmos_bins
 
 
 class pgate(design):
diff --git a/compiler/modules/pinv.py b/compiler/modules/pinv.py
index a60bed13..b5b6c89b 100644
--- a/compiler/modules/pinv.py
+++ b/compiler/modules/pinv.py
@@ -5,18 +5,18 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from .pgate import *
-from base import vector
-from base import logical_effort
-from base.utils import round_to_grid
-from base.errors import drc_error
 import operator
-from tech import drc, parameter, spice
 from math import ceil
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.base.utils import round_to_grid
+from openram.base.errors import drc_error
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
+from .pgate import *
 
 
 class pinv(pgate):
diff --git a/compiler/modules/pinv_dec.py b/compiler/modules/pinv_dec.py
index 7b378f08..a9333788 100644
--- a/compiler/modules/pinv_dec.py
+++ b/compiler/modules/pinv_dec.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, layer
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pinv import pinv
-from tech import drc, parameter, layer
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pinv_dec(pinv):
diff --git a/compiler/modules/pinvbuf.py b/compiler/modules/pinvbuf.py
index 78dca7b5..391f98d6 100644
--- a/compiler/modules/pinvbuf.py
+++ b/compiler/modules/pinvbuf.py
@@ -5,11 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
 from .pgate import *
-from base import vector
-from sram_factory import factory
-from tech import layer
+
 
 class pinvbuf(pgate):
     """
diff --git a/compiler/modules/pnand2.py b/compiler/modules/pnand2.py
index 9262b2f8..e573c39c 100644
--- a/compiler/modules/pnand2.py
+++ b/compiler/modules/pnand2.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand2(pgate):
diff --git a/compiler/modules/pnand3.py b/compiler/modules/pnand3.py
index 31a1b400..bf62edd4 100644
--- a/compiler/modules/pnand3.py
+++ b/compiler/modules/pnand3.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand3(pgate):
diff --git a/compiler/modules/pnand4.py b/compiler/modules/pnand4.py
index db0cbf96..65ab135c 100644
--- a/compiler/modules/pnand4.py
+++ b/compiler/modules/pnand4.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand4(pgate):
diff --git a/compiler/modules/pnor2.py b/compiler/modules/pnor2.py
index 35df000f..862bd57c 100644
--- a/compiler/modules/pnor2.py
+++ b/compiler/modules/pnor2.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnor2(pgate):
diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py
index 576dff01..d1489f06 100644
--- a/compiler/modules/port_address.py
+++ b/compiler/modules/port_address.py
@@ -4,13 +4,13 @@
 # All rights reserved.
 #
 from math import log, ceil
-import debug
-from base import design
-from sram_factory import factory
-from base import vector
-from tech import layer, drc
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, drc
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class port_address(design):
diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py
index f34aa893..e96a20a6 100644
--- a/compiler/modules/port_data.py
+++ b/compiler/modules/port_data.py
@@ -3,16 +3,16 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
-from tech import drc
-import debug
-from base import design
 import math
-from sram_factory import factory
 from collections import namedtuple
-from base import vector
-from globals import OPTS
-from tech import cell_properties
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import cell_properties
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class port_data(design):
diff --git a/compiler/modules/precharge.py b/compiler/modules/precharge.py
index 4a1267e5..ed2550b5 100644
--- a/compiler/modules/precharge.py
+++ b/compiler/modules/precharge.py
@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import parameter, drc
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pgate import *
-from tech import parameter, drc
-from base import vector
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class precharge(design):
diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py
index 3c7ab681..f91c51fd 100644
--- a/compiler/modules/precharge_array.py
+++ b/compiler/modules/precharge_array.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class precharge_array(design):
diff --git a/compiler/modules/ptristate_inv.py b/compiler/modules/ptristate_inv.py
index 583b68ea..0e7ab721 100644
--- a/compiler/modules/ptristate_inv.py
+++ b/compiler/modules/ptristate_inv.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from sram_factory import factory
 
 
 class ptristate_inv(pgate):
diff --git a/compiler/modules/ptx.py b/compiler/modules/ptx.py
index d1bd13c8..4457a573 100644
--- a/compiler/modules/ptx.py
+++ b/compiler/modules/ptx.py
@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import logical_effort
-from base import vector
-from tech import layer, drc, spice
-from sram_factory import factory
-from globals import OPTS
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, drc, spice
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 
 
 class ptx(design):
diff --git a/compiler/modules/pwrite_driver.py b/compiler/modules/pwrite_driver.py
index 9af6c78f..e0b1b5ca 100644
--- a/compiler/modules/pwrite_driver.py
+++ b/compiler/modules/pwrite_driver.py
@@ -5,12 +5,12 @@
 #(acting for and on behalf of Oklahoma State University)
 #All rights reserved.
 #
-from base import design
-from tech import parameter
-import debug
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import parameter
+from openram import OPTS
 
 
 class pwrite_driver(design):
diff --git a/compiler/modules/replica_bitcell_1port.py b/compiler/modules/replica_bitcell_1port.py
index f4c9432e..4d28fd83 100644
--- a/compiler/modules/replica_bitcell_1port.py
+++ b/compiler/modules/replica_bitcell_1port.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import parameter, drc
 from .bitcell_base import bitcell_base
-from tech import cell_properties as props
-from tech import parameter, drc
-from base import logical_effort
 
 
 class replica_bitcell_1port(bitcell_base):
@@ -39,7 +39,7 @@ class replica_bitcell_1port(bitcell_base):
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
+        from openram.tech import spice
         leakage = spice["bitcell_leakage"]
         dynamic = 0 # FIXME
         total_power = self.return_power(dynamic, leakage)
diff --git a/compiler/modules/replica_bitcell_2port.py b/compiler/modules/replica_bitcell_2port.py
index eb46f6d0..e70c20ae 100644
--- a/compiler/modules/replica_bitcell_2port.py
+++ b/compiler/modules/replica_bitcell_2port.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import parameter, drc
 from .bitcell_base import bitcell_base
-from tech import cell_properties as props
-from tech import parameter, drc
-from base import logical_effort
 
 
 class replica_bitcell_2port(bitcell_base):
diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index f3725489..17814f48 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -3,15 +3,14 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
-
-import debug
-from base import vector
-from base import contact
+from openram import debug
+from openram.base import vector
+from openram.base import contact
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram.tech import cell_properties as props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from tech import cell_properties as props
-from globals import OPTS
-from sram_factory import factory
 
 
 class replica_bitcell_array(bitcell_base_array):
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index 5f59c016..af9d5bb6 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -3,12 +3,12 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import layer_properties as layer_props
 
 
 class replica_column(bitcell_base_array):
diff --git a/compiler/modules/replica_pbitcell.py b/compiler/modules/replica_pbitcell.py
index 54fda10a..f36b6dab 100644
--- a/compiler/modules/replica_pbitcell.py
+++ b/compiler/modules/replica_pbitcell.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class replica_pbitcell(design):
diff --git a/compiler/modules/row_cap_array.py b/compiler/modules/row_cap_array.py
index 61b736b3..d8332f30 100644
--- a/compiler/modules/row_cap_array.py
+++ b/compiler/modules/row_cap_array.py
@@ -3,9 +3,9 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class row_cap_array(bitcell_base_array):
diff --git a/compiler/modules/row_cap_bitcell_1port.py b/compiler/modules/row_cap_bitcell_1port.py
index d9defc1b..355eb2b3 100644
--- a/compiler/modules/row_cap_bitcell_1port.py
+++ b/compiler/modules/row_cap_bitcell_1port.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
diff --git a/compiler/modules/row_cap_bitcell_2port.py b/compiler/modules/row_cap_bitcell_2port.py
index 2f6bf766..55ba5387 100644
--- a/compiler/modules/row_cap_bitcell_2port.py
+++ b/compiler/modules/row_cap_bitcell_2port.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py
index e90a02ca..34735382 100644
--- a/compiler/modules/sense_amp.py
+++ b/compiler/modules/sense_amp.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from tech import parameter, drc, spice
-from tech import cell_properties as props
-from base import logical_effort
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import parameter, drc, spice
+from openram.tech import cell_properties as props
 
 
 class sense_amp(design):
@@ -43,7 +43,7 @@ class sense_amp(design):
         # FIXME: This input load will be applied to both the s_en timing and bitline timing.
 
         # Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
-        from tech import spice
+        from openram.tech import spice
         # Default is 8x. Per Samira and Hodges-Jackson book:
         # "Column-mux transistors driven by the decoder must be sized for optimal speed"
         bitline_pmos_size = 8 # FIXME: This should be set somewhere and referenced. Probably in tech file.
diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py
index 3e98a517..c3f51013 100644
--- a/compiler/modules/sense_amp_array.py
+++ b/compiler/modules/sense_amp_array.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import vector
-from sram_factory import factory
-from tech import cell_properties
-import debug
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import cell_properties
+from openram import OPTS
 
 
 class sense_amp_array(design):
diff --git a/compiler/modules/sram.py b/compiler/modules/sram.py
index 6c26e5ec..bf3c14ba 100644
--- a/compiler/modules/sram.py
+++ b/compiler/modules/sram.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import datetime
 import os
-import debug
-from characterizer import functional
-from globals import OPTS, print_time
 import shutil
+import datetime
+from openram import debug
+from openram.characterizer import functional
+from openram import OPTS, print_time
 
 
 class sram():
@@ -26,7 +26,7 @@ class sram():
 
         # reset the static duplicate name checker for unit tests
         # in case we create more than one SRAM
-        from base import design
+        from openram.base import design
         design.name_map=[]
 
         debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
@@ -80,7 +80,7 @@ class sram():
 
         # Import this at the last minute so that the proper tech file
         # is loaded and the right tools are selected
-        import verify
+        from openram import verify
 
         # Save the spice file
         start_time = datetime.datetime.now()
@@ -144,7 +144,7 @@ class sram():
 
         # Characterize the design
         start_time = datetime.datetime.now()
-        from characterizer import lib
+        from openram.characterizer import lib
         debug.print_raw("LIB: Characterizing... ")
         lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
         print_time("Characterization", datetime.datetime.now(), start_time)
@@ -158,7 +158,7 @@ class sram():
 
         # Write the datasheet
         start_time = datetime.datetime.now()
-        from datasheet import datasheet_gen
+        from openram.datasheet import datasheet_gen
         dname = OPTS.output_path + self.s.name + ".html"
         debug.print_raw("Datasheet: Writing to {0}".format(dname))
         datasheet_gen.datasheet_write(dname)
diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py
index 63303c40..fbc347af 100644
--- a/compiler/modules/sram_1bank.py
+++ b/compiler/modules/sram_1bank.py
@@ -5,19 +5,19 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import vector
-from base import channel_route
-from router import router_tech
-from globals import OPTS, print_time
 import datetime
-import debug
 from math import ceil
-from importlib import reload
-from base import design
-from base import verilog
-from base import lef
-from sram_factory import factory
-from tech import spice
+from importlib import import_module, reload
+from openram import debug
+from openram.base import vector
+from openram.base import channel_route
+from openram.base import design
+from openram.base import verilog
+from openram.base import lef
+from openram.router import router_tech
+from openram.sram_factory import factory
+from openram.tech import spice
+from openram import OPTS, print_time
 
 
 class sram_1bank(design, verilog, lef):
@@ -43,7 +43,7 @@ class sram_1bank(design, verilog, lef):
             self.num_spare_cols = 0
 
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             self.supply_stack = power_grid
         except ImportError:
             # if no power_grid is specified by tech we use sensible defaults
@@ -254,9 +254,9 @@ class sram_1bank(design, verilog, lef):
             # Do not route the power supply (leave as must-connect pins)
             return
         elif OPTS.route_supplies == "grid":
-            from router import supply_grid_router as router
+            from openram.router import supply_grid_router as router
         else:
-            from router import supply_tree_router as router
+            from openram.router import supply_tree_router as router
         rtr=router(layers=self.supply_stack,
                    design=self,
                    bbox=bbox,
@@ -367,7 +367,7 @@ class sram_1bank(design, verilog, lef):
                     for bit in range(self.num_spare_cols):
                         pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
 
-        from router import signal_escape_router as router
+        from openram.router import signal_escape_router as router
         rtr=router(layers=self.m3_stack,
                    design=self,
                    bbox=bbox)
@@ -482,7 +482,7 @@ class sram_1bank(design, verilog, lef):
 
         self.bank_count = 0
 
-        c = reload(__import__('modules.' + OPTS.control_logic))
+        c = reload(import_module("." + OPTS.control_logic, "openram.modules"))
         self.mod_control_logic = getattr(c, OPTS.control_logic)
 
         # Create the control logic module for each port type
diff --git a/compiler/modules/sram_config.py b/compiler/modules/sram_config.py
index a46c80a2..17606438 100644
--- a/compiler/modules/sram_config.py
+++ b/compiler/modules/sram_config.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
 from math import log, sqrt, ceil
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_config:
@@ -28,12 +28,12 @@ class sram_config:
         self.num_spare_cols = num_spare_cols
 
         try:
-            from tech import array_row_multiple
+            from openram.tech import array_row_multiple
             self.array_row_multiple = array_row_multiple
         except ImportError:
             self.array_row_multiple = 1
         try:
-            from tech import array_col_multiple
+            from openram.tech import array_col_multiple
             self.array_col_multiple = array_col_multiple
         except ImportError:
             self.array_col_multiple = 1
diff --git a/compiler/modules/sram_multibank.py b/compiler/modules/sram_multibank.py
index 675e0c02..08a4ddaa 100644
--- a/compiler/modules/sram_multibank.py
+++ b/compiler/modules/sram_multibank.py
@@ -1,8 +1,8 @@
-from .template import template
-from globals import OPTS
 import os
-from math import ceil, log
 import re
+from math import ceil, log
+from openram import OPTS
+from .template import template
 
 
 class sram_multibank:
diff --git a/compiler/modules/tri_gate.py b/compiler/modules/tri_gate.py
index c5d65d57..3fcae977 100644
--- a/compiler/modules/tri_gate.py
+++ b/compiler/modules/tri_gate.py
@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import spice
+from openram import debug
+from openram.base import design
+from openram.tech import spice
 
 
 class tri_gate(design):
diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py
index 984d8039..b44d9831 100644
--- a/compiler/modules/tri_gate_array.py
+++ b/compiler/modules/tri_gate_array.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import drc
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram import OPTS
 
 class tri_gate_array(design):
     """
diff --git a/compiler/modules/wordline_buffer_array.py b/compiler/modules/wordline_buffer_array.py
index d624d5db..4d09892d 100644
--- a/compiler/modules/wordline_buffer_array.py
+++ b/compiler/modules/wordline_buffer_array.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import layer
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_buffer_array(design):
diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py
index e8fd8901..f588ee12 100644
--- a/compiler/modules/wordline_driver.py
+++ b/compiler/modules/wordline_driver.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import design
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import vector
+from openram.base import design
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_driver(design):
diff --git a/compiler/modules/wordline_driver_array.py b/compiler/modules/wordline_driver_array.py
index f88d6b86..4387fb02 100644
--- a/compiler/modules/wordline_driver_array.py
+++ b/compiler/modules/wordline_driver_array.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import drc, layer
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_driver_array(design):
diff --git a/compiler/modules/write_driver.py b/compiler/modules/write_driver.py
index 00afa0ee..eef7aa04 100644
--- a/compiler/modules/write_driver.py
+++ b/compiler/modules/write_driver.py
@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import cell_properties as props
+from openram import debug
+from openram.base import design
+from openram.tech import cell_properties as props
 
 
 class write_driver(design):
diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py
index 5c3b664f..ba0d968b 100644
--- a/compiler/modules/write_driver_array.py
+++ b/compiler/modules/write_driver_array.py
@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
 import math
-from tech import drc
-from sram_factory import factory
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram import OPTS
 
 
 class write_driver_array(design):
diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py
index f3e7e9bc..a8a8ef32 100644
--- a/compiler/modules/write_mask_and_array.py
+++ b/compiler/modules/write_mask_and_array.py
@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_mask_and_array(design):
diff --git a/compiler/options.py b/compiler/options.py
index 729718e8..c9c4d303 100644
--- a/compiler/options.py
+++ b/compiler/options.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import optparse
 import os
+import optparse
 
 
 class options(optparse.Values):
diff --git a/compiler/router/direction.py b/compiler/router/direction.py
index a7eeb727..66db4dbf 100644
--- a/compiler/router/direction.py
+++ b/compiler/router/direction.py
@@ -6,8 +6,8 @@
 # All rights reserved.
 #
 from enum import Enum
-from base.vector3d import vector3d
-import debug
+from openram import debug
+from openram.base.vector3d import vector3d
 
 
 class direction(Enum):
diff --git a/compiler/router/grid.py b/compiler/router/grid.py
index 1ace0e05..44aaf96c 100644
--- a/compiler/router/grid.py
+++ b/compiler/router/grid.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base.vector3d import vector3d
+from openram import debug
+from openram.base.vector3d import vector3d
 from .grid_cell import grid_cell
 
 
diff --git a/compiler/router/grid_cell.py b/compiler/router/grid_cell.py
index 7c3ee51f..ae12243a 100644
--- a/compiler/router/grid_cell.py
+++ b/compiler/router/grid_cell.py
@@ -5,6 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+
 class grid_cell:
     """
     A single cell that can be occupied in a given layer, blocked,
diff --git a/compiler/router/grid_path.py b/compiler/router/grid_path.py
index 1c7c576a..68241b56 100644
--- a/compiler/router/grid_path.py
+++ b/compiler/router/grid_path.py
@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 from itertools import tee
-from base.vector3d import vector3d
+from openram.base.vector3d import vector3d
 from .grid import grid
 from .direction import direction
 
diff --git a/compiler/router/grid_utils.py b/compiler/router/grid_utils.py
index 0bf954a3..50f7220b 100644
--- a/compiler/router/grid_utils.py
+++ b/compiler/router/grid_utils.py
@@ -10,8 +10,8 @@ Some utility functions for sets of grid cells.
 """
 
 import math
+from openram.base.vector3d import vector3d
 from .direction import direction
-from base.vector3d import vector3d
 
 
 def increment_set(curset, direct):
diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py
index 7d7f25d8..2afea6b7 100644
--- a/compiler/router/pin_group.py
+++ b/compiler/router/pin_group.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base.vector import vector
-from base.vector3d import vector3d
-from base.pin_layout import pin_layout
+from openram import debug
+from openram.base.vector import vector
+from openram.base.vector3d import vector3d
+from openram.base.pin_layout import pin_layout
 from .direction import direction
 
 
diff --git a/compiler/router/router.py b/compiler/router/router.py
index 2e18b37a..ceef0ad6 100644
--- a/compiler/router/router.py
+++ b/compiler/router/router.py
@@ -5,18 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-import itertools
 import math
+import itertools
 from datetime import datetime
-from gdsMill import gdsMill
-import debug
-from globals import OPTS, print_time
-from tech import drc, GDS
-from tech import layer as techlayer
-from base.vector import vector
-from base.vector3d import vector3d
-from base.pin_layout import pin_layout
+from openram import debug
+from openram.base.vector import vector
+from openram.base.vector3d import vector3d
+from openram.base.pin_layout import pin_layout
+from openram.gdsMill import gdsMill
+from openram.tech import drc, GDS
+from openram.tech import layer as techlayer
+from openram import OPTS, print_time
 from .router_tech import router_tech
 from .pin_group import pin_group
 from . import grid_utils
diff --git a/compiler/router/router_tech.py b/compiler/router/router_tech.py
index 22f1fd15..5daa9bef 100644
--- a/compiler/router/router_tech.py
+++ b/compiler/router/router_tech.py
@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from tech import drc, layer, preferred_directions
-from base.contact import contact
-from base.vector import vector
-import debug
 import math
+from openram import debug
+from openram.base.contact import contact
+from openram.base.vector import vector
+from openram.tech import drc, layer, preferred_directions
 
 
 class router_tech:
diff --git a/compiler/router/signal_escape_router.py b/compiler/router/signal_escape_router.py
index a1d1e10a..7c804fb2 100644
--- a/compiler/router/signal_escape_router.py
+++ b/compiler/router/signal_escape_router.py
@@ -6,8 +6,8 @@
 # All rights reserved.
 #
 from datetime import datetime
-import debug
-from globals import print_time
+from openram import debug
+from openram import print_time
 from .router import router
 from .signal_grid import signal_grid
 
diff --git a/compiler/router/signal_grid.py b/compiler/router/signal_grid.py
index f6ea31f5..9a425a1f 100644
--- a/compiler/router/signal_grid.py
+++ b/compiler/router/signal_grid.py
@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from heapq import heappush,heappop
 from copy import deepcopy
-from base.vector3d import vector3d
+from heapq import heappush,heappop
+from openram import debug
+from openram.base.vector3d import vector3d
 from .grid import grid
 from .grid_path import grid_path
 
diff --git a/compiler/router/signal_router.py b/compiler/router/signal_router.py
index 11e40a91..5015e409 100644
--- a/compiler/router/signal_router.py
+++ b/compiler/router/signal_router.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from router import router
+from openram import debug
+from openram.router import router
 
 
 class signal_router(router):
diff --git a/compiler/router/supply_grid_router.py b/compiler/router/supply_grid_router.py
index 24cd168f..05587091 100644
--- a/compiler/router/supply_grid_router.py
+++ b/compiler/router/supply_grid_router.py
@@ -6,9 +6,9 @@
 # All rights reserved.
 #
 from datetime import datetime
-import debug
-from globals import print_time
-from base.vector3d import vector3d
+from openram import debug
+from openram.base.vector3d import vector3d
+from openram import print_time
 from .router import router
 from .direction import direction
 from .supply_grid import supply_grid
diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py
index a34f7dd0..99b1a5fe 100644
--- a/compiler/router/supply_tree_router.py
+++ b/compiler/router/supply_tree_router.py
@@ -8,8 +8,8 @@
 from datetime import datetime
 from scipy.sparse import csr_matrix
 from scipy.sparse.csgraph import minimum_spanning_tree
-import debug
-from globals import print_time
+from openram import debug
+from openram import print_time
 from .router import router
 from . import grid_utils
 from .signal_grid import signal_grid
diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py
index 0ebb6865..47514de2 100644
--- a/compiler/sram_factory.py
+++ b/compiler/sram_factory.py
@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from globals import OPTS
 import importlib
+from openram import OPTS
 
 
 class sram_factory:
@@ -39,7 +39,7 @@ class sram_factory:
         """
         overridden = False
         try:
-            from tech import tech_modules
+            from openram.tech import tech_modules
             real_module_type = tech_modules[module_type]
             # If we are given a list of modules, it is indexed by number of ports starting from 1
             if type(real_module_type) is list:
@@ -105,12 +105,12 @@ class sram_factory:
             try:
                 # Dynamically load the module
                 if real_module_type == "contact":
-                    c  = importlib.import_module("base.contact")
+                    c  = importlib.import_module("openram.base.contact")
                 else:
-                    c  = importlib.import_module("modules."+real_module_type)
+                    c  = importlib.import_module("openram.modules."+real_module_type)
             except ModuleNotFoundError:
                 # Check if it is a technology specific module
-                c  = importlib.import_module("custom."+real_module_type)
+                c  = importlib.import_module("openram.custom."+real_module_type)
 
             mod = getattr(c, real_module_type)
 
diff --git a/compiler/tests/00_code_format_check_test.py b/compiler/tests/00_code_format_check_test.py
index 8eff7388..0d323799 100755
--- a/compiler/tests/00_code_format_check_test.py
+++ b/compiler/tests/00_code_format_check_test.py
@@ -6,13 +6,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
+import sys, os, re
 import unittest
 from testutils import *
-import sys, os,re
 
-import globals
-import debug
+import openram
+from openram import debug
+
 
 class code_format_test(openram_test):
     "Run a test to check for tabs instead of spaces in the all source files."
@@ -147,7 +147,7 @@ def check_print_output(file_name):
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/01_library_test.py b/compiler/tests/01_library_test.py
index 9a6b5702..2822b6b2 100755
--- a/compiler/tests/01_library_test.py
+++ b/compiler/tests/01_library_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os, re
 import unittest
 from testutils import *
-import sys, os,re
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
+
 
 class library_lvs_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import verify
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import verify
 
         (gds_dir, sp_dir, allnames) = setup_files()
         drc_errors = 0
@@ -41,7 +42,7 @@ class library_lvs_test(openram_test):
 
         # fail if the error count is not zero
         self.assertEqual(drc_errors + lvs_errors, 0)
-        globals.end_openram()
+        openram.end_openram()
 
 
 def setup_files():
@@ -66,7 +67,7 @@ def setup_files():
         tempnames[i] = re.sub('\.sp$', '', tempnames[i])
 
     try:
-        from tech import blackbox_cells
+        from openram.tech import blackbox_cells
         nameset = list(set(tempnames) - set(blackbox_cells))
     except ImportError:
         # remove duplicate base names
@@ -78,7 +79,7 @@ def setup_files():
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py
index 251d517e..95ce662e 100755
--- a/compiler/tests/03_contact_test.py
+++ b/compiler/tests/03_contact_test.py
@@ -6,22 +6,23 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class contact_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
-        from tech import active_stack, poly_stack, beol_stacks
+        from openram.tech import active_stack, poly_stack, beol_stacks
 
         # Don't do active because of nwell contact rules
         # Don't do metal3 because of min area rules
@@ -86,13 +87,12 @@ class contact_test(openram_test):
                            well_type="p")
         self.local_drc_check(c)
 
-        globals.end_openram()
-
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py
index e2f46b90..9903dbe0 100755
--- a/compiler/tests/03_path_test.py
+++ b/compiler/tests/03_path_test.py
@@ -6,22 +6,23 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
+
 
 class path_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from base import wire_path
-        import tech
-        from base import design
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.base import wire_path
+        from openram import tech
+        from openram.base import design
 
         min_space = 2 * tech.drc["minwidth_m1"]
         layer_stack = ("m1")
@@ -86,13 +87,12 @@ class path_test(openram_test):
         wire_path(w, layer_stack, position_list)
         self.local_drc_check(w)
 
-        globals.end_openram()
-
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py
index d7281c87..a05ba575 100755
--- a/compiler/tests/03_ptx_1finger_nmos_test.py
+++ b/compiler/tests/03_ptx_1finger_nmos_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class ptx_1finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import tech
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import tech
 
         debug.info(2, "Checking min size NMOS with 1 finger")
         fet = factory.create(module_type="ptx",
@@ -30,12 +30,12 @@ class ptx_1finger_nmos_test(openram_test):
                              tx_type="nmos")
         self.local_drc_check(fet)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py
index 85c4088a..045bc13c 100755
--- a/compiler/tests/03_ptx_1finger_pmos_test.py
+++ b/compiler/tests/03_ptx_1finger_pmos_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class ptx_1finger_pmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import tech
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import tech
 
         debug.info(2, "Checking min size PMOS with 1 finger")
         fet = factory.create(module_type="ptx",
@@ -29,12 +30,12 @@ class ptx_1finger_pmos_test(openram_test):
                              tx_type="pmos")
         self.local_drc_check(fet)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py
index 5bc43a14..17371825 100755
--- a/compiler/tests/03_ptx_3finger_nmos_test.py
+++ b/compiler/tests/03_ptx_3finger_nmos_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class ptx_3finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import tech
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import tech
 
         debug.info(2, "Checking three fingers NMOS")
         fet = factory.create(module_type="ptx",
@@ -32,12 +33,12 @@ class ptx_3finger_nmos_test(openram_test):
                              connect_poly=True)
         self.local_drc_check(fet)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py
index 699a5190..72df0e50 100755
--- a/compiler/tests/03_ptx_3finger_pmos_test.py
+++ b/compiler/tests/03_ptx_3finger_pmos_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class ptx_3finger_pmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import tech
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import tech
 
         debug.info(2, "Checking three fingers PMOS")
         fet = factory.create(module_type="ptx",
@@ -32,12 +33,12 @@ class ptx_3finger_pmos_test(openram_test):
                              connect_poly=True)
         self.local_drc_check(fet)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py
index 41c05f84..b3677fd2 100755
--- a/compiler/tests/03_ptx_4finger_nmos_test.py
+++ b/compiler/tests/03_ptx_4finger_nmos_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class ptx_4finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import tech
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import tech
 
         debug.info(2, "Checking three fingers NMOS")
         fet = factory.create(module_type="ptx",
@@ -32,12 +33,12 @@ class ptx_4finger_nmos_test(openram_test):
                              connect_poly=True)
         self.local_drc_check(fet)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py
index ae2c88e2..b8ff106b 100755
--- a/compiler/tests/03_ptx_4finger_pmos_test.py
+++ b/compiler/tests/03_ptx_4finger_pmos_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class ptx_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import tech
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import tech
 
         debug.info(2, "Checking three fingers PMOS")
         fet = factory.create(module_type="ptx",
@@ -32,12 +33,12 @@ class ptx_test(openram_test):
                              connect_poly=True)
         self.local_drc_check(fet)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_ptx_no_contacts_test.py b/compiler/tests/03_ptx_no_contacts_test.py
index ad6e346c..cafe6219 100755
--- a/compiler/tests/03_ptx_no_contacts_test.py
+++ b/compiler/tests/03_ptx_no_contacts_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class ptx_no_contacts_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import tech
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram import tech
 
         debug.info(2, "Checking single finger no source/drain")
         fet = factory.create(module_type="ptx",
@@ -49,12 +49,12 @@ class ptx_no_contacts_test(openram_test):
                              tx_type="nmos")
         self.local_drc_check(fet)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py
index 5f4b0661..6bd70f6b 100755
--- a/compiler/tests/03_wire_test.py
+++ b/compiler/tests/03_wire_test.py
@@ -6,22 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys
-import os
 
-import globals
+import openram
 
 
 class wire_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from base import wire
-        import tech
-        from base import design
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.base import wire
+        from openram import tech
+        from openram.base import design
 
         layer_stacks = [tech.poly_stack] + tech.beol_stacks
 
@@ -50,12 +49,12 @@ class wire_test(openram_test):
                 wire(w, layer_stack, position_list)
                 self.local_drc_check(w)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_and2_dec_test.py b/compiler/tests/04_and2_dec_test.py
index bae4c274..68c09940 100755
--- a/compiler/tests/04_and2_dec_test.py
+++ b/compiler/tests/04_and2_dec_test.py
@@ -6,28 +6,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class and2_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        global verify
-        import verify
+        openram.init_openram(config_file, is_unit_test=True)
+        #global verify
+        from openram import verify
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing and2_dec 1rw/1r gate")
         a = factory.create(module_type="and2_dec")
@@ -36,17 +36,18 @@ class and2_dec_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing and2_dec 1rw gate")
         a = factory.create(module_type="and2_dec")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_and3_dec_test.py b/compiler/tests/04_and3_dec_test.py
index 24d5364b..a2d5229f 100755
--- a/compiler/tests/04_and3_dec_test.py
+++ b/compiler/tests/04_and3_dec_test.py
@@ -6,28 +6,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class and3_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        global verify
-        import verify
+        openram.init_openram(config_file, is_unit_test=True)
+        #global verify
+        from openram import verify
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing and3_dec 1rw/1r gate")
         a = factory.create(module_type="and3_dec")
@@ -36,17 +36,18 @@ class and3_dec_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing and3_dec 1rw gate")
         a = factory.create(module_type="and3_dec")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py
index c860eeca..27141098 100755
--- a/compiler/tests/04_and4_dec_test.py
+++ b/compiler/tests/04_and4_dec_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 # @unittest.skip("SKIPPING 04_and4_dec_test")
@@ -21,14 +21,14 @@ class and4_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        global verify
-        import verify
+        openram.init_openram(config_file, is_unit_test=True)
+        #global verify
+        from openram import verify
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing and4_dec 1rw/1r gate")
         a = factory.create(module_type="and4_dec")
@@ -37,17 +37,18 @@ class and4_dec_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing and4_dec 1rw gate")
         a = factory.create(module_type="and4_dec")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_column_mux_1rw_1r_test.py b/compiler/tests/04_column_mux_1rw_1r_test.py
index 61b42f6c..37145332 100755
--- a/compiler/tests/04_column_mux_1rw_1r_test.py
+++ b/compiler/tests/04_column_mux_1rw_1r_test.py
@@ -6,26 +6,26 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Checking column mux port 0")
         tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
@@ -35,11 +35,12 @@ class column_mux_1rw_1r_test(openram_test):
         tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl1", bitcell_br="br1")
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_column_mux_pbitcell_test.py b/compiler/tests/04_column_mux_pbitcell_test.py
index 24ec4129..bb1ccaa6 100755
--- a/compiler/tests/04_column_mux_pbitcell_test.py
+++ b/compiler/tests/04_column_mux_pbitcell_test.py
@@ -6,21 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux in multi-port
         OPTS.bitcell = "pbitcell"
@@ -38,11 +38,12 @@ class column_mux_pbitcell_test(openram_test):
         tx = factory.create(module_type="column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_column_mux_test.py b/compiler/tests/04_column_mux_test.py
index 814c4733..cd36edb9 100755
--- a/compiler/tests/04_column_mux_test.py
+++ b/compiler/tests/04_column_mux_test.py
@@ -6,32 +6,33 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux in single port
         debug.info(2, "Checking column mux")
         tx = factory.create(module_type="column_mux", tx_size=8)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_dff_buf_test.py b/compiler/tests/04_dff_buf_test.py
index 7eb6f37a..0d2ee9f7 100755
--- a/compiler/tests/04_dff_buf_test.py
+++ b/compiler/tests/04_dff_buf_test.py
@@ -6,30 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_buf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         debug.info(2, "Testing dff_buf 4x 8x")
         a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py
index ef214268..f0a09313 100755
--- a/compiler/tests/04_dummy_pbitcell_test.py
+++ b/compiler/tests/04_dummy_pbitcell_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class replica_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import dummy_pbitcell
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import dummy_pbitcell
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
@@ -41,11 +42,12 @@ class replica_pbitcell_test(openram_test):
         tx = dummy_pbitcell(name="rpbc")
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py
index 0740c5f6..152ae8db 100755
--- a/compiler/tests/04_pand2_test.py
+++ b/compiler/tests/04_pand2_test.py
@@ -6,34 +6,35 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
 
 
 class pand2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        global verify
-        import verify
+        openram.init_openram(config_file, is_unit_test=True)
+        #global verify
+        from openram import verify
 
-        from modules import pand2
+        from openram.modules import pand2
 
         debug.info(2, "Testing pand2 gate 4x")
         a = pand2(name="pand2x4", size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py
index d75ff484..67704b56 100755
--- a/compiler/tests/04_pand3_test.py
+++ b/compiler/tests/04_pand3_test.py
@@ -6,34 +6,35 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
 
 
 class pand3_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        global verify
-        import verify
+        openram.init_openram(config_file, is_unit_test=True)
+        #global verify
+        from openram import verify
 
-        from modules import pand3
+        from openram.modules import pand3
 
         debug.info(2, "Testing pand3 gate 4x")
         a = pand3(name="pand3x4", size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pand4_test.py b/compiler/tests/04_pand4_test.py
index 941a8626..c768d922 100755
--- a/compiler/tests/04_pand4_test.py
+++ b/compiler/tests/04_pand4_test.py
@@ -6,34 +6,35 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
 
 
 class pand4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        global verify
-        import verify
+        openram.init_openram(config_file, is_unit_test=True)
+        #global verify
+        from openram import verify
 
-        from modules import pand4
+        from openram.modules import pand4
 
         debug.info(2, "Testing pand4 gate 4x")
         a = pand4(name="pand4x4", size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py
index 227b6755..d02ace05 100755
--- a/compiler/tests/04_pbitcell_test.py
+++ b/compiler/tests/04_pbitcell_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
-from sram_factory import factory
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 #@unittest.skip("SKIPPING 04_pbitcell_test")
 class pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports=1
         OPTS.num_w_ports=1
@@ -102,13 +103,12 @@ class pbitcell_test(openram_test):
         tx = factory.create(module_type="pbitcell")
         self.local_check(tx)
 
-        globals.end_openram()
-
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pbuf_dec_8x_test.py b/compiler/tests/04_pbuf_dec_8x_test.py
index 6de1f48c..84be067c 100755
--- a/compiler/tests/04_pbuf_dec_8x_test.py
+++ b/compiler/tests/04_pbuf_dec_8x_test.py
@@ -6,35 +6,37 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pbuf_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Checking 8x size decoder buffer")
         a = factory.create(module_type="pbuf_dec", size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py
index 83ffcde4..f44ddd09 100755
--- a/compiler/tests/04_pbuf_test.py
+++ b/compiler/tests/04_pbuf_test.py
@@ -6,30 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pbuf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing buffer 8x")
         a = factory.create(module_type="pbuf", size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py
index c2def4ac..ba7d37dc 100755
--- a/compiler/tests/04_pdriver_test.py
+++ b/compiler/tests/04_pdriver_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pdriver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         # a tests the error message for specifying conflicting conditions
@@ -41,11 +42,12 @@ class pdriver_test(openram_test):
         f = factory.create(module_type="pdriver", fanout = 64, inverting = True)
         self.local_check(f)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copdsay of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pinv_100x_test.py b/compiler/tests/04_pinv_100x_test.py
index 62fc48b9..708ba105 100755
--- a/compiler/tests/04_pinv_100x_test.py
+++ b/compiler/tests/04_pinv_100x_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 100x inverter")
         tx = factory.create(module_type="pinv", size=100)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py
index 81be4e27..93136164 100755
--- a/compiler/tests/04_pinv_10x_test.py
+++ b/compiler/tests/04_pinv_10x_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 8x inverter")
         tx = factory.create(module_type="pinv", size=8)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py
index 6554ee99..1dd893d9 100755
--- a/compiler/tests/04_pinv_1x_beta_test.py
+++ b/compiler/tests/04_pinv_1x_beta_test.py
@@ -6,30 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 1x beta=3 size inverter")
         tx = factory.create(module_type="pinv", size=1, beta=3)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py
index 26fbbcb8..9d976f2e 100755
--- a/compiler/tests/04_pinv_1x_test.py
+++ b/compiler/tests/04_pinv_1x_test.py
@@ -6,30 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 1x size inverter")
         tx = factory.create(module_type="pinv", size=1)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py
index e341396f..61ec6b37 100755
--- a/compiler/tests/04_pinv_2x_test.py
+++ b/compiler/tests/04_pinv_2x_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2x size inverter")
         tx = factory.create(module_type="pinv", size=2)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pinv_dec_1x_test.py b/compiler/tests/04_pinv_dec_1x_test.py
index b5c4d264..13f01b2c 100755
--- a/compiler/tests/04_pinv_dec_1x_test.py
+++ b/compiler/tests/04_pinv_dec_1x_test.py
@@ -6,36 +6,37 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class pinv_dec_1x_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Checking 1x size decoder inverter")
         tx = factory.create(module_type="pinv_dec", size=1)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py
index a3fc10ae..67705d8b 100755
--- a/compiler/tests/04_pinvbuf_test.py
+++ b/compiler/tests/04_pinvbuf_test.py
@@ -6,30 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pinvbuf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         a = factory.create(module_type="pinvbuf", size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py
index facd2625..7bf5fe90 100755
--- a/compiler/tests/04_pnand2_test.py
+++ b/compiler/tests/04_pnand2_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pnand2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2-input nand gate")
         tx = factory.create(module_type="pnand2", size=1)
@@ -30,12 +31,12 @@ class pnand2_test(openram_test):
         # # Only DRC because well contacts will fail LVS
         # self.local_drc_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py
index e51a837f..07076bed 100755
--- a/compiler/tests/04_pnand3_test.py
+++ b/compiler/tests/04_pnand3_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pnand3_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 3-input nand gate")
         tx = factory.create(module_type="pnand3", size=1)
@@ -30,12 +31,12 @@ class pnand3_test(openram_test):
         # # Only DRC because well contacts will fail LVS
         # self.local_drc_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pnand4_test.py b/compiler/tests/04_pnand4_test.py
index 88449fce..ac49bb64 100755
--- a/compiler/tests/04_pnand4_test.py
+++ b/compiler/tests/04_pnand4_test.py
@@ -6,32 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class pnand4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 4-input nand gate")
         tx = factory.create(module_type="pnand4", size=1)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py
index 566b16b8..26e090fe 100755
--- a/compiler/tests/04_pnor2_test.py
+++ b/compiler/tests/04_pnor2_test.py
@@ -6,30 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class pnor2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2-input nor gate")
         tx = factory.create(module_type="pnor2", size=1)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_precharge_1rw_1r_test.py b/compiler/tests/04_precharge_1rw_1r_test.py
index 3739a9a0..c5a56b39 100755
--- a/compiler/tests/04_precharge_1rw_1r_test.py
+++ b/compiler/tests/04_precharge_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check precharge array in multi-port
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Checking precharge for 1rw1r port 0")
         tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
@@ -37,11 +37,12 @@ class precharge_test(openram_test):
         tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_precharge_pbitcell_test.py b/compiler/tests/04_precharge_pbitcell_test.py
index 32f625ce..2599cdf1 100755
--- a/compiler/tests/04_precharge_pbitcell_test.py
+++ b/compiler/tests/04_precharge_pbitcell_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class precharge_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check precharge in multi-port
         OPTS.bitcell = "pbitcell"
@@ -42,11 +43,12 @@ class precharge_pbitcell_test(openram_test):
         tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2")
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py
index 5cf57f9a..ca38bf1b 100755
--- a/compiler/tests/04_precharge_test.py
+++ b/compiler/tests/04_precharge_test.py
@@ -6,32 +6,33 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check precharge in single port
         debug.info(2, "Checking precharge for handmade bitcell")
         tx = factory.create(module_type="precharge", size=1)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_pwrite_driver_test.py b/compiler/tests/04_pwrite_driver_test.py
index 08adc62f..46d6ae3c 100755
--- a/compiler/tests/04_pwrite_driver_test.py
+++ b/compiler/tests/04_pwrite_driver_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import header, openram_test
-import sys
-import os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 @unittest.skip("SKIPPING 04_pwrite_driver_test")
 class pwrite_driver_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_{0}".format(OPTS.tech_name), is_unit_test=True)
+        openram.init_openram("config_{0}".format(OPTS.tech_name), is_unit_test=True)
 
         debug.info(2, "Checking 1x pwrite_driver")
         tx = factory.create(module_type="pwrite_driver", size=1)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main()
diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py
index 7249e094..c43352a4 100755
--- a/compiler/tests/04_replica_pbitcell_test.py
+++ b/compiler/tests/04_replica_pbitcell_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class replica_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import replica_pbitcell
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import replica_pbitcell
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
@@ -41,11 +42,12 @@ class replica_pbitcell_test(openram_test):
         tx = replica_pbitcell(name="rpbc")
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_wordline_driver_test.py b/compiler/tests/04_wordline_driver_test.py
index 168ac6bc..0d78ab1c 100755
--- a/compiler/tests/04_wordline_driver_test.py
+++ b/compiler/tests/04_wordline_driver_test.py
@@ -6,33 +6,34 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 #@unittest.skip("SKIPPING 04_driver_test")
-
 class wordline_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
         tx = factory.create(module_type="wordline_driver", cols=8)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/05_bitcell_array_1rw_1r_test.py b/compiler/tests/05_bitcell_array_1rw_1r_test.py
index da9bb597..4e030c87 100755
--- a/compiler/tests/05_bitcell_array_1rw_1r_test.py
+++ b/compiler/tests/05_bitcell_array_1rw_1r_test.py
@@ -6,36 +6,37 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 2x2 array for cell_2port")
         a = factory.create(module_type="bitcell_array", cols=2, rows=2)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py
index cfa80767..4cde4dfd 100755
--- a/compiler/tests/05_bitcell_array_test.py
+++ b/compiler/tests/05_bitcell_array_test.py
@@ -6,21 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 8x8 array for 6t_cell")
 
@@ -34,11 +34,12 @@ class array_test(openram_test):
         a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py
index c4730416..aeee578d 100755
--- a/compiler/tests/05_dummy_array_test.py
+++ b/compiler/tests/05_dummy_array_test.py
@@ -4,20 +4,21 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class dummy_row_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing dummy row for 6t_cell")
         a = factory.create(module_type="dummy_array", rows=1, cols=4)
@@ -27,11 +28,12 @@ class dummy_row_test(openram_test):
         a = factory.create(module_type="dummy_array", rows=4, cols=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py
index cb90e58f..788a59a3 100755
--- a/compiler/tests/05_pbitcell_array_test.py
+++ b/compiler/tests/05_pbitcell_array_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 #@unittest.skip("SKIPPING 05_pbitcell_array_test")
 class pbitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
         OPTS.bitcell = "pbitcell"
@@ -46,11 +47,12 @@ class pbitcell_array_test(openram_test):
         a = factory.create(module_type="bitcell_array", cols=4, rows=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_column_decoder_16row_test.py b/compiler/tests/06_column_decoder_16row_test.py
index 9c6b5508..7fa69848 100755
--- a/compiler/tests/06_column_decoder_16row_test.py
+++ b/compiler/tests/06_column_decoder_16row_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2-input NAND decoder
         debug.info(1, "Testing 16 row sample for column_decoder")
         a = factory.create(module_type="column_decoder", col_addr_size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py
index c145a6a4..4c7d11fc 100755
--- a/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two
         debug.info(1, "Testing 132 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=132)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_132row_test.py b/compiler/tests/06_hierarchical_decoder_132row_test.py
index 77be88dc..88bd8b76 100755
--- a/compiler/tests/06_hierarchical_decoder_132row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_132row_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two
         debug.info(1, "Testing 132 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=132)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py
index 159c5ea5..90568ae2 100755
--- a/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2-input NAND decoder
         debug.info(1, "Testing 16 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_16row_test.py b/compiler/tests/06_hierarchical_decoder_16row_test.py
index 74b39b95..82c24ca0 100755
--- a/compiler/tests/06_hierarchical_decoder_16row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_16row_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2-input NAND decoder
         debug.info(1, "Testing 16 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py
index b100a05e..785633c0 100755
--- a/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2-input NAND decoder with non-power-of-two
         debug.info(1, "Testing 17 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_17row_test.py b/compiler/tests/06_hierarchical_decoder_17row_test.py
index 487f3eb7..60fe315d 100755
--- a/compiler/tests/06_hierarchical_decoder_17row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_17row_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2-input NAND decoder with non-power-of-two
         debug.info(1, "Testing 17 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py
index eabf7693..cdee9eb2 100755
--- a/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 with 3x8 and 2-input NAND decoder
         debug.info(1, "Testing 32 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_32row_test.py b/compiler/tests/06_hierarchical_decoder_32row_test.py
index c567f510..6807e2d0 100755
--- a/compiler/tests/06_hierarchical_decoder_32row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_32row_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 with 3x8 and 2-input NAND decoder
         debug.info(1, "Testing 32 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py
index 0db29543..35c7ce78 100755
--- a/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2-input NAND decoder
         debug.info(1, "Testing 4096 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=4096)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_4096row_test.py b/compiler/tests/06_hierarchical_decoder_4096row_test.py
index f8d497cc..b79e236a 100755
--- a/compiler/tests/06_hierarchical_decoder_4096row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_4096row_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 2x4 and 2-input NAND decoder
         debug.info(1, "Testing 4096 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=4096)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py
index 82592dce..ba1c78be 100755
--- a/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 3 x 3x8 and 3-input NAND decoder
         debug.info(1, "Testing 512 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_512row_test.py b/compiler/tests/06_hierarchical_decoder_512row_test.py
index 48ad81ae..205f9b42 100755
--- a/compiler/tests/06_hierarchical_decoder_512row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_512row_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 3 x 3x8 and 3-input NAND decoder
         debug.info(1, "Testing 512 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py
index 52bea3d7..6d809e4d 100755
--- a/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 3 x 2x4 and 3-input NAND decoder
         debug.info(1, "Testing 64 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=64)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_64row_test.py b/compiler/tests/06_hierarchical_decoder_64row_test.py
index aadec410..40bae453 100755
--- a/compiler/tests/06_hierarchical_decoder_64row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_64row_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # Checks 3 x 2x4 and 3-input NAND decoder
         debug.info(1, "Testing 64 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=64)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py
index 5dcd6b16..602bdc6d 100755
--- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py
+++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py
@@ -6,26 +6,26 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_decoder_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         # check hierarchical decoder for multi-port
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         factory.reset()
         debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
@@ -64,11 +64,12 @@ class hierarchical_decoder_pbitcell_test(openram_test):
         a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py
index 4940bebe..ff1886cd 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py
@@ -6,36 +6,37 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_predecode2x4_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for hierarchy_predecode2x4")
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
index 8f7ef312..a9d156f3 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_predecode2x4_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # checking hierarchical precode 2x4 for multi-port
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py
index 31d14067..201d7034 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_predecode2x4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for hierarchy_predecode2x4")
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py
index 8d51d862..b818c05c 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_predecode3x8_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
index f01f6ad1..8cb4e082 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_predecode3x8_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # checking hierarchical precode 3x8 for multi-port
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py
index 14a498cd..15d7d84e 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_predecode3x8_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode4x16_test.py b/compiler/tests/06_hierarchical_predecode4x16_test.py
index 6a4ef9e6..4091128a 100755
--- a/compiler/tests/06_hierarchical_predecode4x16_test.py
+++ b/compiler/tests/06_hierarchical_predecode4x16_test.py
@@ -6,37 +6,38 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class hierarchical_predecode4x16_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for hierarchy_predecode4x16")
         a = factory.create(module_type="hierarchical_predecode4x16")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py
index cb5503c7..9274c93a 100755
--- a/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py
+++ b/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py
@@ -6,25 +6,25 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for 16-way column_mux_array port 0")
         a = factory.create(module_type="column_mux_array", columns=32, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
@@ -34,12 +34,12 @@ class column_mux_test(openram_test):
         a = factory.create(module_type="column_mux_array", columns=32, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_16mux_test.py b/compiler/tests/07_column_mux_array_16mux_test.py
index b26bc971..785e2201 100755
--- a/compiler/tests/07_column_mux_array_16mux_test.py
+++ b/compiler/tests/07_column_mux_array_16mux_test.py
@@ -6,31 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 16-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=64, word_size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py
index c284158b..50032c11 100755
--- a/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py
+++ b/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py
@@ -6,25 +6,25 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for 2-way column_mux_array port 0")
         a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
@@ -34,12 +34,12 @@ class column_mux_test(openram_test):
         a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_2mux_test.py b/compiler/tests/07_column_mux_array_2mux_test.py
index 8377bff8..39e99164 100755
--- a/compiler/tests/07_column_mux_array_2mux_test.py
+++ b/compiler/tests/07_column_mux_array_2mux_test.py
@@ -6,31 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 2-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=16, word_size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py
index 4487e3ea..c02f3a1a 100755
--- a/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py
+++ b/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py
@@ -6,25 +6,25 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for 4-way column_mux_array port 0")
         a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
@@ -34,12 +34,12 @@ class column_mux_test(openram_test):
         a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_4mux_test.py b/compiler/tests/07_column_mux_array_4mux_test.py
index e5b5b140..10c8dbb3 100755
--- a/compiler/tests/07_column_mux_array_4mux_test.py
+++ b/compiler/tests/07_column_mux_array_4mux_test.py
@@ -6,31 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 4-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=16, word_size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py
index 55a0df95..c6be4f9d 100755
--- a/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py
+++ b/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py
@@ -6,25 +6,25 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Testing sample for 8-way column_mux_array port 0")
         a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
@@ -34,12 +34,12 @@ class column_mux_test(openram_test):
         a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_8mux_test.py b/compiler/tests/07_column_mux_array_8mux_test.py
index 18669aac..c7c08024 100755
--- a/compiler/tests/07_column_mux_array_8mux_test.py
+++ b/compiler/tests/07_column_mux_array_8mux_test.py
@@ -6,31 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 8-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=32, word_size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/07_column_mux_array_pbitcell_test.py b/compiler/tests/07_column_mux_array_pbitcell_test.py
index d406261d..296bbe69 100755
--- a/compiler/tests/07_column_mux_array_pbitcell_test.py
+++ b/compiler/tests/07_column_mux_array_pbitcell_test.py
@@ -6,20 +6,20 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from testutils import *
 import sys, os
+from testutils import *
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import OPTS
+from openram.sram_factory import factory
+from openram import debug
 
 
 class column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux array in multi-port
         OPTS.bitcell = "pbitcell"
@@ -44,12 +44,12 @@ class column_mux_pbitcell_test(openram_test):
         a = factory.create(module_type="column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2", column_offset=3)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py
index 1c185466..90f819c0 100755
--- a/compiler/tests/08_precharge_array_1rw_1r_test.py
+++ b/compiler/tests/08_precharge_array_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openrem import OPTS
 
 
 class precharge_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check precharge array in multi-port
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         factory.reset()
         debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)")
@@ -37,11 +37,12 @@ class precharge_1rw_1r_test(openram_test):
         pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0", column_offset=1)
         self.local_check(pc)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py
index b63b731e..de372857 100755
--- a/compiler/tests/08_precharge_array_test.py
+++ b/compiler/tests/08_precharge_array_test.py
@@ -6,30 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 3 column precharge")
         pc = factory.create(module_type="precharge_array", columns=3)
         self.local_check(pc)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/08_wordline_buffer_array_test.py b/compiler/tests/08_wordline_buffer_array_test.py
index 90b20d9b..056148f3 100755
--- a/compiler/tests/08_wordline_buffer_array_test.py
+++ b/compiler/tests/08_wordline_buffer_array_test.py
@@ -6,32 +6,33 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class wordline_buffer_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
         tx = factory.create(module_type="wordline_buffer_array", rows=8, cols=32)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py
index d1b837ca..741fabb5 100755
--- a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py
+++ b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py
@@ -6,38 +6,39 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class wordline_driver_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
         tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/08_wordline_driver_array_pbitcell_test.py b/compiler/tests/08_wordline_driver_array_pbitcell_test.py
index a49321e1..55ce65f1 100755
--- a/compiler/tests/08_wordline_driver_array_pbitcell_test.py
+++ b/compiler/tests/08_wordline_driver_array_pbitcell_test.py
@@ -6,21 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class wordline_driver_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for multi-port
         OPTS.bitcell = "pbitcell"
@@ -33,11 +33,12 @@ class wordline_driver_array_pbitcell_test(openram_test):
         tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/08_wordline_driver_array_test.py b/compiler/tests/08_wordline_driver_array_test.py
index 62d41506..b59e5af1 100755
--- a/compiler/tests/08_wordline_driver_array_test.py
+++ b/compiler/tests/08_wordline_driver_array_test.py
@@ -6,32 +6,33 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class wordline_driver_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
         tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32)
         self.local_check(tx)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/09_sense_amp_array_1rw_1r_test.py b/compiler/tests/09_sense_amp_array_1rw_1r_test.py
index 9af9ff54..cd1635f5 100755
--- a/compiler/tests/09_sense_amp_array_1rw_1r_test.py
+++ b/compiler/tests/09_sense_amp_array_1rw_1r_test.py
@@ -6,26 +6,26 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sense_amp_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
@@ -39,11 +39,12 @@ class sense_amp_test(openram_test):
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/09_sense_amp_array_pbitcell_test.py b/compiler/tests/09_sense_amp_array_pbitcell_test.py
index 5d5f89b5..19c7e417 100755
--- a/compiler/tests/09_sense_amp_array_pbitcell_test.py
+++ b/compiler/tests/09_sense_amp_array_pbitcell_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys,os
 import unittest
 from testutils import *
-import sys,os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class sense_amp_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         #check sense amp array for multi-port
         OPTS.bitcell = "pbitcell"
@@ -36,11 +37,12 @@ class sense_amp_pbitcell_test(openram_test):
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py
index 06db38ba..8e6a557c 100755
--- a/compiler/tests/09_sense_amp_array_spare_cols_test.py
+++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class sense_amp_array_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check sense amp array for single port
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 and num_spare_cols=3")
@@ -45,11 +46,12 @@ class sense_amp_array_spare_cols_test(openram_test):
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=3)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py
index 7af1481f..675a1fc3 100755
--- a/compiler/tests/09_sense_amp_array_test.py
+++ b/compiler/tests/09_sense_amp_array_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class sense_amp_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
@@ -33,11 +34,12 @@ class sense_amp_test(openram_test):
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_driver_array_1rw_1r_test.py b/compiler/tests/10_write_driver_array_1rw_1r_test.py
index 6a3ae1c1..72df2598 100755
--- a/compiler/tests/10_write_driver_array_1rw_1r_test.py
+++ b/compiler/tests/10_write_driver_array_1rw_1r_test.py
@@ -6,26 +6,26 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
         a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
@@ -35,11 +35,12 @@ class write_driver_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py
index 2a757a2b..aa28f2d5 100755
--- a/compiler/tests/10_write_driver_array_pbitcell_test.py
+++ b/compiler/tests/10_write_driver_array_pbitcell_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"
@@ -36,11 +37,12 @@ class write_driver_pbitcell_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py
index c8c7a923..4162f776 100755
--- a/compiler/tests/10_write_driver_array_spare_cols_test.py
+++ b/compiler/tests/10_write_driver_array_spare_cols_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class write_driver_array_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8 and num_spare_cols=3")
@@ -45,11 +46,12 @@ class write_driver_array_spare_cols_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py
index 8195990c..092b3696 100755
--- a/compiler/tests/10_write_driver_array_test.py
+++ b/compiler/tests/10_write_driver_array_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
@@ -30,11 +31,12 @@ class write_driver_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py
index cd4ed505..eb30fed8 100755
--- a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py
+++ b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py
@@ -6,22 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"
@@ -38,12 +37,12 @@ class write_driver_pbitcell_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py
index e7964983..83ffcc81 100755
--- a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py
+++ b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py
@@ -6,22 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_driver_array_wmask_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")
@@ -36,12 +35,12 @@ class write_driver_array_wmask_spare_cols_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4, num_spare_cols=3)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py
index f2767690..7b74bec2 100755
--- a/compiler/tests/10_write_driver_array_wmask_test.py
+++ b/compiler/tests/10_write_driver_array_wmask_test.py
@@ -6,22 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")
@@ -36,12 +35,12 @@ class write_driver_test(openram_test):
         a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py
index d90cc0a2..205293f5 100755
--- a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py
+++ b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py
@@ -6,26 +6,26 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_mask_and_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4")
         a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
@@ -39,12 +39,12 @@ class write_mask_and_array_test(openram_test):
         a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_mask_and_array_pbitcell_test.py b/compiler/tests/10_write_mask_and_array_pbitcell_test.py
index e3d8fd84..5a89558e 100755
--- a/compiler/tests/10_write_mask_and_array_pbitcell_test.py
+++ b/compiler/tests/10_write_mask_and_array_pbitcell_test.py
@@ -6,22 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_mask_and_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"
@@ -38,12 +37,12 @@ class write_mask_and_array_pbitcell_test(openram_test):
         a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py
index 1b9dcd28..d3a50877 100755
--- a/compiler/tests/10_write_mask_and_array_test.py
+++ b/compiler/tests/10_write_mask_and_array_test.py
@@ -6,22 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_mask_and_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4")
@@ -36,12 +35,12 @@ class write_mask_and_array_test(openram_test):
         a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py
index 32383548..a430f59a 100755
--- a/compiler/tests/11_dff_array_test.py
+++ b/compiler/tests/11_dff_array_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class dff_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing dff_array for 3x3")
         a = factory.create(module_type="dff_array", rows=3, columns=3)
@@ -33,11 +34,12 @@ class dff_array_test(openram_test):
         a = factory.create(module_type="dff_array", rows=3, columns=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py
index ca357666..c7adf900 100755
--- a/compiler/tests/11_dff_buf_array_test.py
+++ b/compiler/tests/11_dff_buf_array_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class dff_buf_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing dff_buf_array for 3x3")
         a = factory.create(module_type="dff_buf_array", rows=3, columns=3)
@@ -33,11 +34,12 @@ class dff_buf_array_test(openram_test):
         a = factory.create(module_type="dff_buf_array", rows=3, columns=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py
index 673dc884..2b269efd 100755
--- a/compiler/tests/12_tri_gate_array_test.py
+++ b/compiler/tests/12_tri_gate_array_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 12_tri_gate_array_test")
@@ -21,7 +21,7 @@ class tri_gate_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
         a = factory.create(module_type="tri_gate_array", columns=8, word_size=8)
@@ -31,11 +31,12 @@ class tri_gate_array_test(openram_test):
         a = factory.create(module_type="tri_gate_array", columns=16, word_size=8)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py
index 563565a8..a89a8115 100755
--- a/compiler/tests/13_delay_chain_test.py
+++ b/compiler/tests/13_delay_chain_test.py
@@ -6,30 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class delay_chain_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing delay_chain")
         a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4])
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
index 0f85caca..e8f9b03e 100755
--- a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
@@ -4,26 +4,26 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 4x4 array left and right replica for dp cell")
         a = factory.create(module_type="replica_bitcell_array",
@@ -34,11 +34,12 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
                            right_rbl=[1])
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
index 2cb9f7c0..727e5187 100755
--- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
@@ -4,26 +4,26 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 4x4 left replica array for dp cell")
         a = factory.create(module_type="replica_bitcell_array",
@@ -33,11 +33,11 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
                            left_rbl=[0])
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
index abe0b40d..31fe041e 100755
--- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
@@ -4,26 +4,26 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 4x4 non-replica array for dp cell")
         a = factory.create(module_type="replica_bitcell_array",
@@ -32,11 +32,12 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
                            rbl=[1, 1])
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py
index 8b754cf2..ce5d00c8 100755
--- a/compiler/tests/14_replica_bitcell_array_test.py
+++ b/compiler/tests/14_replica_bitcell_array_test.py
@@ -4,20 +4,21 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class replica_bitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
@@ -28,11 +29,12 @@ class replica_bitcell_array_test(openram_test):
         a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_column_1rw_1r_test.py b/compiler/tests/14_replica_column_1rw_1r_test.py
index eab07b2a..178d26da 100755
--- a/compiler/tests/14_replica_column_1rw_1r_test.py
+++ b/compiler/tests/14_replica_column_1rw_1r_test.py
@@ -4,26 +4,26 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class replica_column_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing one left replica column for dual port")
         a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1)
@@ -41,11 +41,12 @@ class replica_column_test(openram_test):
         a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py
index 77f49dab..fbf05c18 100755
--- a/compiler/tests/14_replica_column_test.py
+++ b/compiler/tests/14_replica_column_test.py
@@ -4,21 +4,21 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class replica_column_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -34,11 +34,12 @@ class replica_column_test(openram_test):
                            column_offset=num_spare_cols)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py
index 328b2d90..5d2e25ff 100755
--- a/compiler/tests/14_replica_pbitcell_array_test.py
+++ b/compiler/tests/14_replica_pbitcell_array_test.py
@@ -4,20 +4,21 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class replica_pbitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell = "replica_pbitcell"
@@ -42,11 +43,12 @@ class replica_pbitcell_array_test(openram_test):
         a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py
index 5e9589ff..764af0b1 100755
--- a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py
+++ b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py
@@ -6,13 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 # @unittest.skip("SKIPPING 05_global_bitcell_array_test")
@@ -20,12 +21,12 @@ class global_bitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 2 x 4x4 global bitcell array for cell_1rw_1r")
         a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
@@ -35,12 +36,12 @@ class global_bitcell_array_test(openram_test):
         # a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0])
         # self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/15_global_bitcell_array_test.py b/compiler/tests/15_global_bitcell_array_test.py
index e49806c0..ed9ae15a 100755
--- a/compiler/tests/15_global_bitcell_array_test.py
+++ b/compiler/tests/15_global_bitcell_array_test.py
@@ -6,13 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from sram_factory import factory
-import debug
+import openram
+from openram.sram_factory import factory
+from openram import debug
+from openram import OPTS
 
 
 # @unittest.skip("SKIPPING 05_global_bitcell_array_test")
@@ -20,7 +21,7 @@ class global_bitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
         # a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
@@ -30,12 +31,12 @@ class global_bitcell_array_test(openram_test):
         a = factory.create(module_type="global_bitcell_array", cols=[10, 6], rows=4)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py
index ce4636b8..fc6283e8 100755
--- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py
+++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py
@@ -6,13 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 # @unittest.skip("SKIPPING 05_local_bitcell_array_test")
@@ -20,12 +21,12 @@ class local_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica")
         a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1])
@@ -43,12 +44,12 @@ class local_bitcell_array_1rw_1r_test(openram_test):
         a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/15_local_bitcell_array_test.py b/compiler/tests/15_local_bitcell_array_test.py
index 699f3e9f..a724d8f3 100755
--- a/compiler/tests/15_local_bitcell_array_test.py
+++ b/compiler/tests/15_local_bitcell_array_test.py
@@ -6,13 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 # @unittest.skip("SKIPPING 05_local_bitcell_array_test")
@@ -20,7 +21,7 @@ class local_bitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica")
         a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0])
@@ -30,12 +31,12 @@ class local_bitcell_array_test(openram_test):
         a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py
index 71c88dee..5657bd01 100755
--- a/compiler/tests/16_control_logic_multiport_test.py
+++ b/compiler/tests/16_control_logic_multiport_test.py
@@ -10,20 +10,21 @@
 Run a regression test on a control_logic
 """
 
+import sys, os
 import unittest
 from testutils import header,openram_test
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # check control logic for multi-port
         OPTS.bitcell = "pbitcell"
@@ -48,11 +49,12 @@ class control_logic_test(openram_test):
         a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main()
diff --git a/compiler/tests/16_control_logic_r_test.py b/compiler/tests/16_control_logic_r_test.py
index 478acaa9..1a0fe0fe 100755
--- a/compiler/tests/16_control_logic_r_test.py
+++ b/compiler/tests/16_control_logic_r_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_r")
         a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="r")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/16_control_logic_rw_test.py b/compiler/tests/16_control_logic_rw_test.py
index 3c0304d6..5e5d09a0 100755
--- a/compiler/tests/16_control_logic_rw_test.py
+++ b/compiler/tests/16_control_logic_rw_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_rw")
         a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/16_control_logic_w_test.py b/compiler/tests/16_control_logic_w_test.py
index ef426398..0dfe8929 100755
--- a/compiler/tests/16_control_logic_w_test.py
+++ b/compiler/tests/16_control_logic_w_test.py
@@ -6,30 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_w")
         a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="w")
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_address_16rows_1rw_1r_test.py b/compiler/tests/18_port_address_16rows_1rw_1r_test.py
index eacf8da7..edfc2c05 100755
--- a/compiler/tests/18_port_address_16rows_1rw_1r_test.py
+++ b/compiler/tests/18_port_address_16rows_1rw_1r_test.py
@@ -4,37 +4,38 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_address_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Port address 16 rows")
         a = factory.create("port_address", cols=16, rows=16, port=0)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_address_16rows_test.py b/compiler/tests/18_port_address_16rows_test.py
index 20edcbd9..6688dda8 100755
--- a/compiler/tests/18_port_address_16rows_test.py
+++ b/compiler/tests/18_port_address_16rows_test.py
@@ -4,31 +4,32 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_address_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Port address 16 rows")
         a = factory.create("port_address", cols=16, rows=16, port=0)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_address_256rows_1rw_1r_test.py b/compiler/tests/18_port_address_256rows_1rw_1r_test.py
index 53307e21..9dc5882c 100755
--- a/compiler/tests/18_port_address_256rows_1rw_1r_test.py
+++ b/compiler/tests/18_port_address_256rows_1rw_1r_test.py
@@ -4,37 +4,38 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_address_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         debug.info(1, "Port address 256 rows")
         a = factory.create("port_address", cols=256, rows=256, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_address_512rows_test.py b/compiler/tests/18_port_address_512rows_test.py
index 5e610074..e03c6e65 100755
--- a/compiler/tests/18_port_address_512rows_test.py
+++ b/compiler/tests/18_port_address_512rows_test.py
@@ -4,31 +4,32 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_address_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Port address 512 rows")
         a = factory.create("port_address", cols=256, rows=512, port=0)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_16mux_1rw_1r_test.py b/compiler/tests/18_port_data_16mux_1rw_1r_test.py
index 9b5401da..779cb3d9 100755
--- a/compiler/tests/18_port_data_16mux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_16mux_1rw_1r_test.py
@@ -4,27 +4,27 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -40,11 +40,12 @@ class port_data_1rw_1r_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_16mux_test.py b/compiler/tests/18_port_data_16mux_test.py
index 2a374b8e..53496191 100755
--- a/compiler/tests/18_port_data_16mux_test.py
+++ b/compiler/tests/18_port_data_16mux_test.py
@@ -8,18 +8,18 @@ import unittest
 from testutils import *
 import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -42,11 +42,12 @@ class port_data_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_2mux_1rw_1r_test.py b/compiler/tests/18_port_data_2mux_1rw_1r_test.py
index b47d1fbb..895c87a4 100755
--- a/compiler/tests/18_port_data_2mux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_2mux_1rw_1r_test.py
@@ -4,27 +4,27 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -39,11 +39,12 @@ class port_data_1rw_1r_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_2mux_test.py b/compiler/tests/18_port_data_2mux_test.py
index 4498500f..cb822fe6 100755
--- a/compiler/tests/18_port_data_2mux_test.py
+++ b/compiler/tests/18_port_data_2mux_test.py
@@ -4,22 +4,22 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -41,11 +41,12 @@ class port_data_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_4mux_1rw_1r_test.py b/compiler/tests/18_port_data_4mux_1rw_1r_test.py
index b78751f4..a65f65d2 100755
--- a/compiler/tests/18_port_data_4mux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_4mux_1rw_1r_test.py
@@ -4,27 +4,27 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -39,11 +39,12 @@ class port_data_1rw_1r_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_4mux_test.py b/compiler/tests/18_port_data_4mux_test.py
index f3e4ae67..aa4c081d 100755
--- a/compiler/tests/18_port_data_4mux_test.py
+++ b/compiler/tests/18_port_data_4mux_test.py
@@ -4,22 +4,22 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -41,11 +41,12 @@ class port_data_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_8mux_1rw_1r_test.py b/compiler/tests/18_port_data_8mux_1rw_1r_test.py
index 165a83f7..47c8782a 100755
--- a/compiler/tests/18_port_data_8mux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_8mux_1rw_1r_test.py
@@ -4,27 +4,27 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -40,11 +40,12 @@ class port_data_1rw_1r_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_8mux_test.py b/compiler/tests/18_port_data_8mux_test.py
index b74809a2..e2470cbd 100755
--- a/compiler/tests/18_port_data_8mux_test.py
+++ b/compiler/tests/18_port_data_8mux_test.py
@@ -4,22 +4,22 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -42,11 +42,12 @@ class port_data_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_nomux_1rw_1r_test.py b/compiler/tests/18_port_data_nomux_1rw_1r_test.py
index 4ec876c8..5173754f 100755
--- a/compiler/tests/18_port_data_nomux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_nomux_1rw_1r_test.py
@@ -4,27 +4,27 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -38,11 +38,12 @@ class port_data_1rw_1r_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_nomux_test.py b/compiler/tests/18_port_data_nomux_test.py
index 871b0036..304c2e21 100755
--- a/compiler/tests/18_port_data_nomux_test.py
+++ b/compiler/tests/18_port_data_nomux_test.py
@@ -4,22 +4,22 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -40,11 +40,12 @@ class port_data_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py
index 64b66a96..6e0ea480 100755
--- a/compiler/tests/18_port_data_spare_cols_test.py
+++ b/compiler/tests/18_port_data_spare_cols_test.py
@@ -4,22 +4,22 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         c = sram_config(word_size=8,
                         num_words=16,
@@ -62,7 +62,7 @@ class port_data_spare_cols_test(openram_test):
         OPTS.num_rw_ports = 0
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c.num_words=16
         c.words_per_row=1
@@ -105,11 +105,12 @@ class port_data_spare_cols_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py
index 77741cc3..51a83a78 100755
--- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py
@@ -4,27 +4,27 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_wmask_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=16,
                         write_size=4,
@@ -64,7 +64,7 @@ class port_data_wmask_1rw_1r_test(openram_test):
         OPTS.num_rw_ports = 0
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c.num_words = 16
         c.words_per_row = 1
@@ -107,12 +107,12 @@ class port_data_wmask_1rw_1r_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py
index 2d206aac..e3637fbf 100755
--- a/compiler/tests/18_port_data_wmask_test.py
+++ b/compiler/tests/18_port_data_wmask_test.py
@@ -4,23 +4,22 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class port_data_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -69,7 +68,7 @@ class port_data_wmask_test(openram_test):
         OPTS.num_rw_ports = 0
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c.num_words = 16
         c.words_per_row = 1
@@ -112,12 +111,12 @@ class port_data_wmask_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py
index 2ebb9035..45fa9124 100755
--- a/compiler/tests/19_multi_bank_test.py
+++ b/compiler/tests/19_multi_bank_test.py
@@ -6,22 +6,23 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 @unittest.skip("SKIPPING 19_multi_bank_test")
 class multi_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -59,11 +60,12 @@ class multi_bank_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py
index 5749c0dd..4590f7f8 100755
--- a/compiler/tests/19_pmulti_bank_test.py
+++ b/compiler/tests/19_pmulti_bank_test.py
@@ -6,22 +6,23 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 @unittest.skip("SKIPPING 19_pmulti_bank_test")
 class multi_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
         OPTS.bitcell = "pbitcell"
 
         # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent)
@@ -64,11 +65,12 @@ class multi_bank_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py
index 61cbd91a..9c44d439 100755
--- a/compiler/tests/19_psingle_bank_test.py
+++ b/compiler/tests/19_psingle_bank_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psingle_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
@@ -30,7 +30,7 @@ class psingle_bank_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -67,11 +67,12 @@ class psingle_bank_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py
index 027e48a1..ddc6bfab 100755
--- a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=2,
                         num_words=128)
@@ -38,11 +38,12 @@ class single_bank_1rw_1r_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_16mux_test.py b/compiler/tests/19_single_bank_16mux_test.py
index f77a9a27..5630bee2 100755
--- a/compiler/tests/19_single_bank_16mux_test.py
+++ b/compiler/tests/19_single_bank_16mux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -44,11 +44,12 @@ class single_bank_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py
index 2b6829e4..5ad21688 100755
--- a/compiler/tests/19_single_bank_1w_1r_test.py
+++ b/compiler/tests/19_single_bank_1w_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_1w_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 0
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -63,11 +63,12 @@ class single_bank_1w_1r_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py
index 76275e98..aa02236a 100755
--- a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -39,11 +39,12 @@ class single_bank_1rw_1r_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_2mux_test.py b/compiler/tests/19_single_bank_2mux_test.py
index 83e48e00..8006d11f 100755
--- a/compiler/tests/19_single_bank_2mux_test.py
+++ b/compiler/tests/19_single_bank_2mux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -34,11 +34,12 @@ class single_bank_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py
index 57bed230..11768329 100755
--- a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -39,11 +39,12 @@ class single_bank_1rw_1r_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_4mux_test.py b/compiler/tests/19_single_bank_4mux_test.py
index d5cbf640..7d04e715 100755
--- a/compiler/tests/19_single_bank_4mux_test.py
+++ b/compiler/tests/19_single_bank_4mux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -34,11 +34,12 @@ class single_bank_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py
index 01d65bdc..d1bfae89 100755
--- a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -40,11 +40,12 @@ class single_bank_1rw_1r_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_8mux_test.py b/compiler/tests/19_single_bank_8mux_test.py
index 46dfdfcd..9e6ace1b 100755
--- a/compiler/tests/19_single_bank_8mux_test.py
+++ b/compiler/tests/19_single_bank_8mux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -44,11 +44,12 @@ class single_bank_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_global_bitline_test.py b/compiler/tests/19_single_bank_global_bitline_test.py
index e3f942a6..504c49ef 100755
--- a/compiler/tests/19_single_bank_global_bitline_test.py
+++ b/compiler/tests/19_single_bank_global_bitline_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         OPTS.local_array_size = 2
         c = sram_config(word_size=4,
@@ -64,11 +64,12 @@ class single_bank_1rw_1r_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py
index ff31abe8..f01e8c00 100755
--- a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16)
@@ -38,11 +38,12 @@ class single_bank_1rw_1r_test(openram_test):
         a = factory.create(module_type="bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_nomux_test.py b/compiler/tests/19_single_bank_nomux_test.py
index 21724707..675bbcbd 100755
--- a/compiler/tests/19_single_bank_nomux_test.py
+++ b/compiler/tests/19_single_bank_nomux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -42,11 +42,12 @@ class single_bank_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py
index e52aba5d..f7a34704 100755
--- a/compiler/tests/19_single_bank_spare_cols_test.py
+++ b/compiler/tests/19_single_bank_spare_cols_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class single_bank_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         c = sram_config(word_size=4,
                         num_words=16,
@@ -58,11 +59,12 @@ class single_bank_spare_cols_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py
index 908e6655..d7c7ee7d 100755
--- a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class single_bank_wmask_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=8,
                         write_size=4,
@@ -64,11 +64,12 @@ class single_bank_wmask_1rw_1r_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py
index 3c33229d..9c99f373 100755
--- a/compiler/tests/19_single_bank_wmask_test.py
+++ b/compiler/tests/19_single_bank_wmask_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class single_bank_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
-
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         c = sram_config(word_size=8,
                         write_size=4,
@@ -59,11 +59,12 @@ class single_bank_wmask_test(openram_test):
         a = factory.create("bank", sram_config=c)
         self.local_check(a)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
index 1cb73747..d62967fe 100755
--- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
@@ -6,28 +6,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psram_1bank_2mux_1rw_1w_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=32,
@@ -47,11 +47,12 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
index 46c27735..0c554b2d 100755
--- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
@@ -6,28 +6,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=8,
                         write_size=4,
@@ -48,12 +48,12 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
index 2c683be4..c2abb02d 100755
--- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
@@ -6,28 +6,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=32,
@@ -45,11 +45,12 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py
index 25a4f8b1..debf10ef 100755
--- a/compiler/tests/20_psram_1bank_2mux_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_test.py
@@ -6,28 +6,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psram_1bank_2mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=32,
@@ -47,11 +47,12 @@ class psram_1bank_2mux_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
index 7c6a1b10..49598304 100755
--- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
+++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
@@ -6,28 +6,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psram_1bank_4mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=64,
@@ -47,11 +47,12 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py
index 0440c535..874844c5 100755
--- a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_8mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=2,
                         num_words=256,
@@ -46,11 +46,12 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_16mux_test.py b/compiler/tests/20_sram_1bank_16mux_test.py
index a507544d..a94547c7 100755
--- a/compiler/tests/20_sram_1bank_16mux_test.py
+++ b/compiler/tests/20_sram_1bank_16mux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_8mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -50,11 +50,12 @@ class sram_1bank_8mux_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
index b59a76ed..da3ad42e 100755
--- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=32,
@@ -48,11 +48,12 @@ class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
index 4dcc5191..9e5db24a 100755
--- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_2mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=32,
@@ -46,11 +46,11 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py
index e4ba034c..71c2bf5e 100755
--- a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=32,
@@ -48,11 +48,12 @@ class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
index 5627550d..b611d4a7 100755
--- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=32,
@@ -46,11 +46,12 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_2mux_global_test.py b/compiler/tests/20_sram_1bank_2mux_global_test.py
index 92df8a59..4fdf107a 100755
--- a/compiler/tests/20_sram_1bank_2mux_global_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_global_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_2mux_global_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
         OPTS.local_array_size = 8
 
         if OPTS.tech_name == "sky130":
@@ -51,11 +51,12 @@ class sram_1bank_2mux_global_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py
index df69288f..b3c2a7a9 100755
--- a/compiler/tests/20_sram_1bank_2mux_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_2mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -50,11 +50,12 @@ class sram_1bank_2mux_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py
index cb650308..1702f9fe 100755
--- a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_2mux_wmask_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -53,12 +53,12 @@ class sram_1bank_2mux_wmask_spare_cols_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py
index 6b322eac..758d2af6 100755
--- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_2mux_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -52,12 +52,12 @@ class sram_1bank_2mux_wmask_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
index 9a53d04c..f4b7590c 100755
--- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING sram_1bank_32b_1024_wmask_test")
@@ -21,8 +21,8 @@ class sram_1bank_32b_1024_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -52,12 +52,12 @@ class sram_1bank_32b_1024_wmask_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py
index 8224c372..ec014123 100755
--- a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_4mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=64,
@@ -46,11 +46,12 @@ class sram_1bank_4mux_1rw_1r_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py
index c505258d..8d0fc0da 100755
--- a/compiler/tests/20_sram_1bank_4mux_test.py
+++ b/compiler/tests/20_sram_1bank_4mux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_4mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -50,11 +50,12 @@ class sram_1bank_4mux_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
index a6e6ffc6..ea570af6 100755
--- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_8mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=2,
                         num_words=128,
@@ -46,11 +46,12 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py
index d32da29f..63de5333 100755
--- a/compiler/tests/20_sram_1bank_8mux_test.py
+++ b/compiler/tests/20_sram_1bank_8mux_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_8mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -50,11 +50,12 @@ class sram_1bank_8mux_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
index 89c2e8b7..5c161e07 100755
--- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16,
@@ -48,11 +48,12 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
index 2e54fda0..3ced18a1 100755
--- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
@@ -6,27 +6,27 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_nomux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         c = sram_config(word_size=4,
                         num_words=16,
@@ -46,11 +46,12 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py
index 2e7c9c70..7610d9d8 100755
--- a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_nomux_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -51,12 +51,12 @@ class sram_1bank_nomux_spare_cols_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py
index a1440ab2..1e3da295 100755
--- a/compiler/tests/20_sram_1bank_nomux_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_nomux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -49,11 +50,12 @@ class sram_1bank_nomux_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py
index 87631004..b1f69a0e 100755
--- a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_sparecols_test, not working yet")
@@ -21,8 +21,8 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -54,12 +54,12 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py
index 10985ec3..4e38fa4c 100755
--- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py
@@ -6,22 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_nomux_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -52,12 +52,12 @@ class sram_1bank_nomux_wmask_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_1bank_ring_test.py b/compiler/tests/20_sram_1bank_ring_test.py
index af884bf2..5ac417ae 100755
--- a/compiler/tests/20_sram_1bank_ring_test.py
+++ b/compiler/tests/20_sram_1bank_ring_test.py
@@ -6,23 +6,23 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_1bank_nomux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.supply_pin_type = "ring"
-        from modules import sram_config
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -51,11 +51,12 @@ class sram_1bank_nomux_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py
index 7914be7b..88429962 100755
--- a/compiler/tests/20_sram_2bank_test.py
+++ b/compiler/tests/20_sram_2bank_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("Multibank is not working yet.")
@@ -21,8 +21,8 @@ class sram_2bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
         c = sram_config(word_size=16,
                         num_words=32,
                         num_banks=2)
@@ -91,11 +91,12 @@ class sram_2bank_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index e5fdbdb9..2bc80059 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -6,31 +6,32 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 @unittest.skip("SKIPPING 21_hspice_delay_test")
 class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import delay
-        from modules import sram_config
+        from openram.characterizer import delay
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -57,7 +58,7 @@ class timing_sram_test(openram_test):
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
         d = delay(s.s, tempspice, corner)
-        import tech
+        from openram import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
         load_slews = []
@@ -105,11 +106,12 @@ class timing_sram_test(openram_test):
 
         self.assertTrue(self.check_golden_data(data,golden_data,0.25))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py
index dfd5ed68..cd00750c 100755
--- a/compiler/tests/21_hspice_setuphold_test.py
+++ b/compiler/tests/21_hspice_setuphold_test.py
@@ -6,12 +6,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
+import openram
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 21_hspice_setuphold_test")
@@ -19,17 +19,17 @@ class timing_setup_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import setup_hold
-        import tech
+        from openram.characterizer import setup_hold
+        from openram import tech
         slews = [tech.spice["rise_time"]*2]
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
@@ -58,11 +58,12 @@ class timing_setup_test(openram_test):
 
         self.assertTrue(self.check_golden_data(data,golden_data,0.25))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py
index e606d2fd..539c1ab0 100755
--- a/compiler/tests/21_model_delay_test.py
+++ b/compiler/tests/21_model_delay_test.py
@@ -6,14 +6,15 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 # @unittest.skip("SKIPPING 21_model_delay_test")
 class model_delay_test(openram_test):
@@ -21,18 +22,18 @@ class model_delay_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import delay
-        from characterizer import elmore
-        from modules import sram
-        from modules import sram_config
+        from openram.characterizer import delay
+        from openram.characterizer import elmore
+        from openram.modules import sram
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -61,7 +62,7 @@ class model_delay_test(openram_test):
 
         d = delay(s.s, tempspice, corner)
         m = elmore(s.s, tempspice, corner)
-        import tech
+        from openram import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
         load_slews = []
@@ -100,11 +101,12 @@ class model_delay_test(openram_test):
 
         self.assertTrue(self.check_golden_data(spice_delays,model_delays,error_tolerance))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py
index 343373d1..7d7c2f1a 100755
--- a/compiler/tests/21_ngspice_delay_extra_rows_test.py
+++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py
@@ -6,30 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import delay
-        from modules import sram_config
+        from openram.characterizer import delay
+        from openram.modules import sram_config
         c = sram_config(word_size=1,
                         num_words=16,
                         num_banks=1,
@@ -48,7 +49,7 @@ class timing_sram_test(openram_test):
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
         d = delay(s.s, tempspice, corner)
-        import tech
+        from openram import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
         load_slews = []
@@ -97,11 +98,12 @@ class timing_sram_test(openram_test):
 
         self.assertTrue(self.check_golden_data(data,golden_data,0.25))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_ngspice_delay_global_test.py b/compiler/tests/21_ngspice_delay_global_test.py
index 9930cda4..acd9c261 100755
--- a/compiler/tests/21_ngspice_delay_global_test.py
+++ b/compiler/tests/21_ngspice_delay_global_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 21_ngspice_delay_global_test")
@@ -21,17 +21,17 @@ class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import delay
-        from modules import sram_config
+        from openram.characterizer import delay
+        from openram.modules import sram_config
         OPTS.local_array_size = 2
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -65,7 +65,7 @@ class timing_sram_test(openram_test):
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
         d = delay(s.s, tempspice, corner)
-        import tech
+        from openram import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
         load_slews = []
@@ -114,11 +114,12 @@ class timing_sram_test(openram_test):
 
         self.assertTrue(self.check_golden_data(data,golden_data,0.25))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py
index 89561d23..bf632c9a 100755
--- a/compiler/tests/21_ngspice_delay_test.py
+++ b/compiler/tests/21_ngspice_delay_test.py
@@ -6,30 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import delay
-        from modules import sram_config
+        from openram.characterizer import delay
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -56,7 +57,7 @@ class timing_sram_test(openram_test):
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
         d = delay(s.s, tempspice, corner)
-        import tech
+        from openram import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
         load_slews = []
@@ -105,11 +106,12 @@ class timing_sram_test(openram_test):
 
         self.assertTrue(self.check_golden_data(data,golden_data,0.25))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py
index b4e71626..fbfcf543 100755
--- a/compiler/tests/21_ngspice_setuphold_test.py
+++ b/compiler/tests/21_ngspice_setuphold_test.py
@@ -6,29 +6,29 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
+import openram
+from openram import OPTS
 
 
 class timing_setup_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import setup_hold
-        import tech
+        from openram.characterizer import setup_hold
+        from openram import tech
         slews = [tech.spice["rise_time"]*2]
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
@@ -58,11 +58,12 @@ class timing_setup_test(openram_test):
         self.assertTrue(self.check_golden_data(data,golden_data,0.25))
 
         reload(characterizer)
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_regression_delay_test.py b/compiler/tests/21_regression_delay_test.py
index 0955e6d3..70ce3177 100755
--- a/compiler/tests/21_regression_delay_test.py
+++ b/compiler/tests/21_regression_delay_test.py
@@ -6,14 +6,15 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 # @unittest.skip("SKIPPING 21_regression_model_test")
 class regression_model_test(openram_test):
@@ -21,18 +22,18 @@ class regression_model_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import linear_regression
-        from characterizer import neural_network
-        from modules import sram
-        from modules import sram_config
+        from openram.characterizer import linear_regression
+        from openram.characterizer import neural_network
+        from openram.modules import sram
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -66,11 +67,12 @@ class regression_model_test(openram_test):
         accuracy_requirement = 0.75
         self.assertTrue(scores['rise_delay'] >= accuracy_requirement)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py
index 6fae1d9c..7e30f921 100755
--- a/compiler/tests/21_xyce_delay_test.py
+++ b/compiler/tests/21_xyce_delay_test.py
@@ -6,31 +6,31 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="xyce"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import delay
-        from modules import sram_config
+        from openram.characterizer import delay
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -57,7 +57,7 @@ class timing_sram_test(openram_test):
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
         d = delay(s.s, tempspice, corner)
-        import tech
+        from openram import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
         load_slews = []
@@ -105,11 +105,12 @@ class timing_sram_test(openram_test):
 
         self.assertTrue(self.check_golden_data(data,golden_data,0.25))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/21_xyce_setuphold_test.py b/compiler/tests/21_xyce_setuphold_test.py
index 5cc212cf..15159ab2 100755
--- a/compiler/tests/21_xyce_setuphold_test.py
+++ b/compiler/tests/21_xyce_setuphold_test.py
@@ -6,29 +6,29 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
+import openram
+from openram import OPTS
 
 
 class timing_setup_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="Xyce"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import setup_hold
-        import tech
+        from openram.characterizer import setup_hold
+        from openram import tech
         slews = [tech.spice["rise_time"]*2]
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
@@ -57,11 +57,12 @@ class timing_setup_test(openram_test):
 
         self.assertTrue(self.check_golden_data(data,golden_data,0.25))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py
index d44481ba..24ec5ce3 100755
--- a/compiler/tests/22_psram_1bank_2mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_2mux_func_test.py
@@ -6,21 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -35,10 +35,10 @@ class psram_1bank_2mux_func_test(openram_test):
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=32,
                         num_banks=1)
@@ -57,11 +57,12 @@ class psram_1bank_2mux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py
index 084ccf95..cee2e282 100755
--- a/compiler/tests/22_psram_1bank_4mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_4mux_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?")
@@ -21,7 +21,7 @@ class psram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -36,10 +36,10 @@ class psram_1bank_4mux_func_test(openram_test):
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=256,
                         num_banks=1)
@@ -59,11 +59,12 @@ class psram_1bank_4mux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py
index a0151999..b70ae252 100755
--- a/compiler/tests/22_psram_1bank_8mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_8mux_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING 22_psram_1bank_8mux_func_test")
@@ -21,7 +21,7 @@ class psram_1bank_8mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -36,10 +36,10 @@ class psram_1bank_8mux_func_test(openram_test):
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=4,
                         num_words=256,
                         num_banks=1)
@@ -58,11 +58,12 @@ class psram_1bank_8mux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py
index 70b8a0d6..0019fb87 100755
--- a/compiler/tests/22_psram_1bank_nomux_func_test.py
+++ b/compiler/tests/22_psram_1bank_nomux_func_test.py
@@ -6,21 +6,22 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
 
 #@unittest.skip("SKIPPING 22_psram_1bank_nomux_func_test")
 class psram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -35,10 +36,10 @@ class psram_1bank_nomux_func_test(openram_test):
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=32,
                         num_banks=1)
@@ -57,11 +58,12 @@ class psram_1bank_nomux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py
index 6c8988d6..c079dcb0 100755
--- a/compiler/tests/22_sram_1bank_2mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING 22_sram_1bank_2mux_func_test")
@@ -21,17 +21,17 @@ class sram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -56,11 +56,12 @@ class sram_1bank_2mux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_2mux_global_func_test.py b/compiler/tests/22_sram_1bank_2mux_global_func_test.py
index 3e8b16ab..dc9e0987 100755
--- a/compiler/tests/22_sram_1bank_2mux_global_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_global_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING 22_sram_1bank_2mux_func_test")
@@ -21,17 +21,17 @@ class sram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         OPTS.local_array_size = 8
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -57,11 +57,12 @@ class sram_1bank_2mux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py
index 3212a613..e87be09a 100755
--- a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 22_sram_1bank_2mux_sparecols_func_test")
@@ -21,17 +21,17 @@ class sram_1bank_2mux_sparecols_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -57,11 +57,12 @@ class sram_1bank_2mux_sparecols_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py
index 9579377a..ed4ab826 100755
--- a/compiler/tests/22_sram_1bank_4mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_4mux_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING 22_sram_1bank_4mux_func_test")
@@ -21,17 +21,17 @@ class sram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -56,11 +56,12 @@ class sram_1bank_4mux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py
index 8a9dbfdd..6f78c7e1 100755
--- a/compiler/tests/22_sram_1bank_8mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_8mux_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING 22_sram_1bank_8mux_func_test")
@@ -21,20 +21,20 @@ class sram_1bank_8mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from openram.characterizer import functional
         if not OPTS.spice_exe:
             debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
 
-        from modules import sram_config
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -59,11 +59,12 @@ class sram_1bank_8mux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
index 182d700c..aa0e3934 100755
--- a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
+++ b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
@@ -6,21 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class psram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -28,14 +28,14 @@ class psram_1bank_nomux_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=4,
                         num_words=32,
                         num_banks=1)
@@ -51,11 +51,12 @@ class psram_1bank_nomux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py
index c26237a8..c9e78d02 100755
--- a/compiler/tests/22_sram_1bank_nomux_func_test.py
+++ b/compiler/tests/22_sram_1bank_nomux_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING 22_sram_func_test")
@@ -21,17 +21,17 @@ class sram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -56,11 +56,12 @@ class sram_1bank_nomux_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py
index 1dd9c97f..249e9ef2 100755
--- a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py
+++ b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 22_sram_func_test")
@@ -21,17 +21,17 @@ class sram_1bank_nomux_sparecols_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -56,11 +56,12 @@ class sram_1bank_nomux_sparecols_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
index aba82832..e9ef9440 100755
--- a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
+++ b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
@@ -6,21 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_wmask_1w_1r_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -28,14 +28,14 @@ class sram_wmask_1w_1r_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -63,12 +63,12 @@ class sram_wmask_1w_1r_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py
index b5c68910..ea9f8511 100755
--- a/compiler/tests/22_sram_wmask_func_test.py
+++ b/compiler/tests/22_sram_wmask_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING sram_wmask_func_test")
@@ -21,17 +21,17 @@ class sram_wmask_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -58,11 +58,12 @@ class sram_wmask_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/23_lib_sram_linear_regression_test.py b/compiler/tests/23_lib_sram_linear_regression_test.py
index 73c28d5b..640b62f6 100755
--- a/compiler/tests/23_lib_sram_linear_regression_test.py
+++ b/compiler/tests/23_lib_sram_linear_regression_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os, re
 import unittest
 from testutils import *
-import sys, os,re
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
+
 
 #@unittest.skip("SKIPPING 23_lib_sram_linear_regression_test")
 class lib_sram_linear_regression_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.nominal_corner_only = False
         OPTS.netlist_only = True
         OPTS.model_name = "linear_regression"
@@ -31,9 +32,9 @@ class lib_sram_linear_regression_test(openram_test):
             num_spare_rows = 0
             num_spare_cols = 0
 
-        from characterizer import lib
-        from modules import sram
-        from modules import sram_config
+        from openram.characterizer import lib
+        from openram.modules import sram
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,
@@ -63,17 +64,12 @@ class lib_sram_linear_regression_test(openram_test):
             golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
             self.assertTrue(self.isapproxdiff(libname,golden,0.15))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
-
-
-
-
-
-
diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py
index 7cc01d50..9cf60ad4 100755
--- a/compiler/tests/23_lib_sram_model_corners_test.py
+++ b/compiler/tests/23_lib_sram_model_corners_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os, re
 import unittest
 from testutils import *
-import sys, os,re
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
+
 
 #@unittest.skip("SKIPPING 23_lib_sram_model_corners_test")
 class lib_model_corners_lib_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.nominal_corner_only = False
         OPTS.netlist_only = True
 
@@ -30,9 +31,9 @@ class lib_model_corners_lib_test(openram_test):
             num_spare_rows = 0
             num_spare_cols = 0
 
-        from characterizer import lib
-        from modules import sram
-        from modules import sram_config
+        from openram.characterizer import lib
+        from openram.modules import sram
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,
@@ -72,17 +73,12 @@ class lib_model_corners_lib_test(openram_test):
             golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
             self.assertTrue(self.isapproxdiff(libname,golden,0.15))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
-
-
-
-
-
-
diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py
index f70d050b..11102276 100755
--- a/compiler/tests/23_lib_sram_model_test.py
+++ b/compiler/tests/23_lib_sram_model_test.py
@@ -6,20 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os, re
 import unittest
 from testutils import *
-import sys, os,re
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
+
 
 #@unittest.skip("SKIPPING 23_lib_sram_model_test")
 class lib_sram_model_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.nominal_corner_only = False
         OPTS.netlist_only = True
 
@@ -30,9 +31,9 @@ class lib_sram_model_test(openram_test):
             num_spare_rows = 0
             num_spare_cols = 0
 
-        from characterizer import lib
-        from modules import sram
-        from modules import sram_config
+        from openram.characterizer import lib
+        from openram.modules import sram
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,
@@ -62,17 +63,12 @@ class lib_sram_model_test(openram_test):
             golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
             self.assertTrue(self.isapproxdiff(libname,golden,0.15))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
-
-
-
-
-
-
diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py
index 8b93b0d4..7b45b6e0 100755
--- a/compiler/tests/23_lib_sram_prune_test.py
+++ b/compiler/tests/23_lib_sram_prune_test.py
@@ -6,29 +6,30 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os, re
 import unittest
 from testutils import *
-import sys, os,re
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
+
 
 @unittest.skip("SKIPPING 23_lib_sram_prune_test")
 class lib_sram_prune_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import lib
+        from openram.characterizer import lib
         if not OPTS.spice_exe:
             debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
 
@@ -39,8 +40,8 @@ class lib_sram_prune_test(openram_test):
             num_spare_rows = 0
             num_spare_cols = 0
 
-        from modules import sram
-        from modules import sram_config
+        from openram.modules import sram
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,
@@ -72,17 +73,12 @@ class lib_sram_prune_test(openram_test):
             self.assertTrue(self.isapproxdiff(libname,golden,0.40))
 
         reload(characterizer)
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
-
-
-
-
-
-
diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py
index 90cc3ed8..ed1b3324 100755
--- a/compiler/tests/23_lib_sram_test.py
+++ b/compiler/tests/23_lib_sram_test.py
@@ -6,27 +6,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os, re
 import unittest
 from testutils import *
-import sys, os,re
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
+
 
 class lib_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import lib
+        from openram.characterizer import lib
         if not OPTS.spice_exe:
             debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
 
@@ -37,8 +38,8 @@ class lib_test(openram_test):
             num_spare_rows = 0
             num_spare_cols = 0
 
-        from modules import sram
-        from modules import sram_config
+        from openram.modules import sram
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1,
@@ -69,17 +70,12 @@ class lib_test(openram_test):
             self.assertTrue(self.isapproxdiff(libname,golden,0.40))
 
         reload(characterizer)
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
-
-
-
-
-
-
diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py
index 5da40095..33bf22bf 100755
--- a/compiler/tests/24_lef_sram_test.py
+++ b/compiler/tests/24_lef_sram_test.py
@@ -6,13 +6,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 24_lef_sram_test")
@@ -20,11 +20,11 @@ class lef_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
-        from modules import sram
-        from modules import sram_config
+        from openram.modules import sram
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1)
@@ -46,11 +46,12 @@ class lef_test(openram_test):
         golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), leffile)
         self.assertTrue(self.isdiff(lefname, golden))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/25_verilog_multibank_test.py b/compiler/tests/25_verilog_multibank_test.py
index 5f529aa4..0f3c6a8b 100755
--- a/compiler/tests/25_verilog_multibank_test.py
+++ b/compiler/tests/25_verilog_multibank_test.py
@@ -6,25 +6,25 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
-import globals
-from globals import OPTS
-import debug
+
+import openram
+from openram import debug
+from openram import OPTS
 
 
 class multibank_verilog_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
         OPTS.netlist_only=True
-        from modules import sram
-        from modules import sram_config
+        from openram.modules import sram
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=2)
@@ -50,12 +50,12 @@ class multibank_verilog_test(openram_test):
         one_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), v1bfile)
         self.assertTrue(self.isdiff(v1bname, one_golden))
 
-        globals.end_openram()
+        openram.end_openram()
 
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py
index 9d056a8e..07a9986f 100755
--- a/compiler/tests/25_verilog_sram_test.py
+++ b/compiler/tests/25_verilog_sram_test.py
@@ -6,25 +6,25 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
 
 
 class verilog_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
         OPTS.netlist_only=True
-        from modules import sram
-        from modules import sram_config
+        from openram.modules import sram
+        from openram.modules import sram_config
         c = sram_config(word_size=2,
                         num_words=16,
                         num_banks=1)
@@ -44,11 +44,12 @@ class verilog_test(openram_test):
         golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile)
         self.assertTrue(self.isdiff(vname, golden))
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py
index 5d1f4b0e..38ea3a03 100755
--- a/compiler/tests/26_hspice_pex_pinv_test.py
+++ b/compiler/tests/26_hspice_pex_pinv_test.py
@@ -8,13 +8,13 @@
 Run regression tests/pex test on an extracted pinv to ensure pex functionality
 with HSPICE.
 """
+import sys, os
 import unittest
 from testutils import header, openram_test
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 26_hspice_pex_pinv_test")
@@ -22,8 +22,8 @@ class hspice_pex_pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import pinv
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import pinv
 
         # load the hspice
         OPTS.spice_name="hspice"
@@ -31,7 +31,7 @@ class hspice_pex_pinv_test(openram_test):
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
 
         # generate the pinv
@@ -70,7 +70,7 @@ class hspice_pex_pinv_test(openram_test):
         # assert pex_delay > sp_delay, "pex delay {0} is smaller than sp_delay {1}"\
         # .format(pex_delay,sp_delay)
 
-        globals.end_openram()
+        openram.end_openram()
 
     def simulate_delay(self, test_module, top_level_name):
         from charutils import parse_spice_list
@@ -84,8 +84,8 @@ class hspice_pex_pinv_test(openram_test):
 
     def write_simulation(self, sim_file, cir_file, top_module_name):
         """ write pex spice simulation for a pinv test"""
-        import tech
-        from characterizer import measurements, stimuli
+        from openram import tech
+        from openram.characterizer import measurements, stimuli
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
         sim_file = open(OPTS.openram_temp + sim_file, "w")
         simulation = stimuli(sim_file, corner)
@@ -131,7 +131,7 @@ class hspice_pex_pinv_test(openram_test):
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main()
diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py
index c4d77bba..2963ea40 100755
--- a/compiler/tests/26_ngspice_pex_pinv_test.py
+++ b/compiler/tests/26_ngspice_pex_pinv_test.py
@@ -8,20 +8,21 @@
 Run regression tests/pex test on an extracted pinv to ensure pex functionality
 with Ngspice.
 """
+import sys, os
 import unittest
 from testutils import header,openram_test
-import sys, os
 
-import globals
-from globals import OPTS
-import debug
+import openram
+from openram import debug
+from openram import OPTS
+
 
 @unittest.skip("SKIPPING 26_ngspice_pex_pinv_test")
 class ngspice_pex_pinv_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        import pinv
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import pinv
 
         # load the ngspice
         OPTS.spice_name="ngspice"
@@ -29,7 +30,7 @@ class ngspice_pex_pinv_test(openram_test):
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
 
         # generate the pinv module
@@ -68,7 +69,7 @@ class ngspice_pex_pinv_test(openram_test):
         # assert pex_delay > sp_delay, "pex delay {0} is smaller than sp_delay {1}"\
         # .format(pex_delay,sp_delay)
 
-        globals.end_openram()
+        openram.end_openram()
 
     def simulate_delay(self, test_module, top_level_name):
         from charutils import parse_spice_list
@@ -87,8 +88,8 @@ class ngspice_pex_pinv_test(openram_test):
 
     def write_simulation(self, sim_file, cir_file, top_module_name):
         """ write pex spice simulation for a pinv test"""
-        import tech
-        from characterizer import measurements, stimuli
+        from openram import tech
+        from openram.characterizer import measurements, stimuli
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
         sim_file = open(sim_file, "w")
         simulation = stimuli(sim_file, corner)
@@ -135,9 +136,10 @@ class ngspice_pex_pinv_test(openram_test):
         sim_file.close()
         return simulation
 
+
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main()
diff --git a/compiler/tests/26_sram_pex_test.py b/compiler/tests/26_sram_pex_test.py
index 13fa3b8b..1dfe7484 100755
--- a/compiler/tests/26_sram_pex_test.py
+++ b/compiler/tests/26_sram_pex_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 26_sram_pex_test")
@@ -21,16 +21,16 @@ class sram_pex_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.use_pex = True
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=4,
                         num_words=32,
                         num_banks=1)
@@ -49,11 +49,12 @@ class sram_pex_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py
index b23a20d9..818c4c05 100755
--- a/compiler/tests/30_openram_back_end_test.py
+++ b/compiler/tests/30_openram_back_end_test.py
@@ -6,14 +6,15 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os, re
+import shutil
+import getpass
 import unittest
 from testutils import *
-import sys, os, re, shutil
 
-import globals
-from globals import OPTS
-import debug
-import getpass
+import openram
+from openram import debug
+from openram import OPTS
 
 
 class openram_back_end_test(openram_test):
@@ -21,7 +22,7 @@ class openram_back_end_test(openram_test):
     def runTest(self):
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
         config_file = "{}/tests/configs/config_back_end".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing top-level back-end sram_compiler.py with 2-bit, 16 word SRAM.")
         out_file = "testsram"
@@ -102,11 +103,11 @@ class openram_back_end_test(openram_test):
                 shutil.rmtree(out_path, ignore_errors=True)
             self.assertEqual(os.path.exists(out_path), False)
 
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py
index 3202aa03..8a863ad8 100755
--- a/compiler/tests/30_openram_front_end_test.py
+++ b/compiler/tests/30_openram_front_end_test.py
@@ -6,14 +6,15 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os, re
+import shutil
+import getpass
 import unittest
 from testutils import *
-import sys, os, re, shutil
 
-import globals
-from globals import OPTS
-import debug
-import getpass
+import openram
+from openram import debug
+from openram import OPTS
 
 
 class openram_front_end_test(openram_test):
@@ -21,7 +22,7 @@ class openram_front_end_test(openram_test):
     def runTest(self):
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
         config_file = "{}/tests/configs/config_front_end".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing top-level front-end sram_compiler.py with 2-bit, 16 word SRAM.")
         out_file = "testsram"
@@ -96,11 +97,12 @@ class openram_front_end_test(openram_test):
                 shutil.rmtree(out_path, ignore_errors=True)
             self.assertEqual(os.path.exists(out_path), False)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_1k_1rw1r_func_test.py b/compiler/tests/50_riscv_1k_1rw1r_func_test.py
index bf8744fa..b2663a07 100755
--- a/compiler/tests/50_riscv_1k_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_1k_1rw1r_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=256,
@@ -54,11 +54,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_1k_1rw_func_test.py b/compiler/tests/50_riscv_1k_1rw_func_test.py
index 4af2fd99..f9d8a379 100755
--- a/compiler/tests/50_riscv_1k_1rw_func_test.py
+++ b/compiler/tests/50_riscv_1k_1rw_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=256,
@@ -56,11 +56,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_1rw1r_func_test.py b/compiler/tests/50_riscv_1rw1r_func_test.py
index 91ea6716..dcc2044b 100755
--- a/compiler/tests/50_riscv_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_1rw1r_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -29,14 +29,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=32,
@@ -54,11 +54,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_1rw1r_phys_test.py b/compiler/tests/50_riscv_1rw1r_phys_test.py
index 3236d824..ebba5f9d 100755
--- a/compiler/tests/50_riscv_1rw1r_phys_test.py
+++ b/compiler/tests/50_riscv_1rw1r_phys_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 # @unittest.skip("SKIPPING 50_riscv_phys_test")
@@ -21,14 +21,14 @@ class riscv_phys_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
         OPTS.local_array_size = 16
-        globals.setup_bitcell()
+        openram.setup_bitcell()
         OPTS.route_supplies = False
         OPTS.perimeter_pins = False
 
@@ -51,11 +51,12 @@ class riscv_phys_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py
index 248757b5..2a96a74f 100755
--- a/compiler/tests/50_riscv_1rw_func_test.py
+++ b/compiler/tests/50_riscv_1rw_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -37,14 +37,14 @@ class riscv_func_test(openram_test):
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
         OPTS.local_array_size = 16
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=64,
@@ -64,11 +64,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_1rw_phys_test.py b/compiler/tests/50_riscv_1rw_phys_test.py
index 9e8a5b93..6f9f4896 100755
--- a/compiler/tests/50_riscv_1rw_phys_test.py
+++ b/compiler/tests/50_riscv_1rw_phys_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 #@unittest.skip("SKIPPING 50_riscv_phys_test")
@@ -21,8 +21,8 @@ class riscv_phys_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
-        from modules import sram_config
+        openram.init_openram(config_file, is_unit_test=True)
+        from openram.modules import sram_config
 
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
@@ -35,7 +35,7 @@ class riscv_phys_test(openram_test):
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
         OPTS.local_array_size = 16
-        globals.setup_bitcell()
+        openram.setup_bitcell()
         OPTS.route_supplies = False
         OPTS.perimeter_pins = False
 
@@ -59,11 +59,12 @@ class riscv_phys_test(openram_test):
         a = factory.create(module_type="sram", sram_config=c)
         self.local_check(a, final_verification=True)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_2k_1rw1r_func_test.py b/compiler/tests/50_riscv_2k_1rw1r_func_test.py
index 538f5f06..742337d8 100755
--- a/compiler/tests/50_riscv_2k_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_2k_1rw1r_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=512,
@@ -54,11 +54,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_2k_1rw_func_test.py b/compiler/tests/50_riscv_2k_1rw_func_test.py
index 422de33f..17ad0eaa 100755
--- a/compiler/tests/50_riscv_2k_1rw_func_test.py
+++ b/compiler/tests/50_riscv_2k_1rw_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=512,
@@ -56,11 +56,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_4k_1rw1r_func_test.py b/compiler/tests/50_riscv_4k_1rw1r_func_test.py
index 76817e24..14697adc 100755
--- a/compiler/tests/50_riscv_4k_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_4k_1rw1r_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=1024,
@@ -54,11 +54,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_4k_1rw_func_test.py b/compiler/tests/50_riscv_4k_1rw_func_test.py
index 911549c0..6c905834 100755
--- a/compiler/tests/50_riscv_4k_1rw_func_test.py
+++ b/compiler/tests/50_riscv_4k_1rw_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=1024,
@@ -56,11 +56,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_512b_1rw1r_func_test.py b/compiler/tests/50_riscv_512b_1rw1r_func_test.py
index 21854a24..3c2cc88e 100755
--- a/compiler/tests/50_riscv_512b_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_512b_1rw1r_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=128,
@@ -54,11 +54,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_512b_1rw_func_test.py b/compiler/tests/50_riscv_512b_1rw_func_test.py
index b5101e49..f3aa0ead 100755
--- a/compiler/tests/50_riscv_512b_1rw_func_test.py
+++ b/compiler/tests/50_riscv_512b_1rw_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=128,
@@ -56,11 +56,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_8k_1rw1r_func_test.py b/compiler/tests/50_riscv_8k_1rw1r_func_test.py
index 128b5615..d5e3d942 100755
--- a/compiler/tests/50_riscv_8k_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_8k_1rw1r_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=2048,
@@ -54,11 +54,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/50_riscv_8k_1rw_func_test.py b/compiler/tests/50_riscv_8k_1rw_func_test.py
index a2696aca..5a466c33 100755
--- a/compiler/tests/50_riscv_8k_1rw_func_test.py
+++ b/compiler/tests/50_riscv_8k_1rw_func_test.py
@@ -6,14 +6,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 @unittest.skip("SKIPPING 50_riscv_func_test")
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file, is_unit_test=True)
+        openram.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
@@ -30,14 +30,14 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
-        globals.setup_bitcell()
+        openram.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
-        import characterizer
+        from openram import characterizer
         reload(characterizer)
-        from characterizer import functional
-        from modules import sram_config
+        from openram.characterizer import functional
+        from openram.modules import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
                         num_words=2048,
@@ -56,11 +56,12 @@ class riscv_func_test(openram_test):
         (fail, error) = f.run()
         self.assertTrue(fail, error)
 
-        globals.end_openram()
+        openram.end_openram()
+
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/configs/config.py b/compiler/tests/configs/config.py
index 44c3e774..356defca 100644
--- a/compiler/tests/configs/config.py
+++ b/compiler/tests/configs/config.py
@@ -5,7 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from globals import OPTS
+from openram import OPTS
 word_size = 1
 num_words = 16
 
diff --git a/compiler/tests/configs/config_back_end.py b/compiler/tests/configs/config_back_end.py
index 4bf0aa8b..42354e34 100644
--- a/compiler/tests/configs/config_back_end.py
+++ b/compiler/tests/configs/config_back_end.py
@@ -5,7 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from globals import OPTS
+from openram import OPTS
 word_size = 2
 num_words = 16
 
diff --git a/compiler/tests/configs/config_front_end.py b/compiler/tests/configs/config_front_end.py
index 2b42a914..c2c61701 100644
--- a/compiler/tests/configs/config_front_end.py
+++ b/compiler/tests/configs/config_front_end.py
@@ -5,7 +5,7 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from globals import OPTS
+from openram import OPTS
 word_size = 2
 num_words = 16
 
diff --git a/compiler/tests/regress.py b/compiler/tests/regress.py
index 6499f20c..4a707351 100755
--- a/compiler/tests/regress.py
+++ b/compiler/tests/regress.py
@@ -10,8 +10,7 @@
 import re
 import unittest
 import sys, os
-sys.path.append(os.getenv("OPENRAM_HOME"))
-import globals
+from openram import globals
 from subunit import ProtocolTestCase, TestProtocolClient
 from testtools import ConcurrentTestSuite
 
diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py
index bd4a7aa2..e231b8ee 100644
--- a/compiler/tests/testutils.py
+++ b/compiler/tests/testutils.py
@@ -7,11 +7,11 @@
 #
 import unittest
 import sys, os, glob
-from globals import OPTS
-import debug
 import pdb
 import traceback
 import time
+from openram import debug
+from openram import OPTS
 
 
 class openram_test(unittest.TestCase):
@@ -47,7 +47,7 @@ class openram_test(unittest.TestCase):
 
         tempgds = "{}.gds".format(w.name)
         w.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
-        import verify
+        from openram import verify
 
         result=verify.run_drc(w.name, tempgds, None)
         if result != 0:
@@ -67,7 +67,7 @@ class openram_test(unittest.TestCase):
         if not OPTS.netlist_only:
             a.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
 
-            import verify
+            from openram import verify
             # Run both DRC and LVS even if DRC might fail
             # Magic can still extract despite DRC failing, so it might be ok in some techs
             # if we ignore things like minimum metal area of pins
@@ -108,7 +108,7 @@ class openram_test(unittest.TestCase):
 
         a.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
 
-        import verify
+        from openram import verify
         result=verify.run_pex(a.name, tempgds, tempspice, final_verification=False)
         if result != 0:
             self.fail("PEX ERROR: {}".format(a.name))
@@ -139,7 +139,7 @@ class openram_test(unittest.TestCase):
         Reset everything after each test.
         """
         # Reset the static duplicate name checker for unit tests.
-        from base import hierarchy_design
+        from openram.base import hierarchy_design
         hierarchy_design.name_map=[]
 
     def check_golden_data(self, data, golden_data, error_tolerance=1e-2):
@@ -167,7 +167,7 @@ class openram_test(unittest.TestCase):
 
     def isclose(self, key, value, actual_value, error_tolerance=1e-2):
         """ This is used to compare relative values. """
-        import debug
+        from openram import debug
         relative_diff = self.relative_diff(value, actual_value)
         check = relative_diff <= error_tolerance
         if check:
@@ -215,7 +215,7 @@ class openram_test(unittest.TestCase):
 
         """
         import re
-        import debug
+        from openram import debug
 
         numeric_const_pattern = r"""
         [-+]? # optional sign
@@ -294,7 +294,7 @@ class openram_test(unittest.TestCase):
 
     def isdiff(self, filename1, filename2):
         """ This is used to compare two files and display the diff if they are different.. """
-        import debug
+        from openram import debug
         import filecmp
         import difflib
         check = filecmp.cmp(filename1, filename2)
@@ -338,7 +338,7 @@ def header(filename, technology):
     print("|=========" + tst.center(60) + "=========|")
     print("|=========" + technology.center(60) + "=========|")
     print("|=========" + filename.center(60) + "=========|")
-    from globals import OPTS
+    from openram import OPTS
     if OPTS.openram_temp:
         print("|=========" + OPTS.openram_temp.center(60) + "=========|")
     print("|==============================================================================|")
diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py
index b4a3f254..463a71a4 100644
--- a/compiler/verify/__init__.py
+++ b/compiler/verify/__init__.py
@@ -15,12 +15,11 @@ run_pex, repsectively. If there is an error, they should abort and report the er
 If not, OpenRAM will continue as if nothing happened!
 """
 
-import debug
-from globals import OPTS
-from globals import get_tool
-from tech import drc_name
-from tech import lvs_name
-from tech import pex_name
+from openram import debug
+from openram.tech import drc_name
+from openram.tech import lvs_name
+from openram.tech import pex_name
+from openram import OPTS, get_tool
 
 debug.info(1, "Initializing verify...")
 if not OPTS.check_lvsdrc:
diff --git a/compiler/verify/assura.py b/compiler/verify/assura.py
index 64c482a1..4c51af9d 100644
--- a/compiler/verify/assura.py
+++ b/compiler/verify/assura.py
@@ -25,12 +25,11 @@ drc["lvs_subcircuits"] variable, and additional options must be
 inserted in the runset.
 """
 
-
 import os
 import re
-from run_script import *
-import debug
-from globals import OPTS
+from openram import debug
+from openram.verify.run_script import *
+from openram import OPTS
 
 # Keep track of statistics
 num_drc_runs = 0
@@ -39,7 +38,7 @@ num_pex_runs = 0
 
 
 def write_drc_script(cell_name, gds_name, extract, final_verification, output_path):
-    from tech import drc
+    from openram.tech import drc
     drc_rules = drc["drc_rules"]
     drc_runset = output_path + cell_name + ".rsf"
     drc_log_file = "{0}{1}.log".format(OPTS.openram_temp, name)
@@ -108,7 +107,7 @@ def run_drc(name, gds_name, final_verification=False):
 
 def write_lvs_script(cell_name, gds_name, sp_name, final_verification, output_path):
 
-    from tech import drc
+    from openram.tech import drc
     lvs_rules = drc["lvs_rules"]
     lvs_runset = output_path + name + ".rsf"
     # The LVS compare rules must be defined in the tech file for Assura.
diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py
index 32c5c5a9..84cecfbb 100644
--- a/compiler/verify/calibre.py
+++ b/compiler/verify/calibre.py
@@ -16,11 +16,10 @@ Calibre means pointing the code to the proper DRC and LVS rule files.
 
 """
 
-
 import os
 import re
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 from .run_script import run_script
 
 # Keep track of statistics
@@ -36,7 +35,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification=False, out
     if not output_path:
         output_path = OPTS.openram_temp
 
-    from tech import drc
+    from openram.tech import drc
     drc_rules = drc["drc_rules"]
 
     drc_runset = {
@@ -77,7 +76,7 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out
     if not output_path:
         output_path = OPTS.openram_temp
 
-    from tech import drc
+    from openram.tech import drc
     lvs_rules = drc["lvs_rules"]
     lvs_runset = {
         'lvsRulesFile': lvs_rules,
@@ -151,7 +150,7 @@ def write_pex_script(cell_name, extract, output, final_verification=False, outpu
         run_drc(cell_name, gds_name, sp_name)
         run_lvs(cell_name, gds_name, sp_name)
 
-    from tech import drc
+    from openram.tech import drc
     pex_rules = drc["xrc_rules"]
     pex_runset = {
         'pexRulesFile': pex_rules,
diff --git a/compiler/verify/klayout.py b/compiler/verify/klayout.py
index 73cec474..00c48baa 100644
--- a/compiler/verify/klayout.py
+++ b/compiler/verify/klayout.py
@@ -10,12 +10,11 @@ This is a DRC/LVS/PEX interface file for klayout.
 
 """
 
-
 import os
 import re
 import shutil
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 from .run_script import *
 
 # Keep track of statistics
diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py
index a3e0e511..da3ec851 100644
--- a/compiler/verify/magic.py
+++ b/compiler/verify/magic.py
@@ -19,12 +19,11 @@ We obtained this file from Qflow ( http://opencircuitdesign.com/qflow/index.html
 and include its appropriate license.
 """
 
-
 import os
 import re
 import shutil
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 from .run_script import *
 # Keep track of statistics
 num_drc_runs = 0
@@ -96,12 +95,12 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
     # Flatten the transistors
     # Bug in Netgen 1.5.194 when using this...
     try:
-        from tech import blackbox_cells
+        from openram.tech import blackbox_cells
     except ImportError:
         blackbox_cells = []
 
     try:
-        from tech import flatglob
+        from openram.tech import flatglob
     except ImportError:
         flatglob = []
         f.write("gds readonly true\n")
diff --git a/compiler/verify/none.py b/compiler/verify/none.py
index 8385be11..73d7c2df 100644
--- a/compiler/verify/none.py
+++ b/compiler/verify/none.py
@@ -7,9 +7,9 @@
 #
 """
 This is a DRC/LVS/PEX interface file the case with no DRC/LVS tools.
-
 """
-import debug
+
+from openram import debug
 
 # Only print the warning once.
 drc_warned = False
diff --git a/compiler/verify/run_script.py b/compiler/verify/run_script.py
index 1c4cc0dd..541ac9b9 100644
--- a/compiler/verify/run_script.py
+++ b/compiler/verify/run_script.py
@@ -10,10 +10,10 @@ Some baseline functions to run scripts.
 """
 
 import os
-import debug
 import subprocess
 import time
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 
 
 def run_script(cell_name, script="lvs"):
diff --git a/sram_compiler.py b/sram_compiler.py
index 1a2d42b9..1be28df8 100755
--- a/sram_compiler.py
+++ b/sram_compiler.py
@@ -16,8 +16,8 @@ a LEF (.lef) file for preliminary P&R (real one should be from layout)
 a Liberty (.lib) file for timing analysis/optimization
 """
 
-import os
 import sys
+import os
 import datetime
 try:
     import openram
@@ -43,7 +43,7 @@ if len(args) != 1:
 
 
 # These depend on arguments, so don't load them until now.
-import debug
+from openram import debug
 
 # Parse config file and set up all the options
 openram.init_openram(config_file=args[0])
@@ -61,7 +61,7 @@ openram.print_time("Start", start_time)
 # Output info about this run
 openram.report_status()
 
-from modules import sram_config
+from openram.modules import sram_config
 
 
 # Configure the SRAM organization
@@ -87,7 +87,7 @@ for path in output_files:
     debug.print_raw(path)
 
 
-from modules import sram
+from openram.modules import sram
 s = sram(name=OPTS.output_name,
          sram_config=c)
 
@@ -98,4 +98,3 @@ s.save()
 openram.end_openram()
 openram.print_time("End", datetime.datetime.now(), start_time)
 
-
diff --git a/technology/freepdk45/__init__.py b/technology/freepdk45/__init__.py
index 6d9e759d..24f05246 100644
--- a/technology/freepdk45/__init__.py
+++ b/technology/freepdk45/__init__.py
@@ -13,7 +13,7 @@ the trunk
 
 import sys
 import os
-import debug
+from openram import debug
 
 TECHNOLOGY = "freepdk45"
 
diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py
index 76522ff3..0f082eb3 100644
--- a/technology/freepdk45/tech/tech.py
+++ b/technology/freepdk45/tech/tech.py
@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 import os
-import drc as d
+from openram import drc as d
 #from drc.design_rules import design_rules
 #from drc.module_type import module_type
 #from drc.custom_cell_properties import cell_properties
diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py
index 39ca0cfc..6e8b599f 100755
--- a/technology/scn3me_subm/tech/tech.py
+++ b/technology/scn3me_subm/tech/tech.py
@@ -1,7 +1,7 @@
 import os
-from design_rules import *
-from module_type import *
-from custom_cell_properties import CellProperties
+from openram.drc.design_rules import *
+from openram.drc.module_type import *
+from openram.drc.custom_cell_properties import CellProperties
 
 """
 File containing the process technology parameters for SCMOS 3me, subm, 180nm.
@@ -306,4 +306,4 @@ pex_name = "magic"
 ##END Technology Tool Preferences
 ###################################################
 array_row_multiple = 1
-array_col_multiple = 1
\ No newline at end of file
+array_col_multiple = 1
diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py
index e940ce29..86c3f03b 100644
--- a/technology/scn4m_subm/tech/tech.py
+++ b/technology/scn4m_subm/tech/tech.py
@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 import os
-import drc as d
+from openram import drc as d
 #from drc.design_rules import design_rules
 #from drc.module_type import module_type
 #from drc.custom_cell_properties import cell_properties
diff --git a/technology/sky130/custom/sky130_bitcell.py b/technology/sky130/custom/sky130_bitcell.py
index 908ff45d..f47ad843 100644
--- a/technology/sky130/custom/sky130_bitcell.py
+++ b/technology/sky130/custom/sky130_bitcell.py
@@ -5,9 +5,9 @@
 # All rights reserved.
 #
 
-import debug
-from tech import cell_properties as props
-from modules import bitcell_base
+from openram import debug
+from openram.modules import bitcell_base
+from openram.tech import cell_properties as props
 
 
 class sky130_bitcell(bitcell_base):
diff --git a/technology/sky130/custom/sky130_bitcell_array.py b/technology/sky130/custom/sky130_bitcell_array.py
index d6e4066c..eb231c8f 100644
--- a/technology/sky130/custom/sky130_bitcell_array.py
+++ b/technology/sky130/custom/sky130_bitcell_array.py
@@ -5,11 +5,11 @@
 # All rights reserved.
 #
 
-import debug
-from modules import bitcell_array
+from openram import debug
+from openram.modules import bitcell_array
+from openram.sram_factory import factory
+from openram import OPTS
 from .sky130_bitcell_base_array import sky130_bitcell_base_array
-from globals import OPTS
-from sram_factory import factory
 
 
 class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
diff --git a/technology/sky130/custom/sky130_bitcell_base_array.py b/technology/sky130/custom/sky130_bitcell_base_array.py
index 50199c77..d4134cd0 100644
--- a/technology/sky130/custom/sky130_bitcell_base_array.py
+++ b/technology/sky130/custom/sky130_bitcell_base_array.py
@@ -5,12 +5,12 @@
 # All rights reserved.
 #
 
-import debug
-from base import geometry
-from sram_factory import factory
-from modules import bitcell_base_array
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import geometry
+from openram.modules import bitcell_base_array
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class sky130_bitcell_base_array(bitcell_base_array):
@@ -154,7 +154,7 @@ class sky130_bitcell_base_array(bitcell_base_array):
 
                     if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins:
                         try:
-                            from tech import layer_override
+                            from openram.tech import layer_override
                             if layer_override['VNB']:
                                 pin = inst.get_pin("vnb")
                                 self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
diff --git a/technology/sky130/custom/sky130_col_cap.py b/technology/sky130/custom/sky130_col_cap.py
index eb2383e5..24a7171e 100644
--- a/technology/sky130/custom/sky130_col_cap.py
+++ b/technology/sky130/custom/sky130_col_cap.py
@@ -5,9 +5,9 @@
 # All rights reserved.
 #
 
-import debug
-from base import design
-from tech import cell_properties as props
+from openram import debug
+from openram.base import design
+from openram.tech import cell_properties as props
 
 
 class sky130_col_cap(design):
diff --git a/technology/sky130/custom/sky130_col_cap_array.py b/technology/sky130/custom/sky130_col_cap_array.py
index 940296d3..5ee45f9d 100644
--- a/technology/sky130/custom/sky130_col_cap_array.py
+++ b/technology/sky130/custom/sky130_col_cap_array.py
@@ -5,11 +5,11 @@
 # All rights reserved.
 #
 
-from sram_factory import factory
+from openram.base import geometry
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 from .sky130_bitcell_base_array import sky130_bitcell_base_array
-from globals import OPTS
-from base import geometry
-from tech import layer
 
 class sky130_col_cap_array(sky130_bitcell_base_array):
     """
@@ -230,7 +230,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
                 
             if 'VNB' or 'vnb' in self.cell_inst[col].mod.pins:
                 try:
-                    from tech import layer_override
+                    from openram.tech import layer_override
                     if layer_override['VNB']:
                         pin = inst.get_pin("vnb")
                         self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
diff --git a/technology/sky130/custom/sky130_corner.py b/technology/sky130/custom/sky130_corner.py
index 858a0a4a..269952d5 100644
--- a/technology/sky130/custom/sky130_corner.py
+++ b/technology/sky130/custom/sky130_corner.py
@@ -5,10 +5,10 @@
 # All rights reserved.
 #
 
-import debug
-from base import design
-from base import get_libcell_size
-from tech import layer, GDS
+from openram import debug
+from openram.base import design
+from openram.base import get_libcell_size
+from openram.tech import layer, GDS
 
 
 class sky130_corner(design):
diff --git a/technology/sky130/custom/sky130_dummy_array.py b/technology/sky130/custom/sky130_dummy_array.py
index bfdca620..8a2393b0 100644
--- a/technology/sky130/custom/sky130_dummy_array.py
+++ b/technology/sky130/custom/sky130_dummy_array.py
@@ -5,11 +5,11 @@
 # All rights reserved.
 #
 
+from openram.base import geometry
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 from .sky130_bitcell_base_array import sky130_bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
-from base import geometry
-from tech import layer
 
 class sky130_dummy_array(sky130_bitcell_base_array):
     """
@@ -177,7 +177,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
 
                 if 'VNB' or 'vnb' in self.cell_inst[row, col].mod.pins:
                     try:
-                        from tech import layer_override
+                        from openram.tech import layer_override
                         if layer_override['VNB']:
                             pin = inst.get_pin("vnb")
                             self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
diff --git a/technology/sky130/custom/sky130_dummy_bitcell.py b/technology/sky130/custom/sky130_dummy_bitcell.py
index 58ef8026..eb7ab7b9 100644
--- a/technology/sky130/custom/sky130_dummy_bitcell.py
+++ b/technology/sky130/custom/sky130_dummy_bitcell.py
@@ -5,9 +5,9 @@
 # All rights reserved.
 #
 
-import debug
-from tech import cell_properties as props
-from modules import bitcell_base
+from openram import debug
+from openram.modules import bitcell_base
+from openram.tech import cell_properties as props
 
 
 class sky130_dummy_bitcell(bitcell_base):
diff --git a/technology/sky130/custom/sky130_internal.py b/technology/sky130/custom/sky130_internal.py
index 83bdd42c..63f3fc8f 100644
--- a/technology/sky130/custom/sky130_internal.py
+++ b/technology/sky130/custom/sky130_internal.py
@@ -6,8 +6,8 @@
 #
 
 from copy import deepcopy
-from modules import internal_base
-from tech import cell_properties as props
+from openram.modules import internal_base
+from openram.tech import cell_properties as props
 
 class sky130_internal(internal_base):
 
diff --git a/technology/sky130/custom/sky130_replica_bitcell.py b/technology/sky130/custom/sky130_replica_bitcell.py
index 2b30fb7a..ca0797c2 100644
--- a/technology/sky130/custom/sky130_replica_bitcell.py
+++ b/technology/sky130/custom/sky130_replica_bitcell.py
@@ -5,11 +5,11 @@
 # All rights reserved.
 #
 
-import debug
-from modules import bitcell_base
-from base import logical_effort
-from tech import parameter, drc
-from tech import cell_properties as props
+from openram import debug
+from openram.base import logical_effort
+from openram.modules import bitcell_base
+from openram.tech import parameter, drc
+from openram.tech import cell_properties as props
 
 
 class sky130_replica_bitcell(bitcell_base):
@@ -43,7 +43,7 @@ class sky130_replica_bitcell(bitcell_base):
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
+        from openram.tech import spice
         leakage = spice["bitcell_leakage"]
         dynamic = 0 # temporary
         total_power = self.return_power(dynamic, leakage)
diff --git a/technology/sky130/custom/sky130_replica_bitcell_array.py b/technology/sky130/custom/sky130_replica_bitcell_array.py
index 93ea3f0b..a6ec49ce 100644
--- a/technology/sky130/custom/sky130_replica_bitcell_array.py
+++ b/technology/sky130/custom/sky130_replica_bitcell_array.py
@@ -5,16 +5,16 @@
 # All rights reserved.
 #
 
-import debug
-from modules import replica_bitcell_array
-from base import vector
-from .sky130_bitcell_base_array import sky130_bitcell_base_array
-from base import round_to_grid
 from math import sqrt
-from tech import drc
-from tech import array_row_multiple
-from tech import array_col_multiple
-from globals import OPTS
+from openram import debug
+from openram.base import vector
+from openram.base import round_to_grid
+from openram.modules import replica_bitcell_array
+from openram.tech import drc
+from openram.tech import array_row_multiple
+from openram.tech import array_col_multiple
+from openram import OPTS
+from .sky130_bitcell_base_array import sky130_bitcell_base_array
 
 
 class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_array):
diff --git a/technology/sky130/custom/sky130_replica_column.py b/technology/sky130/custom/sky130_replica_column.py
index 66999542..f7fedf7e 100644
--- a/technology/sky130/custom/sky130_replica_column.py
+++ b/technology/sky130/custom/sky130_replica_column.py
@@ -5,12 +5,12 @@
 # All rights reserved.
 #
 
-import debug
+from openram import debug
+from openram.base import geometry
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 from .sky130_bitcell_base_array import sky130_bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
-from base import geometry
-from tech import layer
 
 
 class sky130_replica_column(sky130_bitcell_base_array):
@@ -246,7 +246,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
 
                 if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
                     try:
-                        from tech import layer_override
+                        from openram.tech import layer_override
                         if layer_override['VNB']:
                             pin = inst.get_pin("vnb")
                             self.add_label("gnd", pin.layer, pin.center())
diff --git a/technology/sky130/custom/sky130_row_cap.py b/technology/sky130/custom/sky130_row_cap.py
index 1c81b8dd..ac1534a2 100644
--- a/technology/sky130/custom/sky130_row_cap.py
+++ b/technology/sky130/custom/sky130_row_cap.py
@@ -5,9 +5,9 @@
 # All rights reserved.
 #
 
-import debug
-from base import design
-from tech import cell_properties as props
+from openram import debug
+from openram.base import design
+from openram.tech import cell_properties as props
 
 
 class sky130_row_cap(design):
diff --git a/technology/sky130/custom/sky130_row_cap_array.py b/technology/sky130/custom/sky130_row_cap_array.py
index 45b63c77..620850e2 100644
--- a/technology/sky130/custom/sky130_row_cap_array.py
+++ b/technology/sky130/custom/sky130_row_cap_array.py
@@ -5,9 +5,9 @@
 # All rights reserved.
 #
 
-from sram_factory import factory
+from openram.sram_factory import factory
+from openram import OPTS
 from .sky130_bitcell_base_array import sky130_bitcell_base_array
-from globals import OPTS
 
 
 class sky130_row_cap_array(sky130_bitcell_base_array):
diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py
index 443a61b6..15600b38 100755
--- a/technology/sky130/tech/tech.py
+++ b/technology/sky130/tech/tech.py
@@ -7,7 +7,7 @@
 
 
 import os
-import drc as d
+from openram import drc as d
 
 """
 File containing the process technology parameters for Skywater 130nm.