Use library imports globally

compiler/verify/__init__.py

@@ -15,12 +15,11 @@ run_pex, repsectively. If there is an error, they should abort and report the er
 If not, OpenRAM will continue as if nothing happened!
 """
 
-import debug
-from globals import OPTS
-from globals import get_tool
-from tech import drc_name
-from tech import lvs_name
-from tech import pex_name
+from openram import debug
+from openram.tech import drc_name
+from openram.tech import lvs_name
+from openram.tech import pex_name
+from openram import OPTS, get_tool
 
 debug.info(1, "Initializing verify...")
 if not OPTS.check_lvsdrc:

compiler/verify/assura.py

@@ -25,12 +25,11 @@ drc["lvs_subcircuits"] variable, and additional options must be
 inserted in the runset.
 """
 
-
 import os
 import re
-from run_script import *
-import debug
-from globals import OPTS
+from openram import debug
+from openram.verify.run_script import *
+from openram import OPTS
 
 # Keep track of statistics
 num_drc_runs = 0
@@ -39,7 +38,7 @@ num_pex_runs = 0
 
 
 def write_drc_script(cell_name, gds_name, extract, final_verification, output_path):
-    from tech import drc
+    from openram.tech import drc
     drc_rules = drc["drc_rules"]
     drc_runset = output_path + cell_name + ".rsf"
     drc_log_file = "{0}{1}.log".format(OPTS.openram_temp, name)
@@ -108,7 +107,7 @@ def run_drc(name, gds_name, final_verification=False):
 
 def write_lvs_script(cell_name, gds_name, sp_name, final_verification, output_path):
 
-    from tech import drc
+    from openram.tech import drc
     lvs_rules = drc["lvs_rules"]
     lvs_runset = output_path + name + ".rsf"
     # The LVS compare rules must be defined in the tech file for Assura.

compiler/verify/calibre.py

@@ -16,11 +16,10 @@ Calibre means pointing the code to the proper DRC and LVS rule files.
 
 """
 
-
 import os
 import re
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 from .run_script import run_script
 
 # Keep track of statistics
@@ -36,7 +35,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification=False, out
     if not output_path:
         output_path = OPTS.openram_temp
 
-    from tech import drc
+    from openram.tech import drc
     drc_rules = drc["drc_rules"]
 
     drc_runset = {
@@ -77,7 +76,7 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out
     if not output_path:
         output_path = OPTS.openram_temp
 
-    from tech import drc
+    from openram.tech import drc
     lvs_rules = drc["lvs_rules"]
     lvs_runset = {
         'lvsRulesFile': lvs_rules,
@@ -151,7 +150,7 @@ def write_pex_script(cell_name, extract, output, final_verification=False, outpu
         run_drc(cell_name, gds_name, sp_name)
         run_lvs(cell_name, gds_name, sp_name)
 
-    from tech import drc
+    from openram.tech import drc
     pex_rules = drc["xrc_rules"]
     pex_runset = {
         'pexRulesFile': pex_rules,

compiler/verify/klayout.py

@@ -10,12 +10,11 @@ This is a DRC/LVS/PEX interface file for klayout.
 
 """
 
-
 import os
 import re
 import shutil
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 from .run_script import *
 
 # Keep track of statistics

compiler/verify/magic.py

@@ -19,12 +19,11 @@ We obtained this file from Qflow ( http://opencircuitdesign.com/qflow/index.html
 and include its appropriate license.
 """
 
-
 import os
 import re
 import shutil
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 from .run_script import *
 # Keep track of statistics
 num_drc_runs = 0
@@ -96,12 +95,12 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
     # Flatten the transistors
     # Bug in Netgen 1.5.194 when using this...
     try:
-        from tech import blackbox_cells
+        from openram.tech import blackbox_cells
     except ImportError:
         blackbox_cells = []
 
     try:
-        from tech import flatglob
+        from openram.tech import flatglob
     except ImportError:
         flatglob = []
         f.write("gds readonly true\n")

compiler/verify/none.py

@@ -7,9 +7,9 @@
 #
 """
 This is a DRC/LVS/PEX interface file the case with no DRC/LVS tools.
-
 """
-import debug
+
+from openram import debug
 
 # Only print the warning once.
 drc_warned = False

compiler/verify/run_script.py

@@ -10,10 +10,10 @@ Some baseline functions to run scripts.
 """
 
 import os
-import debug
 import subprocess
 import time
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 
 
 def run_script(cell_name, script="lvs"):