mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Use library imports globally
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@@ -6,22 +6,21 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys, os
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import unittest
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from testutils import *
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import sys, os
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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import openram
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from openram import debug
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from openram.sram_factory import factory
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from openram import OPTS
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class write_driver_pbitcell_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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globals.init_openram(config_file, is_unit_test=True)
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openram.init_openram(config_file, is_unit_test=True)
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# check write driver array for multi-port
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OPTS.bitcell = "pbitcell"
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@@ -38,12 +37,12 @@ class write_driver_pbitcell_test(openram_test):
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a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
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self.local_check(a)
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globals.end_openram()
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openram.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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