Use library imports globally

compiler/modules/and2_dec.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import design
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import vector
+from openram.base import design
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and2_dec(design):

compiler/modules/and3_dec.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and3_dec(design):

compiler/modules/and4_dec.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class and4_dec(design):

compiler/modules/bank.py

@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
 from math import log, ceil, floor
-from tech import drc
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class bank(design):

compiler/modules/bitcell_1port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/bitcell_2port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/bitcell_array.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.tech import drc, spice
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from globals import OPTS
-from sram_factory import factory
 
 
 class bitcell_array(bitcell_base_array):

compiler/modules/bitcell_base.py

@@ -5,12 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-import debug
-from base import design
-from globals import OPTS
-from base import logical_effort
-from tech import parameter, drc, layer, spice
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import parameter, drc, layer, spice
+from openram import OPTS
 
 
 class bitcell_base(design):
@@ -46,7 +45,7 @@ class bitcell_base(design):
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
+        from openram.tech import spice
         leakage = spice["bitcell_leakage"]
         # FIXME
         dynamic = 0

compiler/modules/bitcell_base_array.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class bitcell_base_array(design):

compiler/modules/col_cap_array.py

@@ -3,9 +3,9 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class col_cap_array(bitcell_base_array):

compiler/modules/col_cap_bitcell_1port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/col_cap_bitcell_2port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/column_decoder.py

@@ -3,15 +3,15 @@
 # Copyright (c) 2016-2022 Regents of the University of California
 # All rights reserved.
 #
-from tech import drc
-import debug
-from base import design
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import cell_properties
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import cell_properties
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class column_decoder(design):

compiler/modules/column_mux.py

@@ -5,14 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, layer
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pgate import *
-import debug
-from tech import drc, layer
-from base import vector
-from .pgate import *
-from sram_factory import factory
-from tech import cell_properties as cell_props
-from globals import OPTS
 
 
 class column_mux(pgate):

compiler/modules/column_mux_array.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from tech import layer, preferred_directions
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, preferred_directions
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class column_mux_array(design):

compiler/modules/control_logic.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from sram_factory import factory
 import math
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 from .control_logic_base import control_logic_base
 
 

compiler/modules/control_logic_base.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from sram_factory import factory
 import math
-from base import vector
-from globals import OPTS
-from base import logical_effort
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class control_logic_base(design):

compiler/modules/delay_chain.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class delay_chain(design):

compiler/modules/dff.py

@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import cell_properties as props
-from tech import spice
+from openram.base import design
+from openram.tech import cell_properties as props
+from openram.tech import spice
 
 
 class dff(design):

compiler/modules/dff_array.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_array(design):

compiler/modules/dff_buf.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import layer
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram import OPTS
 
 
 class dff_buf(design):

compiler/modules/dff_buf_array.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_buf_array(design):

compiler/modules/dff_inv.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_inv(design):

compiler/modules/dff_inv_array.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dff_inv_array(design):

compiler/modules/dummy_array.py

@@ -3,9 +3,9 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class dummy_array(bitcell_base_array):

compiler/modules/dummy_bitcell_1port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
@@ -21,4 +21,3 @@ class dummy_bitcell_1port(bitcell_base):
         super().__init__(name, prop=props.bitcell_1port)
         debug.info(2, "Create dummy bitcell")
 
-

compiler/modules/dummy_bitcell_2port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 
@@ -21,4 +21,3 @@ class dummy_bitcell_2port(bitcell_base):
         super().__init__(name, prop=props.bitcell_2port)
         debug.info(2, "Create dummy bitcell 2 port object")
 
-

compiler/modules/dummy_pbitcell.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class dummy_pbitcell(design):

compiler/modules/global_bitcell_array.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .bitcell_base_array import bitcell_base_array
-from globals import OPTS
-from sram_factory import factory
-from base import vector
-import debug
 from numpy import cumsum
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
+from .bitcell_base_array import bitcell_base_array
 
 
 class global_bitcell_array(bitcell_base_array):

compiler/modules/hierarchical_decoder.py

@@ -5,16 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import layer_indices
-from tech import layer_stacks
-from tech import layer_properties as layer_props
-from tech import drc
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_indices
+from openram.tech import layer_stacks
+from openram.tech import layer_properties as layer_props
+from openram.tech import drc
+from openram import OPTS
+
 
 class hierarchical_decoder(design):
     """

compiler/modules/hierarchical_predecode.py

@@ -5,17 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
 import math
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
-from tech import layer_indices
-from tech import layer_stacks
-from tech import preferred_directions
-from tech import drc
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram.tech import layer_indices
+from openram.tech import layer_stacks
+from openram.tech import preferred_directions
+from openram.tech import drc
+from openram import OPTS
 
 
 class hierarchical_predecode(design):

compiler/modules/hierarchical_predecode2x4.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode2x4(hierarchical_predecode):

compiler/modules/hierarchical_predecode3x8.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode3x8(hierarchical_predecode):

compiler/modules/hierarchical_predecode4x16.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import OPTS
 from .hierarchical_predecode import hierarchical_predecode
-from globals import OPTS
 
 
 class hierarchical_predecode4x16(hierarchical_predecode):

compiler/modules/internal_base.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram.base import design
 
-from base import design
 
 class internal_base(design):
 

compiler/modules/inv_dec.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import logical_effort
-from tech import cell_properties as props
-from tech import spice, parameter
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import spice, parameter
 
 
 class inv_dec(design):

compiler/modules/local_bitcell_array.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from globals import OPTS
-from sram_factory import factory
-from base import vector
-import debug
-from tech import layer_properties as layer_props
 
 
 class local_bitcell_array(bitcell_base_array):

compiler/modules/multibank.py

@@ -6,14 +6,15 @@
 # All rights reserved.
 #
 import sys
-from tech import drc, parameter
-import debug
-from base import design
 import math
-from math import log,sqrt,ceil
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from math import log, sqrt, ceil
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter
+from openram import OPTS
+
 
 class multibank(design):
     """

compiler/modules/nand2_dec.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand2_dec(design):

compiler/modules/nand3_dec.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand3_dec(design):

compiler/modules/nand4_dec.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from tech import spice, parameter, drc
-from tech import cell_properties as props
-from base import logical_effort
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import spice, parameter, drc
+from openram.tech import cell_properties as props
 
 
 class nand4_dec(design):

compiler/modules/orig_bitcell_array.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from globals import OPTS
-from sram_factory import factory
 
 
 class bitcell_array(bitcell_base_array):

compiler/modules/pand2.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand2(pgate):

compiler/modules/pand3.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand3(pgate):

compiler/modules/pand4.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pand4(pgate):

compiler/modules/pbitcell.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import logical_effort
-from base import vector
-from tech import drc, parameter, layer
-from tech import cell_properties as props
-from globals import OPTS
+from openram import debug
+from openram.base import logical_effort
+from openram.base import vector
+from openram.tech import drc, parameter, layer
+from openram.tech import cell_properties as props
+from openram import OPTS
 from .ptx import ptx
 from .bitcell_base import bitcell_base
 

compiler/modules/pbuf.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pbuf(pgate):

compiler/modules/pbuf_dec.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from sram_factory import factory
 
 
 class pbuf_dec(pgate):

compiler/modules/pdriver.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
 from .pgate import *
-from base import vector
-from sram_factory import factory
 
 
 class pdriver(pgate):

compiler/modules/pgate.py

@@ -5,17 +5,17 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import vector
-import debug
 import math
 from bisect import bisect_left
-from tech import layer, drc
-from globals import OPTS
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.tech import layer, drc
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 
 if cell_props.ptx.bin_spice_models:
-    from tech import nmos_bins, pmos_bins
+    from openram.tech import nmos_bins, pmos_bins
 
 
 class pgate(design):

compiler/modules/pinv.py

@@ -5,18 +5,18 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from .pgate import *
-from base import vector
-from base import logical_effort
-from base.utils import round_to_grid
-from base.errors import drc_error
 import operator
-from tech import drc, parameter, spice
 from math import ceil
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.base.utils import round_to_grid
+from openram.base.errors import drc_error
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
+from .pgate import *
 
 
 class pinv(pgate):

compiler/modules/pinv_dec.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, layer
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pinv import pinv
-from tech import drc, parameter, layer
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pinv_dec(pinv):

compiler/modules/pinvbuf.py

@@ -5,11 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
 from .pgate import *
-from base import vector
-from sram_factory import factory
-from tech import layer
+
 
 class pinvbuf(pgate):
     """

compiler/modules/pnand2.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand2(pgate):

compiler/modules/pnand3.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand3(pgate):

compiler/modules/pnand4.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.base import logical_effort
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from base import logical_effort
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnand4(pgate):

compiler/modules/pnor2.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
+from openram.tech import cell_properties as cell_props
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class pnor2(pgate):

compiler/modules/port_address.py

@@ -4,13 +4,13 @@
 # All rights reserved.
 #
 from math import log, ceil
-import debug
-from base import design
-from sram_factory import factory
-from base import vector
-from tech import layer, drc
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, drc
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class port_address(design):

compiler/modules/port_data.py

@@ -3,16 +3,16 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
-from tech import drc
-import debug
-from base import design
 import math
-from sram_factory import factory
 from collections import namedtuple
-from base import vector
-from globals import OPTS
-from tech import cell_properties
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram.tech import cell_properties
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class port_data(design):

compiler/modules/precharge.py

@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import parameter, drc
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 from .pgate import *
-from tech import parameter, drc
-from base import vector
-from globals import OPTS
-from sram_factory import factory
-from tech import cell_properties as cell_props
 
 
 class precharge(design):

compiler/modules/precharge_array.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class precharge_array(design):

compiler/modules/ptristate_inv.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, parameter, spice
 from .pgate import *
-import debug
-from tech import drc, parameter, spice
-from base import vector
-from sram_factory import factory
 
 
 class ptristate_inv(pgate):

compiler/modules/ptx.py

@@ -5,14 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import logical_effort
-from base import vector
-from tech import layer, drc, spice
-from sram_factory import factory
-from globals import OPTS
-from tech import cell_properties as cell_props
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer, drc, spice
+from openram.tech import cell_properties as cell_props
+from openram import OPTS
 
 
 class ptx(design):

compiler/modules/pwrite_driver.py

@@ -5,12 +5,12 @@
 #(acting for and on behalf of Oklahoma State University)
 #All rights reserved.
 #
-from base import design
-from tech import parameter
-import debug
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import parameter
+from openram import OPTS
 
 
 class pwrite_driver(design):

compiler/modules/replica_bitcell_1port.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import parameter, drc
 from .bitcell_base import bitcell_base
-from tech import cell_properties as props
-from tech import parameter, drc
-from base import logical_effort
 
 
 class replica_bitcell_1port(bitcell_base):
@@ -39,7 +39,7 @@ class replica_bitcell_1port(bitcell_base):
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
-        from tech import spice
+        from openram.tech import spice
         leakage = spice["bitcell_leakage"]
         dynamic = 0 # FIXME
         total_power = self.return_power(dynamic, leakage)

compiler/modules/replica_bitcell_2port.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import logical_effort
+from openram.tech import cell_properties as props
+from openram.tech import parameter, drc
 from .bitcell_base import bitcell_base
-from tech import cell_properties as props
-from tech import parameter, drc
-from base import logical_effort
 
 
 class replica_bitcell_2port(bitcell_base):

compiler/modules/replica_bitcell_array.py

@@ -3,15 +3,14 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
-
-import debug
-from base import vector
-from base import contact
+from openram import debug
+from openram.base import vector
+from openram.base import contact
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram.tech import cell_properties as props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from tech import cell_properties as props
-from globals import OPTS
-from sram_factory import factory
 
 
 class replica_bitcell_array(bitcell_base_array):

compiler/modules/replica_column.py

@@ -3,12 +3,12 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-from tech import layer_properties as layer_props
 
 
 class replica_column(bitcell_base_array):

compiler/modules/replica_pbitcell.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class replica_pbitcell(design):

compiler/modules/row_cap_array.py

@@ -3,9 +3,9 @@
 # Copyright (c) 2016-2021 Regents of the University of California
 # All rights reserved.
 #
+from openram.sram_factory import factory
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from sram_factory import factory
-from globals import OPTS
 
 
 class row_cap_array(bitcell_base_array):

compiler/modules/row_cap_bitcell_1port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/row_cap_bitcell_2port.py

@@ -5,8 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import cell_properties as props
+from openram import debug
+from openram.tech import cell_properties as props
 from .bitcell_base import bitcell_base
 
 

compiler/modules/sense_amp.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
-from tech import parameter, drc, spice
-from tech import cell_properties as props
-from base import logical_effort
+from openram import debug
+from openram.base import design
+from openram.base import logical_effort
+from openram.tech import parameter, drc, spice
+from openram.tech import cell_properties as props
 
 
 class sense_amp(design):
@@ -43,7 +43,7 @@ class sense_amp(design):
         # FIXME: This input load will be applied to both the s_en timing and bitline timing.
 
         # Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
-        from tech import spice
+        from openram.tech import spice
         # Default is 8x. Per Samira and Hodges-Jackson book:
         # "Column-mux transistors driven by the decoder must be sized for optimal speed"
         bitline_pmos_size = 8 # FIXME: This should be set somewhere and referenced. Probably in tech file.

compiler/modules/sense_amp_array.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-from base import vector
-from sram_factory import factory
-from tech import cell_properties
-import debug
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import cell_properties
+from openram import OPTS
 
 
 class sense_amp_array(design):

compiler/modules/sram.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import datetime
 import os
-import debug
-from characterizer import functional
-from globals import OPTS, print_time
 import shutil
+import datetime
+from openram import debug
+from openram.characterizer import functional
+from openram import OPTS, print_time
 
 
 class sram():
@@ -26,7 +26,7 @@ class sram():
 
         # reset the static duplicate name checker for unit tests
         # in case we create more than one SRAM
-        from base import design
+        from openram.base import design
         design.name_map=[]
 
         debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
@@ -80,7 +80,7 @@ class sram():
 
         # Import this at the last minute so that the proper tech file
         # is loaded and the right tools are selected
-        import verify
+        from openram import verify
 
         # Save the spice file
         start_time = datetime.datetime.now()
@@ -144,7 +144,7 @@ class sram():
 
         # Characterize the design
         start_time = datetime.datetime.now()
-        from characterizer import lib
+        from openram.characterizer import lib
         debug.print_raw("LIB: Characterizing... ")
         lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
         print_time("Characterization", datetime.datetime.now(), start_time)
@@ -158,7 +158,7 @@ class sram():
 
         # Write the datasheet
         start_time = datetime.datetime.now()
-        from datasheet import datasheet_gen
+        from openram.datasheet import datasheet_gen
         dname = OPTS.output_path + self.s.name + ".html"
         debug.print_raw("Datasheet: Writing to {0}".format(dname))
         datasheet_gen.datasheet_write(dname)

compiler/modules/sram_1bank.py

@@ -5,19 +5,19 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import vector
-from base import channel_route
-from router import router_tech
-from globals import OPTS, print_time
 import datetime
-import debug
 from math import ceil
-from importlib import reload
-from base import design
-from base import verilog
-from base import lef
-from sram_factory import factory
-from tech import spice
+from importlib import import_module, reload
+from openram import debug
+from openram.base import vector
+from openram.base import channel_route
+from openram.base import design
+from openram.base import verilog
+from openram.base import lef
+from openram.router import router_tech
+from openram.sram_factory import factory
+from openram.tech import spice
+from openram import OPTS, print_time
 
 
 class sram_1bank(design, verilog, lef):
@@ -43,7 +43,7 @@ class sram_1bank(design, verilog, lef):
             self.num_spare_cols = 0
 
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             self.supply_stack = power_grid
         except ImportError:
             # if no power_grid is specified by tech we use sensible defaults
@@ -254,9 +254,9 @@ class sram_1bank(design, verilog, lef):
             # Do not route the power supply (leave as must-connect pins)
             return
         elif OPTS.route_supplies == "grid":
-            from router import supply_grid_router as router
+            from openram.router import supply_grid_router as router
         else:
-            from router import supply_tree_router as router
+            from openram.router import supply_tree_router as router
         rtr=router(layers=self.supply_stack,
                    design=self,
                    bbox=bbox,
@@ -367,7 +367,7 @@ class sram_1bank(design, verilog, lef):
                     for bit in range(self.num_spare_cols):
                         pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
 
-        from router import signal_escape_router as router
+        from openram.router import signal_escape_router as router
         rtr=router(layers=self.m3_stack,
                    design=self,
                    bbox=bbox)
@@ -482,7 +482,7 @@ class sram_1bank(design, verilog, lef):
 
         self.bank_count = 0
 
-        c = reload(__import__('modules.' + OPTS.control_logic))
+        c = reload(import_module("." + OPTS.control_logic, "openram.modules"))
         self.mod_control_logic = getattr(c, OPTS.control_logic)
 
         # Create the control logic module for each port type

compiler/modules/sram_config.py

@@ -5,10 +5,10 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
 from math import log, sqrt, ceil
-from globals import OPTS
-from sram_factory import factory
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class sram_config:
@@ -28,12 +28,12 @@ class sram_config:
         self.num_spare_cols = num_spare_cols
 
         try:
-            from tech import array_row_multiple
+            from openram.tech import array_row_multiple
             self.array_row_multiple = array_row_multiple
         except ImportError:
             self.array_row_multiple = 1
         try:
-            from tech import array_col_multiple
+            from openram.tech import array_col_multiple
             self.array_col_multiple = array_col_multiple
         except ImportError:
             self.array_col_multiple = 1

compiler/modules/sram_multibank.py

@@ -1,8 +1,8 @@
-from .template import template
-from globals import OPTS
 import os
-from math import ceil, log
 import re
+from math import ceil, log
+from openram import OPTS
+from .template import template
 
 
 class sram_multibank:

compiler/modules/tri_gate.py

@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import spice
+from openram import debug
+from openram.base import design
+from openram.tech import spice
 
 
 class tri_gate(design):

compiler/modules/tri_gate_array.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import drc
-from base import design
-from base import vector
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram import OPTS
 
 class tri_gate_array(design):
     """

compiler/modules/wordline_buffer_array.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import layer
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_buffer_array(design):

compiler/modules/wordline_driver.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import design
-from sram_factory import factory
-from globals import OPTS
-from tech import layer
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import vector
+from openram.base import design
+from openram.sram_factory import factory
+from openram.tech import layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_driver(design):

compiler/modules/wordline_driver_array.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import drc, layer
-from base import vector
-from sram_factory import factory
-from globals import OPTS
-from tech import layer_properties as layer_props
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc, layer
+from openram.tech import layer_properties as layer_props
+from openram import OPTS
 
 
 class wordline_driver_array(design):

compiler/modules/write_driver.py

@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import design
-from tech import cell_properties as props
+from openram import debug
+from openram.base import design
+from openram.tech import cell_properties as props
 
 
 class write_driver(design):

compiler/modules/write_driver_array.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
 import math
-from tech import drc
-from sram_factory import factory
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram.tech import drc
+from openram import OPTS
 
 
 class write_driver_array(design):

compiler/modules/write_mask_and_array.py

@@ -5,12 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from base import design
-import debug
 import math
-from sram_factory import factory
-from base import vector
-from globals import OPTS
+from openram import debug
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class write_mask_and_array(design):