Use library imports globally

compiler/base/channel_route.py

@@ -6,8 +6,8 @@
 # All rights reserved.
 #
 import collections
-import debug
-from tech import drc
+from openram import debug
+from openram.tech import drc
 from .vector import vector
 from .design import design
 
@@ -405,4 +405,3 @@ class channel_route(design):
                                       to_layer=self.horizontal_layer,
                                       offset=pin_pos)
 
-

compiler/base/contact.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.tech import drc, layer, preferred_directions
+from openram.tech import layer as tech_layers
 from .hierarchy_design import hierarchy_design
 from .vector import vector
-from tech import drc, layer, preferred_directions
-from tech import layer as tech_layers
 
 
 class contact(hierarchy_design):

compiler/base/delay_data.py

@@ -6,7 +6,6 @@
 # All rights reserved.
 #
 
-
 class delay_data():
     """
     This is the delay class to represent the delay information
@@ -38,7 +37,3 @@ class delay_data():
         assert isinstance(other, delay_data)
         return delay_data(other.delay + self.delay,
                           self.slew)
-
-
-
-

compiler/base/design.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import GDS, layer
-from tech import preferred_directions
-from tech import cell_properties as props
-from globals import OPTS
+from openram import debug
+from openram.tech import GDS, layer
+from openram.tech import preferred_directions
+from openram.tech import cell_properties as props
+from openram import OPTS
 from . import utils
 from .hierarchy_design import hierarchy_design
 
@@ -67,7 +67,7 @@ class design(hierarchy_design):
         self.setup_multiport_constants()
 
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             self.supply_stack = power_grid
         except ImportError:
             # if no power_grid is specified by tech we use sensible defaults

compiler/base/geometry.py

@@ -8,14 +8,14 @@
 """
 This provides a set of useful generic types for the gdsMill interface.
 """
-import debug
-from .vector import vector
-import tech
 import math
 import copy
 import numpy as np
-from globals import OPTS
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .utils import round_to_grid
+from .vector import vector
 
 
 class geometry:

compiler/base/hierarchy_design.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import os
+from openram import debug
+from openram import OPTS
 from .hierarchy_layout import layout
 from .hierarchy_spice import spice
-import debug
-import os
-from globals import OPTS
 
 
 class hierarchy_design(spice, layout):
@@ -49,7 +49,7 @@ class hierarchy_design(spice, layout):
 
     def DRC_LVS(self, final_verification=False, force_check=False):
         """Checks both DRC and LVS for a module"""
-        import verify
+        from openram import verify
 
         # No layout to check
         if OPTS.netlist_only:
@@ -82,7 +82,7 @@ class hierarchy_design(spice, layout):
 
     def DRC(self, final_verification=False):
         """Checks DRC for a module"""
-        import verify
+        from openram import verify
 
         # Unit tests will check themselves.
         # Do not run if disabled in options.
@@ -102,7 +102,7 @@ class hierarchy_design(spice, layout):
 
     def LVS(self, final_verification=False):
         """Checks LVS for a module"""
-        import verify
+        from openram import verify
 
         # Unit tests will check themselves.
         # Do not run if disabled in options.

compiler/base/hierarchy_layout.py

@@ -5,28 +5,28 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os
 import sys
+import os
 import re
 from math import sqrt
-import debug
-from gdsMill import gdsMill
-import tech
-from tech import drc, GDS
-from tech import layer as tech_layer
-from tech import layer_indices as tech_layer_indices
-from tech import preferred_directions
-from tech import layer_stacks as tech_layer_stacks
-from tech import active_stack as tech_active_stack
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.gdsMill import gdsMill
+from openram import tech
+from openram.tech import drc, GDS
+from openram.tech import layer as tech_layer
+from openram.tech import layer_indices as tech_layer_indices
+from openram.tech import preferred_directions
+from openram.tech import layer_stacks as tech_layer_stacks
+from openram.tech import active_stack as tech_active_stack
+from openram.sram_factory import factory
+from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
 from .utils import round_to_grid
 from . import geometry
 
 try:
-    from tech import special_purposes
+    from openram.tech import special_purposes
 except ImportError:
     special_purposes = {}
 
@@ -171,7 +171,7 @@ class layout():
         in many places in the compiler.
         """
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             layout.pwr_grid_layers = [power_grid[0], power_grid[2]]
         except ImportError:
             layout.pwr_grid_layers = ["m3", "m4"]
@@ -1253,7 +1253,7 @@ class layout():
 
     def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None):
         """ Add a three layer via structure. """
-        from sram_factory import factory
+        from openram.sram_factory import factory
         via = factory.create(module_type="contact",
                              layer_stack=layers,
                              dimensions=size,
@@ -1272,7 +1272,7 @@ class layout():
         Add a three layer via structure by the center coordinate
         accounting for mirroring and rotation.
         """
-        from sram_factory import factory
+        from openram.sram_factory import factory
         via = factory.create(module_type="contact",
                              layer_stack=layers,
                              dimensions=size,
@@ -1379,10 +1379,10 @@ class layout():
 
     def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
         """Adds a ptx module to the design."""
-        import ptx
-        mos = ptx.ptx(width=width,
-                      mults=mults,
-                      tx_type=tx_type)
+        from openram.modules import ptx
+        mos = ptx(width=width,
+                  mults=mults,
+                  tx_type=tx_type)
         inst = self.add_inst(name=mos.name,
                              mod=mos,
                              offset=offset,
@@ -2176,7 +2176,7 @@ class layout():
 
         # Find the number of vias for this pitch
         supply_vias = 1
-        from sram_factory import factory
+        from openram.sram_factory import factory
         while True:
             c = factory.create(module_type="contact",
                                layer_stack=self.m1_stack,
@@ -2289,7 +2289,7 @@ class layout():
 
         # Find the number of vias for this pitch
         self.supply_vias = 1
-        from sram_factory import factory
+        from openram.sram_factory import factory
         while True:
             c = factory.create(module_type="contact",
                                layer_stack=self.m1_stack,

compiler/base/hierarchy_spice.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-import re
 import os
+import re
 import math
-import tech
-from globals import OPTS
 from pprint import pformat
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .delay_data import delay_data
 from .wire_spice_model import wire_spice_model
 from .power_data import power_data
@@ -37,7 +37,7 @@ class spice():
         # If we have a separate lvs directory, then all the lvs files
         # should be in there (all or nothing!)
         try:
-            from tech import lvs_name
+            from openram.tech import lvs_name
             lvs_dir = OPTS.openram_tech + lvs_name + "_lvs_lib/"
         except ImportError:
             lvs_dir = OPTS.openram_tech + "lvs_lib/"

compiler/base/lef.py

@@ -5,13 +5,13 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import pin_layout
-from tech import layer_names
 import os
 import shutil
-from globals import OPTS
+from openram import debug
+from openram.base import vector
+from openram.base import pin_layout
+from openram.tech import layer_names
+from openram import OPTS
 
 
 class lef:
@@ -64,7 +64,7 @@ class lef:
         f.write('puts "Finished writing LEF cell {}"\n'.format(self.name))
         f.close()
         os.system("chmod u+x {}".format(run_file))
-        from run_script import run_script
+        from openram.verify.run_script import run_script
         (outfile, errfile, resultsfile) = run_script(self.name, "lef")
 
     def lef_write(self, lef_name):

compiler/base/logical_effort.py

@@ -5,8 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import parameter
+from openram import debug
+from openram.tech import parameter
+
 
 class logical_effort():
     """

compiler/base/pin_layout.py

@@ -5,11 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import GDS, drc
-from .vector import vector
-from tech import layer, layer_indices
 import math
+from openram import debug
+from openram.tech import GDS, drc
+from openram.tech import layer, layer_indices
+from .vector import vector
 
 
 class pin_layout:
@@ -48,8 +48,8 @@ class pin_layout:
 
             else:
                 try:
-                    from tech import layer_override
-                    from tech import layer_override_name
+                    from openram.tech import layer_override
+                    from openram.tech import layer_override_name
                     if layer_override[name]:
                        self.lpp = layer_override[name]
                        self.layer = "pwellp"
@@ -406,15 +406,15 @@ class pin_layout:
         # Try to use a global pin purpose if it exists,
         # otherwise, use the regular purpose
         try:
-            from tech import pin_purpose as global_pin_purpose
+            from openram.tech import pin_purpose as global_pin_purpose
             pin_purpose = global_pin_purpose
         except ImportError:
             pass
 
         try:
-            from tech import label_purpose
+            from openram.tech import label_purpose
             try:
-                from tech import layer_override_purpose
+                from openram.tech import layer_override_purpose
                 if pin_layer_num in layer_override_purpose:
                     layer_num = layer_override_purpose[pin_layer_num][0]
                     label_purpose = layer_override_purpose[pin_layer_num][1]

compiler/base/route.py

@@ -5,13 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from itertools import tee
+from openram import debug
+from openram.sram_factory import factory
+from openram.tech import drc
 from .design import design
 from .vector import vector
 from .vector3d import vector3d
-from tech import drc
-from itertools import tee
-from sram_factory import factory
+
 
 class route(design):
     """

compiler/base/timing_graph.py

@@ -1,6 +1,6 @@
 import copy
 from collections import defaultdict
-import debug
+from openram import debug
 
 
 class timing_graph():

compiler/base/utils.py

@@ -4,21 +4,19 @@
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
-
+#
 import os
 import math
-
-from gdsMill import gdsMill
-import tech
-import globals
-import debug
+from openram import debug
+from openram import tech
+from openram.gdsMill import gdsMill
+from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
 try:
-    from tech import special_purposes
+    from openram.tech import special_purposes
 except ImportError:
     special_purposes = {}
-OPTS = globals.OPTS
 
 
 def ceil(decimal):
@@ -159,7 +157,7 @@ def get_gds_pins(pin_names, name, gds_filename, units):
                     # may have must-connect pins
                     if isinstance(lpp[1], list):
                         try:
-                            from tech import layer_override
+                            from openram.tech import layer_override
                             if layer_override[pin_name]:
                                 lpp = layer_override[pin_name.textString]
                         except:

compiler/base/vector.py

@@ -5,9 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
 import math
-import tech
+from openram import tech
 
 
 class vector():

compiler/base/verilog.py

@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 import math
-from tech import spice
+from openram.tech import spice
 
 
 class verilog:

compiler/base/wire.py

@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from tech import drc
+from openram.tech import drc
+from openram.sram_factory import factory
 from .wire_path import wire_path
-from sram_factory import factory
 
 
 class wire(wire_path):
@@ -71,7 +71,7 @@ class wire(wire_path):
 
         # This is here for the unit tests which may not have
         # initialized the static parts of the layout class yet.
-        from base import layout
+        from openram.base import layout
         layout("fake", "fake")
 
         (layer1, via, layer2) = layer_stack

compiler/base/wire_path.py

@@ -5,11 +5,12 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .vector import vector
-from .utils import snap_to_grid
+from openram.tech import drc
+from openram.tech import layer as techlayer
 from .design import design
-from tech import drc
-from tech import layer as techlayer
+from .utils import snap_to_grid
+from .vector import vector
+
 
 def create_rectilinear_route(my_list):
     """ Add intermediate nodes if it isn't rectilinear. Also skip

compiler/base/wire_spice_model.py

@@ -16,14 +16,14 @@ class wire_spice_model():
         self.wire_r = self.cal_wire_r(wire_length, wire_width) # r in each segment
 
     def cal_wire_c(self, wire_length, wire_width):
-        from tech import spice
+        from openram.tech import spice
         # Convert the F/um^2 to fF/um^2 then multiple by width and length
         total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width
         wire_c = total_c / self.lump_num
         return wire_c
 
     def cal_wire_r(self, wire_length, wire_width):
-        from tech import spice
+        from openram.tech import spice
         total_r = spice["wire_unit_r"] * wire_length / wire_width
         wire_r = total_r / self.lump_num
         return wire_r