Remove split_wl

compiler/base/custom_cell_properties.py

@@ -32,9 +32,8 @@ class _mirror_axis:
         self.y = y
 
 class _bitcell:
-    def __init__(self, mirror, split_wl, cell_s8_6t, cell_6t, cell_1rw1r, cell_1w1r):
+    def __init__(self, mirror, cell_s8_6t, cell_6t, cell_1rw1r, cell_1w1r):
         self.mirror = mirror
-        self.split_wl = split_wl
         self._s8_6t = cell_s8_6t
         self._6t = cell_6t
         self._1rw1r = cell_1rw1r
@@ -43,8 +42,8 @@ class _bitcell:
     def _default():
         axis = _mirror_axis(True, False)
 
-        cell_s8_6t = _cell({'bl' : 'bl0',
+        cell_s8_6t = _cell({'bl' : 'bl',
-                            'br' : 'bl1',
+                            'br' : 'br',
                             'wl': 'wl'})
 
         cell_6t = _cell({'bl' : 'bl',
@@ -69,7 +68,6 @@ class _bitcell:
                         cell_6t=cell_6t,
                         cell_1rw1r=cell_1rw1r,
                         cell_1w1r=cell_1w1r,
-                        split_wl = [],
                         mirror=axis)
 
     @property

compiler/bitcells/bitcell.py

@@ -22,11 +22,6 @@ class bitcell(bitcell_base.bitcell_base):
 
     # If we have a split WL bitcell, if not be backwards
     # compatible in the tech file
-
-    if props.compare_ports(props.bitcell.split_wl):
-        pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
-        type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
-    else:
     pin_names = [props.bitcell.cell_6t.pin.bl,
                  props.bitcell.cell_6t.pin.br,
                  props.bitcell.cell_6t.pin.wl,
@@ -55,9 +50,6 @@ class bitcell(bitcell_base.bitcell_base):
               
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """
-        if props.compare_ports(props.bitcell.split_wl):
-            row_pins = ["wl0", "wl1"]
-        else:
         row_pins = [props.bitcell.cell_6t.pin.wl]
         return row_pins
 
@@ -87,9 +79,6 @@ class bitcell(bitcell_base.bitcell_base):
 
     def get_wl_name(self, port=0):
         """Get wl name"""
-        if props.compare_ports(props.bitcell.split_wl):
-            return "wl{}".format(port)
-        else:
         debug.check(port == 0, "One port for bitcell only.")
         return props.bitcell.cell_6t.pin.wl
 

compiler/bitcells/replica_bitcell.py

@@ -20,16 +20,11 @@ class replica_bitcell(design.design):
     is a hand-made cell, so the layout and netlist should be available in
     the technology library. """
 
-    if cell_properties.compare_ports(cell_properties.bitcell.split_wl):
-        pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
-        type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] 
-    else:
     pin_names = [props.bitcell.cell_6t.pin.bl,
                  props.bitcell.cell_6t.pin.br,
                  props.bitcell.cell_6t.pin.wl,
                  props.bitcell.cell_6t.pin.vdd,
                  props.bitcell.cell_6t.pin.gnd]
-
     type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
     
     if not OPTS.netlist_only:

compiler/custom/s8_bitcell.py

@@ -20,13 +20,6 @@ class s8_bitcell(bitcell_base.bitcell_base):
     library.
     """
 
-    # If we have a split WL bitcell, if not be backwards
-    # compatible in the tech file
-
-    if props.compare_ports(props.bitcell.split_wl):
-        pin_names = ["bl0", "bl1", "wl0", "wl1", "vpwr", "vgnd"]
-        type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
-    else:
     pin_names = [props.bitcell.cell_s8_6t.pin.bl,
                  props.bitcell.cell_s8_6t.pin.br,
                  props.bitcell.cell_s8_6t.pin.wl,
@@ -57,9 +50,6 @@ class s8_bitcell(bitcell_base.bitcell_base):
 
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """
-        if props.compare_ports(props.bitcell.split_wl):
-            row_pins = ["wl0", "wl1"]
-        else:
         row_pins = [props.bitcell.cell_s8_6t.pin.wl]
         return row_pins
 
@@ -89,9 +79,6 @@ class s8_bitcell(bitcell_base.bitcell_base):
 
     def get_wl_name(self, port=0):
         """Get wl name"""
-        if props.compare_ports(props.bitcell.split_wl):
-            return "wl{}".format(port)
-        else:
         debug.check(port == 0, "One port for bitcell only.")
         return props.bitcell.cell_s8_6t.pin.wl
 

compiler/modules/bitcell_base_array.py

@@ -59,11 +59,7 @@ class bitcell_base_array(design.design):
     def create_all_wordline_names(self, remove_num_wordlines=0):
         for row in range(self.row_size - remove_num_wordlines):
             for port in self.all_ports:
-                if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
                 self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
-                else:
-                    self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
-                    self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
 
         self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]