From fcacd46866ed2ed9350f9306637878a9a227f236 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 21 Feb 2018 15:45:49 -0800 Subject: [PATCH] UPdate tests with new delay and slew names and leakage power. --- compiler/characterizer/delay.py | 19 +++++++------ compiler/characterizer/lib.py | 12 +++----- compiler/tests/21_hspice_delay_test.py | 32 ++++++++++----------- compiler/tests/21_ngspice_delay_test.py | 38 +++++++++++++------------ 4 files changed, 51 insertions(+), 50 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index d1c8bea2..985db403 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -280,7 +280,7 @@ class delay(): # add measure statements for power t_initial = period t_final = 2*period - self.stim.gen_meas_power(meas_name="LEAKAGE_POWER", + self.stim.gen_meas_power(meas_name="leakage_power", t_initial=t_initial, t_final=t_final) @@ -563,26 +563,29 @@ class delay(): for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power", "read1_power", "write0_power", "write1_power", "leakage_power"]: char_data[m]=[] - full_array_leakage = [] - trim_array_leakage = [] + full_array_leakage = {} + trim_array_leakage = {} for load in loads: # 2a) Find the leakage power of the trimmmed and UNtrimmed arrays. (full_leak, trim_leak)=self.run_power_simulation(feasible_period, load) - full_array_leakage.append(full_leak) - trim_array_leakage.append(trim_leak) - for slew in slews: + full_array_leakage[load]=full_leak + trim_array_leakage[load]=trim_leak + char_data["leakage_power"].append(full_array_leakage[load]) + + for slew in slews: + for load in loads: # 2c) Find the delay, dynamic power, and leakage power of the trimmed array. (success, delay_results) = self.run_delay_simulation(feasible_period, load, slew) debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(slew,load)) for k,v in delay_results.items(): if "power" in k: # Subtract partial array leakage and add full array leakage for the power measures - char_data[k].append(v - trim_array_leakage[-1] + full_array_leakage[-1]) - char_data["leakage_power"].append(full_array_leakage[-1]) + char_data[k].append(v - trim_array_leakage[load] + full_array_leakage[load]) else: char_data[k].append(v) + # 3) Finds the minimum period without degrading the delays by X% min_period = self.find_min_period(feasible_period, max(loads), max(slews), feasible_delay_lh, feasible_delay_hl) debug.check(type(min_period)==float,"Couldn't find minimum period.") diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index fe374e8c..99ace380 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -323,20 +323,16 @@ class lib: self.lib.write(" related_pin : \"clk\"; \n") self.lib.write(" timing_type : falling_edge; \n") self.lib.write(" cell_rise(CELL_TABLE) {\n") - rounded_values = map(ch.round_time,self.char_results["delayLH"]) - self.write_values(rounded_values,len(self.loads)," ") + self.write_values(self.char_results["delay_lh"],len(self.loads)," ") self.lib.write(" }\n") self.lib.write(" cell_fall(CELL_TABLE) {\n") - rounded_values = map(ch.round_time,self.char_results["delayHL"]) - self.write_values(rounded_values,len(self.loads)," ") + self.write_values(self.char_results["delay_hl"],len(self.loads)," ") self.lib.write(" }\n") self.lib.write(" rise_transition(CELL_TABLE) {\n") - rounded_values = map(ch.round_time,self.char_results["slewLH"]) - self.write_values(rounded_values,len(self.loads)," ") + self.write_values(self.char_results["slew_lh"],len(self.loads)," ") self.lib.write(" }\n") self.lib.write(" fall_transition(CELL_TABLE) {\n") - rounded_values = map(ch.round_time,self.char_results["slewHL"]) - self.write_values(rounded_values,len(self.loads)," ") + self.write_values(self.char_results["slew_hl"],len(self.loads)," ") self.lib.write(" }\n") self.lib.write(" }\n") self.lib.write(" }\n") diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index e863b4f6..adaa8e1f 100644 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -51,25 +51,25 @@ class timing_sram_test(openram_test): data = d.analyze(probe_address, probe_data,slews,loads) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.032946500000000004, - 'read0_power': 0.0337812, - 'write0_power': 0.026179099999999997, - 'delay1': [0.0573055], - 'delay0': [0.070554], + golden_data = {'read1_power': [0.032946500000000004], + 'read0_power': [0.0337812], + 'write0_power': [0.026179099999999997], + 'delay_lh': [0.0573055], + 'delay_hl': [0.070554], 'min_period': 0.205, - 'write1_power': 0.0361529, - 'slew0': [0.0285185], - 'slew1': [0.0190073]} + 'write1_power': [0.0361529], + 'slew_hl': [0.0285185], + 'slew_lh': [0.0190073]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 9.589, - 'read0_power': 9.7622, - 'write0_power': 6.928400000000001, - 'delay1': [0.6538954], - 'delay0': [0.9019090999999999], + golden_data = {'read1_power': [9.589], + 'read0_power': [9.7622], + 'write0_power': [6.928400000000001], + 'delay_lh': [0.6538954], + 'delay_hl': [0.9019090999999999], 'min_period': 2.344, - 'write1_power': 10.2578, - 'slew0': [0.8321625], - 'slew1': [0.5896232]} + 'write1_power': [10.2578], + 'slew_hl': [0.8321625], + 'slew_lh': [0.5896232]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index cf821cbb..6a44138b 100644 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -47,27 +47,29 @@ class timing_sram_test(openram_test): loads = [tech.spice["msflop_in_cap"]*4] slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data,slews,loads) - #print data + print data if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.03308298, - 'read0_power': 0.03866541, - 'write0_power': 0.02695139, - 'delay1': [0.05840294000000001], - 'delay0': [0.40787249999999997], - 'min_period': 0.781, - 'write1_power': 0.037257830000000006, - 'slew0': [0.035826199999999996], - 'slew1': [0.02059459]} + golden_data = {'leakage_power': [0.0007348262], + 'delay_lh': [0.05799613], + 'read0_power': [0.0384102], + 'read1_power': [0.03279848], + 'write1_power': [0.03693655], + 'write0_power': [0.02717752], + 'slew_hl': [0.03607912], + 'min_period': 0.742, + 'delay_hl': [0.3929995], + 'slew_lh': [0.02160862]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 11.416549999999999, - 'read0_power': 11.44908, - 'write0_power': 8.250219, - 'delay1': [0.8018421], - 'delay0': [1.085861], + golden_data = {'leakage_power': [0.00142014], + 'delay_lh': [0.8018421], + 'read0_power': [11.44908], + 'read1_power': [11.416549999999999], + 'write1_power': [11.718020000000001], + 'write0_power': [8.250219], + 'slew_hl': [0.8273725], 'min_period': 2.734, - 'write1_power': 11.718020000000001, - 'slew0': [0.8273725], - 'slew1': [0.5730144]} + 'delay_hl': [1.085861], + 'slew_lh': [0.5730144]} else: self.assertTrue(False) # other techs fail