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OpenRAM
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

This commit is contained in:
Michael Timothy Grimes 2018-09-18 18:56:15 -07:00
parent 43f5316eed a58b1906ad
commit fc5f163828
84 changed files with 18543 additions and 389 deletions
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4
.gitlab-ci.yml
View File

@ -1,6 +1,6 @@
freepdk45:
script: "/home/gitlab-runner/regress_freepdk45.sh"
scn3me_subm:
script: "/home/gitlab-runner/regress_scn3me_subm.sh"
scn4m_subm:
script: "/home/gitlab-runner/regress_scn4m_subm.sh"

8
compiler/characterizer/setup_hold.py
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@ -3,7 +3,7 @@ import tech
from .stimuli import *
import debug
from .charutils import *
import ms_flop
import dff
from globals import OPTS
@ -15,9 +15,9 @@ class setup_hold():
def __init__(self, corner):
# This must match the spice model order
self.pins = ["data", "dout", "dout_bar", "clk", "vdd", "gnd"]
self.model_name = "ms_flop"
self.model_location = OPTS.openram_tech + "sp_lib/ms_flop.sp"
self.pins = ["data", "dout", "clk", "vdd", "gnd"]
self.model_name = "dff"
self.model_location = OPTS.openram_tech + "sp_lib/dff.sp"
self.period = tech.spice["feasible_period"]
debug.info(2,"Feasible period from technology file: {0} ".format(self.period))

2
compiler/globals.py
View File

@ -59,7 +59,7 @@ def parse_args():
OPTS.tech_name = "scmos"
# Alias SCMOS to AMI 0.5um
if OPTS.tech_name == "scmos":
OPTS.tech_name = "scn3me_subm"
OPTS.tech_name = "scn4m_subm"
return (options, args)

2
compiler/modules/bank.py
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@ -205,7 +205,7 @@ class bank(design.design):
def add_modules(self):
""" Create all the modules using the class loader """
mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver",
mod_list = ["bitcell", "decoder", "wordline_driver",
"bitcell_array", "sense_amp_array", "precharge_array",
"column_mux_array", "write_driver_array",
"dff", "bank_select"]

2
compiler/modules/control_logic.py
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@ -282,7 +282,7 @@ class control_logic(design.design):
# Connect the clock rail to the other clock rail
in_pos = self.ctrl_dff_inst.get_pin("clk").uc()
mid_pos = in_pos + vector(0,self.m2_pitch)
mid_pos = in_pos + vector(0,2*self.m2_pitch)
rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y)
self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos])
self.add_via_center(layers=("metal1","via1","metal2"),

19
compiler/modules/dff.py
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@ -21,6 +21,25 @@ class dff(design.design):
self.height = dff.height
self.pin_map = dff.pin_map
def analytical_power(self, proc, vdd, temp, load):
"""Returns dynamic and leakage power. Results in nW"""
from tech import spice
c_eff = self.calculate_effective_capacitance(load)
f = spice["default_event_rate"]
power_dyn = c_eff*vdd*vdd*f
power_leak = spice["msflop_leakage"]
total_power = self.return_power(power_dyn, power_leak)
return total_power
def calculate_effective_capacitance(self, load):
"""Computes effective capacitance. Results in fF"""
from tech import spice, parameter
c_load = load
c_para = spice["flop_para_cap"]#ff
transition_prob = spice["flop_transition_prob"]
return transition_prob*(c_load + c_para)
def analytical_delay(self, slew, load = 0.0):
# dont know how to calculate this now, use constant in tech file
from tech import spice

6
compiler/modules/hierarchical_predecode.py
View File

@ -56,8 +56,8 @@ class hierarchical_predecode(design.design):
# x offset for input inverters
self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch
# x offset to NAND decoder includes the left rails, mid rails and inverters, plus an extra m2 pitch
self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 1) * self.m2_pitch
# x offset to NAND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches
self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch
# x offset to output inverters
self.x_off_inv_2 = self.x_off_nand + self.nand.width
@ -78,7 +78,7 @@ class hierarchical_predecode(design.design):
invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)]
non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)]
decode_names = invert_names + non_invert_names
offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, 2*self.m1_width)
offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width)
self.decode_rails = self.create_vertical_bus(layer="metal2",
pitch=self.m2_pitch,
offset=offset,

50
compiler/modules/ms_flop.py
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@ -1,50 +0,0 @@
import globals
import design
from math import log
import design
from tech import GDS,layer
import utils
class ms_flop(design.design):
"""
Memory address flip-flop
"""
pin_names = ["din", "dout", "dout_bar", "clk", "vdd", "gnd"]
(width,height) = utils.get_libcell_size("ms_flop", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "ms_flop", GDS["unit"], layer["boundary"])
def __init__(self, name="ms_flop"):
design.design.__init__(self, name)
self.width = ms_flop.width
self.height = ms_flop.height
self.pin_map = ms_flop.pin_map
def analytical_delay(self, slew, load = 0.0):
# dont know how to calculate this now, use constant in tech file
from tech import spice
result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
return result
def analytical_power(self, proc, vdd, temp, load):
"""Returns dynamic and leakage power. Results in nW"""
from tech import spice
c_eff = self.calculate_effective_capacitance(load)
f = spice["default_event_rate"]
power_dyn = c_eff*vdd*vdd*f
power_leak = spice["msflop_leakage"]
total_power = self.return_power(power_dyn, power_leak)
return total_power
def calculate_effective_capacitance(self, load):
"""Computes effective capacitance. Results in fF"""
from tech import spice, parameter
c_load = load
c_para = spice["flop_para_cap"]#ff
transition_prob = spice["flop_transition_prob"]
return transition_prob*(c_load + c_para)

136
compiler/modules/ms_flop_array.py
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@ -1,136 +0,0 @@
import debug
import design
from tech import drc
from math import log
from vector import vector
from globals import OPTS
class ms_flop_array(design.design):
"""
An Array of D-Flipflops used for to store Data_in & Data_out of
Write_driver & Sense_amp, address inputs of column_mux &
hierdecoder
"""
def __init__(self, columns, word_size, name=""):
self.columns = columns
self.word_size = word_size
if name=="":
name = "flop_array_c{0}_w{1}".format(columns,word_size)
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
self.words_per_row = int(self.columns / self.word_size)
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
def create_netlist(self):
self.add_modules()
self.add_pins()
self.create_ms_flop_array()
def create_layout(self):
self.width = self.columns * self.ms.width
self.height = self.ms.height
self.place_ms_flop_array()
self.add_layout_pins()
self.DRC_LVS()
def add_modules(self):
from importlib import reload
c = reload(__import__(OPTS.ms_flop))
self.mod_ms_flop = getattr(c, OPTS.ms_flop)
self.ms = self.mod_ms_flop("ms_flop")
self.add_mod(self.ms)
def add_pins(self):
for i in range(self.word_size):
self.add_pin("din[{0}]".format(i))
for i in range(self.word_size):
self.add_pin("dout[{0}]".format(i))
self.add_pin("dout_bar[{0}]".format(i))
self.add_pin("clk")
self.add_pin("vdd")
self.add_pin("gnd")
def create_ms_flop_array(self):
self.ms_inst={}
for i in range(0,self.columns,self.words_per_row):
name = "Xdff{0}".format(i)
index = int(i/self.words_per_row)
self.ms_inst[index]=self.add_inst(name=name,
mod=self.ms)
self.connect_inst(["din[{0}]".format(index),
"dout[{0}]".format(index),
"dout_bar[{0}]".format(index),
"clk",
"vdd", "gnd"])
def place_ms_flop_array(self):
for i in range(0,self.columns,self.words_per_row):
index = int(i/self.words_per_row)
if (i % 2 == 0 or self.words_per_row>1):
base = vector(i*self.ms.width,0)
mirror = "R0"
else:
base = vector((i+1)*self.ms.width,0)
mirror = "MY"
self.ms_inst[index].place(offset=base,
mirror=mirror)
def add_layout_pins(self):
for i in range(self.word_size):
# Route both supplies
for n in ["vdd", "gnd"]:
for supply_pin in self.ms_inst[i].get_pins(n):
pin_pos = supply_pin.center()
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=pin_pos)
self.add_layout_pin_rect_center(text=n,
layer="metal3",
offset=pin_pos)
din_pins = self.ms_inst[i].get_pins("din")
for din_pin in din_pins:
self.add_layout_pin(text="din[{}]".format(i),
layer=din_pin.layer,
offset=din_pin.ll(),
width=din_pin.width(),
height=din_pin.height())
dout_pin = self.ms_inst[i].get_pin("dout")
self.add_layout_pin(text="dout[{}]".format(i),
layer="metal2",
offset=dout_pin.ll(),
width=dout_pin.width(),
height=dout_pin.height())
doutbar_pin = self.ms_inst[i].get_pin("dout_bar")
self.add_layout_pin(text="dout_bar[{}]".format(i),
layer="metal2",
offset=doutbar_pin.ll(),
width=doutbar_pin.width(),
height=doutbar_pin.height())
# Continous clk rail along with label.
self.add_layout_pin(text="clk",
layer="metal1",
offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1),
width=self.width,
height=drc["minwidth_metal1"])
def analytical_delay(self, slew, load=0.0):
return self.ms.analytical_delay(slew=slew, load=load)

2
compiler/modules/multibank.py
View File

@ -23,7 +23,7 @@ class multibank(design.design):
def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""):
mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver",
mod_list = ["tri_gate", "bitcell", "decoder", "wordline_driver",
"bitcell_array", "sense_amp_array", "precharge_array",
"column_mux_array", "write_driver_array", "tri_gate_array",
"dff", "bank_select"]

3
compiler/options.py
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@ -69,8 +69,7 @@ class options(optparse.Values):
# These are the default modules that can be over-riden
decoder = "hierarchical_decoder"
ms_flop = "ms_flop"
ms_flop_array = "ms_flop_array"
dff_array = "dff_array"
dff = "dff"
control_logic = "control_logic"
bitcell_array = "bitcell_array"

4
compiler/sram_base.py
View File

@ -227,10 +227,6 @@ class sram_base(design):
c = reload(__import__(OPTS.control_logic))
self.mod_control_logic = getattr(c, OPTS.control_logic)
c = reload(__import__(OPTS.ms_flop))
self.mod_ms_flop = getattr(c, OPTS.ms_flop)
self.ms_flop = self.mod_ms_flop()
from control_logic import control_logic
# Create the control logic module

0
compiler/tests/04_precharge_test.py Normal file → Executable file
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0
compiler/tests/04_single_level_column_mux_test.py Normal file → Executable file
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0
compiler/tests/07_single_level_column_mux_array_test.py Normal file → Executable file
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0
compiler/tests/08_precharge_array_test.py Normal file → Executable file
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0
compiler/tests/08_wordline_driver_test.py Normal file → Executable file
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0
compiler/tests/09_sense_amp_array_test.py Normal file → Executable file
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0
compiler/tests/10_write_driver_array_test.py Normal file → Executable file
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35
compiler/tests/11_ms_flop_array_test.py
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@ -1,35 +0,0 @@
#!/usr/bin/env python3
"""
Run a regression test on a dff_array.
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class dff_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ms_flop_array
debug.info(2, "Testing ms_flop_array for columns=8, word_size=8")
a = ms_flop_array.ms_flop_array(columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing ms_flop_array for columns=16, word_size=8")
a = ms_flop_array.ms_flop_array(columns=16, word_size=8)
self.local_check(a)
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()

0
compiler/tests/19_psingle_bank_test.py Normal file → Executable file
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0
compiler/tests/20_psram_1bank_test.py Normal file → Executable file
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20
compiler/tests/21_hspice_delay_test.py
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@ -62,17 +62,17 @@ class timing_sram_test(openram_test):
'slew_lh0': [0.0236264],
'write0_power0': [0.06545659999999999],
'write1_power0': [0.057846299999999996]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'delay_hl0': [4.0249],
'delay_lh0': [2.2611],
'leakage_power': 0.0257389,
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl0': [3.452],
'delay_lh0': [1.3792000000000002],
'leakage_power': 0.0257065,
'min_period': 4.688,
'read0_power0': [24.9279],
'read1_power0': [24.0219],
'slew_hl0': [0.8500753999999999],
'slew_lh0': [0.4122653],
'write0_power0': [28.197600000000005],
'write1_power0': [25.685]}
'read0_power0': [15.0755],
'read1_power0': [14.4526],
'slew_hl0': [0.6137363],
'slew_lh0': [0.3381045],
'write0_power0': [16.9203],
'write1_power0': [15.367]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results

18
compiler/tests/21_hspice_setuphold_test.py
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@ -35,15 +35,15 @@ class timing_setup_test(openram_test):
data = sh.analyze(slews,slews)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {'setup_times_LH': [0.014648399999999999],
'hold_times_LH': [0.0024414],
'hold_times_HL': [-0.0036620999999999997],
'setup_times_HL': [0.0085449]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'setup_times_LH': [0.08178709999999999],
'hold_times_LH': [0.0024414],
'hold_times_HL': [-0.0646973],
'setup_times_HL': [0.0390625]}
golden_data = {'hold_times_HL': [-0.0097656],
'hold_times_LH': [-0.0158691],
'setup_times_HL': [0.026855499999999997],
'setup_times_LH': [0.032959]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'hold_times_HL': [-0.0891113],
'hold_times_LH': [-0.0769043],
'setup_times_HL': [0.1184082],
'setup_times_LH': [0.1733398]}
else:
self.assertTrue(False) # other techs fail

20
compiler/tests/21_ngspice_delay_test.py
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@ -61,17 +61,17 @@ class timing_sram_test(openram_test):
'slew_lh0': [0.025474979999999998],
'write0_power0': [0.06513271999999999],
'write1_power0': [0.058057000000000004]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'delay_hl0': [4.221382999999999],
'delay_lh0': [2.6459520000000003],
'leakage_power': 0.0013865260000000001,
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl0': [3.644147],
'delay_lh0': [1.629815],
'leakage_power': 0.0009299118999999999,
'min_period': 4.688,
'read0_power0': [26.699669999999998],
'read1_power0': [26.13123],
'slew_hl0': [0.9821776000000001],
'slew_lh0': [1.5791520000000001],
'write0_power0': [30.71939],
'write1_power0': [27.44753]}
'read0_power0': [16.28732],
'read1_power0': [15.75155],
'slew_hl0': [0.6722473],
'slew_lh0': [0.3386347],
'write0_power0': [18.545450000000002],
'write1_power0': [16.81084]}
else:
self.assertTrue(False) # other techs fail

18
compiler/tests/21_ngspice_setuphold_test.py
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@ -35,15 +35,15 @@ class timing_setup_test(openram_test):
data = sh.analyze(slews,slews)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {'setup_times_LH': [0.01464844],
'hold_times_LH': [0.0024414059999999997],
'hold_times_HL': [-0.003662109],
'setup_times_HL': [0.008544922]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'setup_times_LH': [0.07568359],
'hold_times_LH': [0.008544922],
'hold_times_HL': [-0.05859374999999999],
'setup_times_HL': [0.03295898]}
golden_data = {'hold_times_HL': [-0.01586914],
'hold_times_LH': [-0.01586914],
'setup_times_HL': [0.02685547],
'setup_times_LH': [0.03295898]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'hold_times_HL': [-0.08911132999999999],
'hold_times_LH': [-0.0769043],
'setup_times_HL': [0.1184082],
'setup_times_LH': [0.1672363]}
else:
self.assertTrue(False) # other techs fail

13
compiler/tests/config_20_scn4m_subm.py Normal file
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@ -0,0 +1,13 @@
word_size = 1
num_words = 16
num_banks = 1
tech_name = "scn4m_subm"
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"

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compiler/tests/golden/sram_2_16_1_scn4m_subm.lef Normal file
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File diff suppressed because it is too large Load Diff

681
compiler/tests/golden/sram_2_16_1_scn4m_subm.sp vendored Normal file
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@ -0,0 +1,681 @@
* OpenRAM generated memory.
* User: mrg
.global vdd gnd
*master-slave flip-flop with both output and inverted ouput
.subckt ms_flop din dout dout_bar clk vdd gnd
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
.ends flop
.subckt dlatch din dout dout_bar clk clk_bar vdd gnd
*clk inverter
mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1
*transmission gate 1
mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1
mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1
*foward inverter
mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1
mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1
*backward inverter
mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1
mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1
*transmission gate 2
mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
.ends dlatch
.SUBCKT inv_nmos11 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS inv_nmos11
.SUBCKT inv_pmos12 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS inv_pmos12
.SUBCKT pinv A Z vdd gnd
Xpinv_nmos Z A gnd gnd inv_nmos11
Xpinv_pmos Z A vdd vdd inv_pmos12
.ENDS pinv
.SUBCKT nand_2_nmos13 D G S B
Mnmos D G S B n m=1 w=2.4u l=0.6u
.ENDS nand_2_nmos13
.SUBCKT nand_2_nmos24 D G S B
Mnmos D G S B n m=1 w=2.4u l=0.6u
.ENDS nand_2_nmos24
.SUBCKT nand_2_pmos15 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_2_pmos15
.SUBCKT nand_2_pmos26 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_2_pmos26
.SUBCKT nand2 A B Z vdd gnd
Xnmos1 Z A net1 gnd nand_2_nmos13
Xnmos2 net1 B gnd gnd nand_2_nmos24
Xpmos1 vdd A Z vdd nand_2_pmos15
Xpmos2 Z B vdd vdd nand_2_pmos26
.ENDS nand2
.SUBCKT nand_3_nmos17 D G S B
Mnmos D G S B n m=1 w=3.6u l=0.6u
.ENDS nand_3_nmos17
.SUBCKT nand_3_nmos28 D G S B
Mnmos D G S B n m=1 w=3.6u l=0.6u
.ENDS nand_3_nmos28
.SUBCKT nand_3_nmos39 D G S B
Mnmos D G S B n m=1 w=3.6u l=0.6u
.ENDS nand_3_nmos39
.SUBCKT nand_3_pmos110 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_3_pmos110
.SUBCKT nand_3_pmos211 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_3_pmos211
.SUBCKT nand_3_pmos312 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_3_pmos312
.SUBCKT NAND3 A B C Z vdd gnd
Xnmos1 net2 A gnd gnd nand_3_nmos17
Xnmos2 net1 B net2 gnd nand_3_nmos28
Xnmos3 Z C net1 gnd nand_3_nmos39
Xpmos1 Z A vdd vdd nand_3_pmos110
Xpmos2 vdd B Z vdd nand_3_pmos211
Xpmos3 Z C vdd vdd nand_3_pmos312
.ENDS NAND3
.SUBCKT inv_nmos113 D G S B
Mnmos D G S B n m=4 w=1.2u l=0.6u
.ENDS inv_nmos113
.SUBCKT inv_pmos114 D G S B
Mpmos D G S B p m=4 w=2.4u l=0.6u
.ENDS inv_pmos114
.SUBCKT pinv4 A Z vdd gnd
Xpinv_nmos Z A gnd gnd inv_nmos113
Xpinv_pmos Z A vdd vdd inv_pmos114
.ENDS pinv4
.SUBCKT nor_2_nmos123 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS nor_2_nmos123
.SUBCKT nor_2_nmos224 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS nor_2_nmos224
.SUBCKT nor_2_pmos125 D G S B
Mpmos D G S B p m=4 w=1.2u l=0.6u
.ENDS nor_2_pmos125
.SUBCKT nor_2_pmos226 D G S B
Mpmos D G S B p m=4 w=1.2u l=0.6u
.ENDS nor_2_pmos226
.SUBCKT nor2 A B Z vdd gnd
Xnmos1 Z A gnd gnd nor_2_nmos123
Xnmos2 Z B gnd gnd nor_2_nmos224
Xpmos1 vdd A net1 vdd nor_2_pmos125
Xpmos2 net1 B Z vdd nor_2_pmos226
.ENDS nor2
.SUBCKT msf_control DATA[0] DATA[1] DATA[2] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] data_in[2] data_in_bar[2] clk vdd gnd
XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop
XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop
XXdff2 DATA[2] data_in[2] data_in_bar[2] clk vdd gnd ms_flop
.ENDS msf_control
*********************** "cell_6t" ******************************
.SUBCKT replica_cell_6t bl br wl vdd gnd
M_1 gnd net_2 vdd vdd p W='0.9u' L=1.2u
M_2 net_2 gnd vdd vdd p W='0.9u' L=1.2u
M_3 br wl net_2 gnd n W='1.2u' L=0.6u
M_4 bl wl gnd gnd n W='1.2u' L=0.6u
M_5 net_2 gnd gnd gnd n W='2.4u' L=0.6u
M_6 gnd net_2 gnd gnd n W='2.4u' L=0.6u
.ENDS $ replica_cell_6t
*********************** "cell_6t" ******************************
.SUBCKT cell_6t bl br wl vdd gnd
M_1 net_1 net_2 vdd vdd p W='0.9u' L=1.2u
M_2 net_2 net_1 vdd vdd p W='0.9u' L=1.2u
M_3 br wl net_2 gnd n W='1.2u' L=0.6u
M_4 bl wl net_1 gnd n W='1.2u' L=0.6u
M_5 net_2 net_1 gnd gnd n W='2.4u' L=0.6u
M_6 net_1 net_2 gnd gnd n W='2.4u' L=0.6u
.ENDS $ cell_6t
.SUBCKT bitline_load bl[0] br[0] wl[0] wl[1] vdd gnd
Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t
Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t
.ENDS bitline_load
.SUBCKT inv_nmos127 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS inv_nmos127
.SUBCKT inv_pmos128 D G S B
Mpmos D G S B p m=1 w=3.6u l=0.6u
.ENDS inv_pmos128
.SUBCKT delay_chain_inv A Z vdd gnd
Xpinv_nmos Z A gnd gnd inv_nmos127
Xpinv_pmos Z A vdd vdd inv_pmos128
.ENDS delay_chain_inv
.SUBCKT delay_chain clk_in clk_out vdd gnd
Xinv_chain0 clk_in s1 vdd gnd delay_chain_inv
Xinv_chain1 s1 s2 vdd gnd delay_chain_inv
Xinv_chain2 s2 s3 vdd gnd delay_chain_inv
Xinv_chain3 s3 clk_out vdd gnd delay_chain_inv
.ENDS delay_chain
.SUBCKT inv_nmos129 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS inv_nmos129
.SUBCKT inv_pmos130 D G S B
Mpmos D G S B p m=1 w=3.6u l=0.6u
.ENDS inv_pmos130
.SUBCKT RBL_inv A Z vdd gnd
Xpinv_nmos Z A gnd gnd inv_nmos129
Xpinv_pmos Z A vdd vdd inv_pmos130
.ENDS RBL_inv
.SUBCKT nor_2_nmos139 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS nor_2_nmos139
.SUBCKT nor_2_nmos240 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS nor_2_nmos240
.SUBCKT nor_2_pmos141 D G S B
Mpmos D G S B p m=4 w=1.2u l=0.6u
.ENDS nor_2_pmos141
.SUBCKT nor_2_pmos242 D G S B
Mpmos D G S B p m=4 w=1.2u l=0.6u
.ENDS nor_2_pmos242
.SUBCKT replica_bitline_nor2 A B Z vdd gnd
Xnmos1 Z A gnd gnd nor_2_nmos139
Xnmos2 Z B gnd gnd nor_2_nmos240
Xpmos1 vdd A net1 vdd nor_2_pmos141
Xpmos2 net1 B Z vdd nor_2_pmos242
.ENDS replica_bitline_nor2
.SUBCKT access_tx43 D G S B
Mpmos D G S B p m=1 w=1.2u l=0.6u
.ENDS access_tx43
.SUBCKT replica_bitline en out vdd gnd
XBL_inv bl[0] out vdd gnd RBL_inv
XBL_access_tx vdd delayed_en bl[0] vdd access_tx43
Xdelay_chain en delayed_en vdd gnd delay_chain
Xbitcell bl[0] br[0] delayed_en vdd gnd replica_cell_6t
Xload bl[0] br[0] gnd gnd vdd gnd bitline_load
.ENDS replica_bitline
.SUBCKT control_logic CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd
Xmsf_control CSb WEb OEb CS_bar CS WE_bar WE OE_bar OE clk vdd gnd msf_control
Xclk_inverter clk clk_bar vdd gnd pinv4
Xnor2 clk OE_bar tri_en vdd gnd nor2
Xnand2_tri_en OE clk_bar tri_en_bar vdd gnd nand2
Xreplica_bitline rblk pre_s_en vdd gnd replica_bitline
Xinv_s_en1 pre_s_en_bar s_en vdd gnd pinv
Xinv_s_en2 pre_s_en pre_s_en_bar vdd gnd pinv
XNAND3_rblk_bar clk_bar OE CS rblk_bar vdd gnd NAND3
XNAND3_w_en_bar clk_bar WE CS w_en_bar vdd gnd NAND3
Xinv_rblk rblk_bar rblk vdd gnd pinv
Xinv_w_en w_en_bar pre_w_en vdd gnd pinv
Xinv_w_en1 pre_w_en pre_w_en1 vdd gnd pinv
Xinv_w_en2 pre_w_en1 w_en vdd gnd pinv
.ENDS control_logic
.SUBCKT bitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd
Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t
Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t
Xbit_r2_c0 bl[0] br[0] wl[2] vdd gnd cell_6t
Xbit_r3_c0 bl[0] br[0] wl[3] vdd gnd cell_6t
Xbit_r4_c0 bl[0] br[0] wl[4] vdd gnd cell_6t
Xbit_r5_c0 bl[0] br[0] wl[5] vdd gnd cell_6t
Xbit_r6_c0 bl[0] br[0] wl[6] vdd gnd cell_6t
Xbit_r7_c0 bl[0] br[0] wl[7] vdd gnd cell_6t
Xbit_r8_c0 bl[0] br[0] wl[8] vdd gnd cell_6t
Xbit_r9_c0 bl[0] br[0] wl[9] vdd gnd cell_6t
Xbit_r10_c0 bl[0] br[0] wl[10] vdd gnd cell_6t
Xbit_r11_c0 bl[0] br[0] wl[11] vdd gnd cell_6t
Xbit_r12_c0 bl[0] br[0] wl[12] vdd gnd cell_6t
Xbit_r13_c0 bl[0] br[0] wl[13] vdd gnd cell_6t
Xbit_r14_c0 bl[0] br[0] wl[14] vdd gnd cell_6t
Xbit_r15_c0 bl[0] br[0] wl[15] vdd gnd cell_6t
Xbit_r0_c1 bl[1] br[1] wl[0] vdd gnd cell_6t
Xbit_r1_c1 bl[1] br[1] wl[1] vdd gnd cell_6t
Xbit_r2_c1 bl[1] br[1] wl[2] vdd gnd cell_6t
Xbit_r3_c1 bl[1] br[1] wl[3] vdd gnd cell_6t
Xbit_r4_c1 bl[1] br[1] wl[4] vdd gnd cell_6t
Xbit_r5_c1 bl[1] br[1] wl[5] vdd gnd cell_6t
Xbit_r6_c1 bl[1] br[1] wl[6] vdd gnd cell_6t
Xbit_r7_c1 bl[1] br[1] wl[7] vdd gnd cell_6t
Xbit_r8_c1 bl[1] br[1] wl[8] vdd gnd cell_6t
Xbit_r9_c1 bl[1] br[1] wl[9] vdd gnd cell_6t
Xbit_r10_c1 bl[1] br[1] wl[10] vdd gnd cell_6t
Xbit_r11_c1 bl[1] br[1] wl[11] vdd gnd cell_6t
Xbit_r12_c1 bl[1] br[1] wl[12] vdd gnd cell_6t
Xbit_r13_c1 bl[1] br[1] wl[13] vdd gnd cell_6t
Xbit_r14_c1 bl[1] br[1] wl[14] vdd gnd cell_6t
Xbit_r15_c1 bl[1] br[1] wl[15] vdd gnd cell_6t
.ENDS bitcell_array
.SUBCKT lower_pmos44 D G S B
Mpmos D G S B p m=1 w=1.2u l=0.6u
.ENDS lower_pmos44
.SUBCKT upper_pmos45 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS upper_pmos45
.SUBCKT precharge_cell bl br clk vdd
Xlower_pmos bl clk br vdd lower_pmos44
Xupper_pmos1 bl clk vdd vdd upper_pmos45
Xupper_pmos2 br clk vdd vdd upper_pmos45
.ENDS precharge_cell
.SUBCKT precharge_array bl[0] br[0] bl[1] br[1] clk vdd
Xpre_column_0 bl[0] br[0] clk vdd precharge_cell
Xpre_column_1 bl[1] br[1] clk vdd precharge_cell
.ENDS precharge_array
*********************** "sense_amp" ******************************
.SUBCKT sense_amp bl br dout sclk vdd gnd
M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u
M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u
M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u
M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u
M_5 bl sclk dout vdd p W='7.2*1u' L=0.6u
M_6 br sclk net_1 vdd p W='7.2*1u' L=0.6u
M_7 net_2 sclk gnd gnd n W='2.7*1u' L=0.6u
.ENDS sense_amp
.SUBCKT sense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] sclk vdd gnd
Xsa_d0 bl[0] br[0] data_out[0] sclk vdd gnd sense_amp
Xsa_d1 bl[1] br[1] data_out[1] sclk vdd gnd sense_amp
.ENDS sense_amp_array
*********************** Write_Driver ******************************
.SUBCKT write_driver din bl br wen vdd gnd
**** Inverter to conver Data_in to data_in_bar ******
M_1 net_3 din gnd gnd n W='1.2*1u' L=0.6u
M_2 net_3 din vdd vdd p W='2.1*1u' L=0.6u
**** 2input nand gate follwed by inverter to drive BL ******
M_3 net_2 wen net_7 gnd n W='2.1*1u' L=0.6u
M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u
M_5 net_2 wen vdd vdd p W='2.1*1u' L=0.6u
M_6 net_2 din vdd vdd p W='2.1*1u' L=0.6u
M_7 net_1 net_2 vdd vdd p W='2.1*1u' L=0.6u
M_8 net_1 net_2 gnd gnd n W='1.2*1u' L=0.6u
**** 2input nand gate follwed by inverter to drive BR******
M_9 net_4 wen vdd vdd p W='2.1*1u' L=0.6u
M_10 net_4 wen net_8 gnd n W='2.1*1u' L=0.6u
M_11 net_8 net_3 gnd gnd n W='2.1*1u' L=0.6u
M_12 net_4 net_3 vdd vdd p W='2.1*1u' L=0.6u
M_13 net_6 net_4 vdd vdd p W='2.1*1u' L=0.6u
M_14 net_6 net_4 gnd gnd n W='1.2*1u' L=0.6u
************************************************
M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u
M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u
M_17 net_5 wen gnd gnd n W='3.6*1u' L=0.6u
.ENDS $ write_driver
.SUBCKT write_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] wen vdd gnd
XXwrite_driver0 data_in[0] bl[0] br[0] wen vdd gnd write_driver
XXwrite_driver1 data_in[1] bl[1] br[1] wen vdd gnd write_driver
.ENDS write_driver_array
.SUBCKT inv_nmos147 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS inv_nmos147
.SUBCKT inv_pmos148 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS inv_pmos148
.SUBCKT INVERTER A Z vdd gnd
Xpinv_nmos Z A gnd gnd inv_nmos147
Xpinv_pmos Z A vdd vdd inv_pmos148
.ENDS INVERTER
.SUBCKT nand_2_nmos149 D G S B
Mnmos D G S B n m=1 w=2.4u l=0.6u
.ENDS nand_2_nmos149
.SUBCKT nand_2_nmos250 D G S B
Mnmos D G S B n m=1 w=2.4u l=0.6u
.ENDS nand_2_nmos250
.SUBCKT nand_2_pmos151 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_2_pmos151
.SUBCKT nand_2_pmos252 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_2_pmos252
.SUBCKT NAND2 A B Z vdd gnd
Xnmos1 Z A net1 gnd nand_2_nmos149
Xnmos2 net1 B gnd gnd nand_2_nmos250
Xpmos1 vdd A Z vdd nand_2_pmos151
Xpmos2 Z B vdd vdd nand_2_pmos252
.ENDS NAND2
.SUBCKT nand_2_nmos159 D G S B
Mnmos D G S B n m=1 w=2.4u l=0.6u
.ENDS nand_2_nmos159
.SUBCKT nand_2_nmos260 D G S B
Mnmos D G S B n m=1 w=2.4u l=0.6u
.ENDS nand_2_nmos260
.SUBCKT nand_2_pmos161 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_2_pmos161
.SUBCKT nand_2_pmos262 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_2_pmos262
.SUBCKT a_nand_2 A B Z vdd gnd
Xnmos1 Z A net1 gnd nand_2_nmos159
Xnmos2 net1 B gnd gnd nand_2_nmos260
Xpmos1 vdd A Z vdd nand_2_pmos161
Xpmos2 Z B vdd vdd nand_2_pmos262
.ENDS a_nand_2
.SUBCKT inv_nmos163 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS inv_nmos163
.SUBCKT inv_pmos164 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS inv_pmos164
.SUBCKT a_inv_1 A Z vdd gnd
Xpinv_nmos Z A gnd gnd inv_nmos163
Xpinv_pmos Z A vdd vdd inv_pmos164
.ENDS a_inv_1
.SUBCKT pre2x4 A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd
XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1
XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1
XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1
XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1
XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1
XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1
XXpre2x4_nand[0] A[0] A[1] Z[3] vdd gnd a_nand_2
XXpre2x4_nand[1] B[0] A[1] Z[2] vdd gnd a_nand_2
XXpre2x4_nand[2] A[0] B[1] Z[1] vdd gnd a_nand_2
XXpre2x4_nand[3] B[0] B[1] Z[0] vdd gnd a_nand_2
.ENDS pre2x4
.SUBCKT nand_3_nmos165 D G S B
Mnmos D G S B n m=1 w=3.6u l=0.6u
.ENDS nand_3_nmos165
.SUBCKT nand_3_nmos266 D G S B
Mnmos D G S B n m=1 w=3.6u l=0.6u
.ENDS nand_3_nmos266
.SUBCKT nand_3_nmos367 D G S B
Mnmos D G S B n m=1 w=3.6u l=0.6u
.ENDS nand_3_nmos367
.SUBCKT nand_3_pmos168 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_3_pmos168
.SUBCKT nand_3_pmos269 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_3_pmos269
.SUBCKT nand_3_pmos370 D G S B
Mpmos D G S B p m=1 w=2.4u l=0.6u
.ENDS nand_3_pmos370
.SUBCKT a_nand_3 A B C Z vdd gnd
Xnmos1 net2 A gnd gnd nand_3_nmos165
Xnmos2 net1 B net2 gnd nand_3_nmos266
Xnmos3 Z C net1 gnd nand_3_nmos367
Xpmos1 Z A vdd vdd nand_3_pmos168
Xpmos2 vdd B Z vdd nand_3_pmos269
Xpmos3 Z C vdd vdd nand_3_pmos370
.ENDS a_nand_3
.SUBCKT pre3x8 A[0] A[1] A[2] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] vdd gnd
XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1
XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1
XXpre2x4_inv[2] A[2] B[2] vdd gnd a_inv_1
XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1
XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1
XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1
XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1
XXpre2x4_nand_inv[4] Z[4] out[4] vdd gnd a_inv_1
XXpre2x4_nand_inv[5] Z[5] out[5] vdd gnd a_inv_1
XXpre2x4_nand_inv[6] Z[6] out[6] vdd gnd a_inv_1
XXpre2x4_nand_inv[7] Z[7] out[7] vdd gnd a_inv_1
XXpre3x8_nand[0] A[0] A[1] A[2] Z[7] vdd gnd a_nand_3
XXpre3x8_nand[1] A[0] A[1] B[2] Z[6] vdd gnd a_nand_3
XXpre3x8_nand[2] A[0] B[1] A[2] Z[5] vdd gnd a_nand_3
XXpre3x8_nand[3] A[0] B[1] B[2] Z[4] vdd gnd a_nand_3
XXpre3x8_nand[4] B[0] A[1] A[2] Z[3] vdd gnd a_nand_3
XXpre3x8_nand[5] B[0] A[1] B[2] Z[2] vdd gnd a_nand_3
XXpre3x8_nand[6] B[0] B[1] A[2] Z[1] vdd gnd a_nand_3
XXpre3x8_nand[7] B[0] B[1] B[2] Z[0] vdd gnd a_nand_3
.ENDS pre3x8
.SUBCKT hierarchical_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd
Xpre[0] A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd pre2x4
Xpre[1] A[2] A[3] out[4] out[5] out[6] out[7] vdd gnd pre2x4
XNAND2_[0] out[0] out[4] Z[0] vdd gnd NAND2
XNAND2_[1] out[0] out[5] Z[1] vdd gnd NAND2
XNAND2_[2] out[0] out[6] Z[2] vdd gnd NAND2
XNAND2_[3] out[0] out[7] Z[3] vdd gnd NAND2
XNAND2_[4] out[1] out[4] Z[4] vdd gnd NAND2
XNAND2_[5] out[1] out[5] Z[5] vdd gnd NAND2
XNAND2_[6] out[1] out[6] Z[6] vdd gnd NAND2
XNAND2_[7] out[1] out[7] Z[7] vdd gnd NAND2
XNAND2_[8] out[2] out[4] Z[8] vdd gnd NAND2
XNAND2_[9] out[2] out[5] Z[9] vdd gnd NAND2
XNAND2_[10] out[2] out[6] Z[10] vdd gnd NAND2
XNAND2_[11] out[2] out[7] Z[11] vdd gnd NAND2
XNAND2_[12] out[3] out[4] Z[12] vdd gnd NAND2
XNAND2_[13] out[3] out[5] Z[13] vdd gnd NAND2
XNAND2_[14] out[3] out[6] Z[14] vdd gnd NAND2
XNAND2_[15] out[3] out[7] Z[15] vdd gnd NAND2
XINVERTER_[0] Z[0] decode_out[0] vdd gnd INVERTER
XINVERTER_[1] Z[1] decode_out[1] vdd gnd INVERTER
XINVERTER_[2] Z[2] decode_out[2] vdd gnd INVERTER
XINVERTER_[3] Z[3] decode_out[3] vdd gnd INVERTER
XINVERTER_[4] Z[4] decode_out[4] vdd gnd INVERTER
XINVERTER_[5] Z[5] decode_out[5] vdd gnd INVERTER
XINVERTER_[6] Z[6] decode_out[6] vdd gnd INVERTER
XINVERTER_[7] Z[7] decode_out[7] vdd gnd INVERTER
XINVERTER_[8] Z[8] decode_out[8] vdd gnd INVERTER
XINVERTER_[9] Z[9] decode_out[9] vdd gnd INVERTER
XINVERTER_[10] Z[10] decode_out[10] vdd gnd INVERTER
XINVERTER_[11] Z[11] decode_out[11] vdd gnd INVERTER
XINVERTER_[12] Z[12] decode_out[12] vdd gnd INVERTER
XINVERTER_[13] Z[13] decode_out[13] vdd gnd INVERTER
XINVERTER_[14] Z[14] decode_out[14] vdd gnd INVERTER
XINVERTER_[15] Z[15] decode_out[15] vdd gnd INVERTER
.ENDS hierarchical_decoder
.SUBCKT msf_address ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] addr_clk vdd gnd
XXdff0 ADDR[0] A[0] A_bar[0] addr_clk vdd gnd ms_flop
XXdff1 ADDR[1] A[1] A_bar[1] addr_clk vdd gnd ms_flop
XXdff2 ADDR[2] A[2] A_bar[2] addr_clk vdd gnd ms_flop
XXdff3 ADDR[3] A[3] A_bar[3] addr_clk vdd gnd ms_flop
.ENDS msf_address
.SUBCKT msf_data_in DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk vdd gnd
XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop
XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop
.ENDS msf_data_in
.SUBCKT msf_data_out data_out[0] data_out[1] tri_in[0] tri_in_bar[0] tri_in[1] tri_in_bar[1] sclk vdd gnd
XXdff0 data_out[0] tri_in[0] tri_in_bar[0] sclk vdd gnd ms_flop
XXdff1 data_out[1] tri_in[1] tri_in_bar[1] sclk vdd gnd ms_flop
.ENDS msf_data_out
*********************** tri_gate ******************************
.SUBCKT tri_gate in out en en_bar vdd gnd
M_1 net_2 in_inv gnd gnd n W='1.2*1u' L=0.6u
M_2 net_3 in_inv vdd vdd p W='2.4*1u' L=0.6u
M_3 out en_bar net_3 vdd p W='2.4*1u' L=0.6u
M_4 out en net_2 gnd n W='1.2*1u' L=0.6u
M_5 in_inv in vdd vdd p W='2.4*1u' L=0.6u
M_6 in_inv in gnd gnd n W='1.2*1u' L=0.6u
.ENDS
.SUBCKT tri_gate_array tri_in[0] tri_in[1] DATA[0] DATA[1] en en_bar vdd gnd
XXtri_gate0 tri_in[0] DATA[0] en en_bar vdd gnd tri_gate
XXtri_gate1 tri_in[1] DATA[1] en en_bar vdd gnd tri_gate
.ENDS tri_gate_array
.SUBCKT wordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd
XWordline_driver_inv_clk0 clk clk_bar[0] vdd gnd INVERTER
XWordline_driver_nand0 decode_out[0] clk_bar[0] net[0] vdd gnd NAND2
XWordline_driver_inv0 net[0] wl[0] vdd gnd INVERTER
XWordline_driver_inv_clk1 clk clk_bar[1] vdd gnd INVERTER
XWordline_driver_nand1 decode_out[1] clk_bar[1] net[1] vdd gnd NAND2
XWordline_driver_inv1 net[1] wl[1] vdd gnd INVERTER
XWordline_driver_inv_clk2 clk clk_bar[2] vdd gnd INVERTER
XWordline_driver_nand2 decode_out[2] clk_bar[2] net[2] vdd gnd NAND2
XWordline_driver_inv2 net[2] wl[2] vdd gnd INVERTER
XWordline_driver_inv_clk3 clk clk_bar[3] vdd gnd INVERTER
XWordline_driver_nand3 decode_out[3] clk_bar[3] net[3] vdd gnd NAND2
XWordline_driver_inv3 net[3] wl[3] vdd gnd INVERTER
XWordline_driver_inv_clk4 clk clk_bar[4] vdd gnd INVERTER
XWordline_driver_nand4 decode_out[4] clk_bar[4] net[4] vdd gnd NAND2
XWordline_driver_inv4 net[4] wl[4] vdd gnd INVERTER
XWordline_driver_inv_clk5 clk clk_bar[5] vdd gnd INVERTER
XWordline_driver_nand5 decode_out[5] clk_bar[5] net[5] vdd gnd NAND2
XWordline_driver_inv5 net[5] wl[5] vdd gnd INVERTER
XWordline_driver_inv_clk6 clk clk_bar[6] vdd gnd INVERTER
XWordline_driver_nand6 decode_out[6] clk_bar[6] net[6] vdd gnd NAND2
XWordline_driver_inv6 net[6] wl[6] vdd gnd INVERTER
XWordline_driver_inv_clk7 clk clk_bar[7] vdd gnd INVERTER
XWordline_driver_nand7 decode_out[7] clk_bar[7] net[7] vdd gnd NAND2
XWordline_driver_inv7 net[7] wl[7] vdd gnd INVERTER
XWordline_driver_inv_clk8 clk clk_bar[8] vdd gnd INVERTER
XWordline_driver_nand8 decode_out[8] clk_bar[8] net[8] vdd gnd NAND2
XWordline_driver_inv8 net[8] wl[8] vdd gnd INVERTER
XWordline_driver_inv_clk9 clk clk_bar[9] vdd gnd INVERTER
XWordline_driver_nand9 decode_out[9] clk_bar[9] net[9] vdd gnd NAND2
XWordline_driver_inv9 net[9] wl[9] vdd gnd INVERTER
XWordline_driver_inv_clk10 clk clk_bar[10] vdd gnd INVERTER
XWordline_driver_nand10 decode_out[10] clk_bar[10] net[10] vdd gnd NAND2
XWordline_driver_inv10 net[10] wl[10] vdd gnd INVERTER
XWordline_driver_inv_clk11 clk clk_bar[11] vdd gnd INVERTER
XWordline_driver_nand11 decode_out[11] clk_bar[11] net[11] vdd gnd NAND2
XWordline_driver_inv11 net[11] wl[11] vdd gnd INVERTER
XWordline_driver_inv_clk12 clk clk_bar[12] vdd gnd INVERTER
XWordline_driver_nand12 decode_out[12] clk_bar[12] net[12] vdd gnd NAND2
XWordline_driver_inv12 net[12] wl[12] vdd gnd INVERTER
XWordline_driver_inv_clk13 clk clk_bar[13] vdd gnd INVERTER
XWordline_driver_nand13 decode_out[13] clk_bar[13] net[13] vdd gnd NAND2
XWordline_driver_inv13 net[13] wl[13] vdd gnd INVERTER
XWordline_driver_inv_clk14 clk clk_bar[14] vdd gnd INVERTER
XWordline_driver_nand14 decode_out[14] clk_bar[14] net[14] vdd gnd NAND2
XWordline_driver_inv14 net[14] wl[14] vdd gnd INVERTER
XWordline_driver_inv_clk15 clk clk_bar[15] vdd gnd INVERTER
XWordline_driver_nand15 decode_out[15] clk_bar[15] net[15] vdd gnd NAND2
XWordline_driver_inv15 net[15] wl[15] vdd gnd INVERTER
.ENDS wordline_driver
.SUBCKT inv_nmos181 D G S B
Mnmos D G S B n m=4 w=1.2u l=0.6u
.ENDS inv_nmos181
.SUBCKT inv_pmos182 D G S B
Mpmos D G S B p m=4 w=2.4u l=0.6u
.ENDS inv_pmos182
.SUBCKT pinv4x A Z vdd gnd
Xpinv_nmos Z A gnd gnd inv_nmos181
Xpinv_pmos Z A vdd vdd inv_pmos182
.ENDS pinv4x
.SUBCKT nor_2_nmos195 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS nor_2_nmos195
.SUBCKT nor_2_nmos296 D G S B
Mnmos D G S B n m=1 w=1.2u l=0.6u
.ENDS nor_2_nmos296
.SUBCKT nor_2_pmos197 D G S B
Mpmos D G S B p m=4 w=1.2u l=0.6u
.ENDS nor_2_pmos197
.SUBCKT nor_2_pmos298 D G S B
Mpmos D G S B p m=4 w=1.2u l=0.6u
.ENDS nor_2_pmos298
.SUBCKT NOR2 A B Z vdd gnd
Xnmos1 Z A gnd gnd nor_2_nmos195
Xnmos2 Z B gnd gnd nor_2_nmos296
Xpmos1 vdd A net1 vdd nor_2_pmos197
Xpmos2 net1 B Z vdd nor_2_pmos298
.ENDS NOR2
.SUBCKT test_bank1 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd
Xbitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd bitcell_array
Xprecharge_array bl[0] br[0] bl[1] br[1] clk_bar vdd precharge_array
Xsense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] s_en vdd gnd sense_amp_array
Xwrite_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] w_en vdd gnd write_driver_array
Xdata_in_flop_array DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk_bar vdd gnd msf_data_in
Xtrigate_data_array data_out[0] data_out[1] DATA[0] DATA[1] tri_en tri_en_bar vdd gnd tri_gate_array
Xaddress_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd hierarchical_decoder
Xwordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd wordline_driver
Xaddress_flop_array ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] clk vdd gnd msf_address
.ENDS test_bank1
.SUBCKT testsram DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] CSb WEb OEb clk vdd gnd
Xbank0 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd test_bank1
Xcontrol CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd control_logic
.ENDS testsram

47
compiler/tests/golden/sram_2_16_1_scn4m_subm.v Normal file
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@ -0,0 +1,47 @@
// OpenRAM SRAM model
// Words: 16
// Word size: 2
module sram_2_16_1_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk);
parameter DATA_WIDTH = 2 ;
parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
parameter DELAY = 3 ;
inout [DATA_WIDTH-1:0] DATA;
input [ADDR_WIDTH-1:0] ADDR;
input CSb; // active low chip select
input WEb; // active low write control
input OEb; // active output enable
input clk; // clock
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Tri-State Buffer control
// output : When WEb = 1, oeb = 0, csb = 0
assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
// Memory Write Block
// Write Operation : When WEb = 0, CSb = 0
always @ (posedge clk)
begin : MEM_WRITE
if ( !CSb && !WEb ) begin
mem[ADDR] = DATA;
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
end
end
// Memory Read Block
// Read Operation : When WEb = 1, CSb = 0
always @ (posedge clk)
begin : MEM_READ
if (!CSb && WEb) begin
data_out <= #(DELAY) mem[ADDR];
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
end
end
endmodule

318
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib Normal file
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library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.0125, 0.05, 0.4");
index_2("2.45605, 9.8242, 78.5936");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.0125, 0.05, 0.4");
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 2;
bit_from : 0;
bit_to : 1;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 4;
bit_from : 0;
bit_to : 3;
}
cell (sram_2_16_1_scn4m_subm){
memory(){
type : ram;
address_width : 4;
word_width : 2;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 60176.520000000004;
leakage_power () {
when : "CSb0";
value : 0.000175;
}
cell_leakage_power : 0;
bus(DIN0){
bus_type : DATA;
direction : input;
capacitance : 9.8242;
memory_write(){
address : ADDR0;
clocked_on : clk;
}
}
bus(DOUT0){
bus_type : DATA;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
memory_read(){
address : ADDR0;
}
pin(DOUT0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : rising_edge;
cell_rise(CELL_TABLE) {
values("0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268");
}
cell_fall(CELL_TABLE) {
values("0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268");
}
rise_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
}
fall_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
}
}
}
}
bus(ADDR0){
bus_type : ADDR;
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
}
pin(CSb0){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(WEb0){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb0 & clk & !WEb0";
rise_power(scalar){
values("11.3007276371");
}
fall_power(scalar){
values("11.3007276371");
}
}
internal_power(){
when : "!CSb0 & !clk & WEb0";
rise_power(scalar){
values("11.3007276371");
}
fall_power(scalar){
values("11.3007276371");
}
}
internal_power(){
when : "CSb0";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.0");
}
fall_constraint(scalar) {
values("0.0");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0");
}
fall_constraint(scalar) {
values("0");
}
}
}
}
}

318
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib Normal file
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@ -0,0 +1,318 @@
library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.0125, 0.05, 0.4");
index_2("2.45605, 9.8242, 78.5936");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.0125, 0.05, 0.4");
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 2;
bit_from : 0;
bit_to : 1;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 4;
bit_from : 0;
bit_to : 3;
}
cell (sram_2_16_1_scn4m_subm){
memory(){
type : ram;
address_width : 4;
word_width : 2;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 60176.520000000004;
leakage_power () {
when : "CSb0";
value : 0.000175;
}
cell_leakage_power : 0;
bus(DIN0){
bus_type : DATA;
direction : input;
capacitance : 9.8242;
memory_write(){
address : ADDR0;
clocked_on : clk;
}
}
bus(DOUT0){
bus_type : DATA;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
memory_read(){
address : ADDR0;
}
pin(DOUT0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : rising_edge;
cell_rise(CELL_TABLE) {
values("0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268");
}
cell_fall(CELL_TABLE) {
values("0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268");
}
rise_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
}
fall_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
}
}
}
}
bus(ADDR0){
bus_type : ADDR;
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
}
pin(CSb0){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(WEb0){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb0 & clk & !WEb0";
rise_power(scalar){
values("11.3007276371");
}
fall_power(scalar){
values("11.3007276371");
}
}
internal_power(){
when : "!CSb0 & !clk & WEb0";
rise_power(scalar){
values("11.3007276371");
}
fall_power(scalar){
values("11.3007276371");
}
}
internal_power(){
when : "CSb0";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.0");
}
fall_constraint(scalar) {
values("0.0");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0");
}
fall_constraint(scalar) {
values("0");
}
}
}
}
}

318
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib Normal file
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@ -0,0 +1,318 @@
library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
current_unit : "1mA" ;
resistance_unit : "1kohm" ;
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
output_threshold_pct_fall : 50.0 ;
input_threshold_pct_rise : 50.0 ;
output_threshold_pct_rise : 50.0 ;
slew_lower_threshold_pct_fall : 10.0 ;
slew_upper_threshold_pct_fall : 90.0 ;
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
default_inout_pin_cap : 1.0 ;
default_output_pin_cap : 0.0 ;
default_max_transition : 0.5 ;
default_fanout_load : 1.0 ;
default_max_fanout : 4.0 ;
default_connection_class : universal ;
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.0125, 0.05, 0.4");
index_2("2.45605, 9.8242, 78.5936");
}
lu_table_template(CONSTRAINT_TABLE){
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1("0.0125, 0.05, 0.4");
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : OC;
type (DATA){
base_type : array;
data_type : bit;
bit_width : 2;
bit_from : 0;
bit_to : 1;
}
type (ADDR){
base_type : array;
data_type : bit;
bit_width : 4;
bit_from : 0;
bit_to : 3;
}
cell (sram_2_16_1_scn4m_subm){
memory(){
type : ram;
address_width : 4;
word_width : 2;
}
interface_timing : true;
dont_use : true;
map_only : true;
dont_touch : true;
area : 60176.520000000004;
leakage_power () {
when : "CSb0";
value : 0.025716199999999998;
}
cell_leakage_power : 0;
bus(DIN0){
bus_type : DATA;
direction : input;
capacitance : 9.8242;
memory_write(){
address : ADDR0;
clocked_on : clk;
}
}
bus(DOUT0){
bus_type : DATA;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
memory_read(){
address : ADDR0;
}
pin(DOUT0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.179, 0.173, 0.228",\
"0.179, 0.173, 0.228",\
"0.179, 0.173, 0.228");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.125, 0.125, 0.143",\
"0.125, 0.125, 0.143",\
"0.125, 0.125, 0.143");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.089, -0.089, -0.095",\
"-0.089, -0.089, -0.095",\
"-0.089, -0.089, -0.095");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : rising_edge;
cell_rise(CELL_TABLE) {
values("1.277, 1.297, 1.475",\
"1.28, 1.3, 1.479",\
"1.347, 1.367, 1.545");
}
cell_fall(CELL_TABLE) {
values("3.217, 3.281, 3.71",\
"3.22, 3.285, 3.714",\
"3.261, 3.325, 3.75");
}
rise_transition(CELL_TABLE) {
values("0.122, 0.164, 0.579",\
"0.122, 0.164, 0.578",\
"0.122, 0.164, 0.58");
}
fall_transition(CELL_TABLE) {
values("0.363, 0.396, 0.958",\
"0.363, 0.396, 0.957",\
"0.366, 0.399, 0.951");
}
}
}
}
bus(ADDR0){
bus_type : ADDR;
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.179, 0.173, 0.228",\
"0.179, 0.173, 0.228",\
"0.179, 0.173, 0.228");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.125, 0.125, 0.143",\
"0.125, 0.125, 0.143",\
"0.125, 0.125, 0.143");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.089, -0.089, -0.095",\
"-0.089, -0.089, -0.095",\
"-0.089, -0.089, -0.095");
}
}
}
}
pin(CSb0){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.179, 0.173, 0.228",\
"0.179, 0.173, 0.228",\
"0.179, 0.173, 0.228");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.125, 0.125, 0.143",\
"0.125, 0.125, 0.143",\
"0.125, 0.125, 0.143");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.089, -0.089, -0.095",\
"-0.089, -0.089, -0.095",\
"-0.089, -0.089, -0.095");
}
}
}
pin(WEb0){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.179, 0.173, 0.228",\
"0.179, 0.173, 0.228",\
"0.179, 0.173, 0.228");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.125, 0.125, 0.143",\
"0.125, 0.125, 0.143",\
"0.125, 0.125, 0.143");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.089, -0.089, -0.095",\
"-0.089, -0.089, -0.095",\
"-0.089, -0.089, -0.095");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb0 & clk & !WEb0";
rise_power(scalar){
values("9.141838916666668");
}
fall_power(scalar){
values("9.141838916666668");
}
}
internal_power(){
when : "!CSb0 & !clk & WEb0";
rise_power(scalar){
values("8.304491694444444");
}
fall_power(scalar){
values("8.304491694444444");
}
}
internal_power(){
when : "CSb0";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("2.344");
}
fall_constraint(scalar) {
values("2.344");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("4.688");
}
fall_constraint(scalar) {
values("4.688");
}
}
}
}
}

16
compiler/tests/testutils.py
View File

@ -227,17 +227,21 @@ class openram_test(unittest.TestCase):
check = filecmp.cmp(filename1,filename2)
if not check:
debug.error("MISMATCH file1={0} file2={1}".format(filename1,filename2))
f1 = open(filename1,"r")
s1 = f1.readlines().decode('utf-8')
f1 = open(filename1,mode="r",encoding='utf-8')
s1 = f1.readlines()
f1.close()
f2 = open(filename2,"r").decode('utf-8')
f2 = open(filename2,mode="r",encoding='utf-8')
s2 = f2.readlines()
f2.close()
mismatches=0
for line in difflib.unified_diff(s1, s2):
for line in list(difflib.unified_diff(s1, s2)):
mismatches += 1
self.error("DIFF LINES:",line)
if mismatches>10:
if mismatches==0:
print("DIFF LINES:")
if mismatches<11:
print(line.rstrip('\n'))
else:
return False
return False
else:

5
compiler/verify/magic.py
View File

@ -99,7 +99,10 @@ def write_netgen_script(cell_name, sp_name):
f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name))
# This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass
# Is there a more elegant way to add this when needed?
f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name))
f.write("flatten class {{{0}.spice precharge_array_1}}\n".format(cell_name))
f.write("flatten class {{{0}.spice precharge_array_2}}\n".format(cell_name))
f.write("flatten class {{{0}.spice precharge_array_3}}\n".format(cell_name))
f.write("flatten class {{{0}.spice precharge_array_4}}\n".format(cell_name))
f.write("property {{nfet {0}.spice}} remove as ad ps pd\n".format(cell_name))
f.write("property {{pfet {0}.spice}} remove as ad ps pd\n".format(cell_name))
f.write("property {{n {0}}} remove as ad ps pd\n".format(sp_name))

BIN
technology/freepdk45/gds_lib/ms_flop.gds
View File

Binary file not shown.

29
technology/freepdk45/sp_lib/ms_flop.sp vendored
View File

@ -1,29 +0,0 @@
*master-slave flip-flop with both output and inverted ouput
.SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd
*clk inverter
mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1
mNff1 clk_bar clk gnd gnd NMOS_VTG W=90n L=50n m=1
*transmission gate 1
mtmP1 din clk int1 vdd PMOS_VTG W=180.0n L=50n m=1
mtmN1 din clk_bar int1 gnd NMOS_VTG W=90n L=50n m=1
*foward inverter
mPff3 dout_bar int1 vdd vdd PMOS_VTG W=180.0n L=50n m=1
mNff3 dout_bar int1 gnd gnd NMOS_VTG W=90n L=50n m=1
*backward inverter
mPff4 dout dout_bar vdd vdd PMOS_VTG W=180.0n L=50n m=1
mNf4 dout dout_bar gnd gnd NMOS_VTG W=90n L=50n m=1
*transmission gate 2
mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1
mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1
.ENDS dlatch
.SUBCKT ms_flop din dout dout_bar clk vdd gnd
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
.ENDS flop

5
technology/scn3me_subm/mag_lib/.magicrc
View File

@ -1,2 +1,5 @@
path sys +$::env(OPENRAM_TECH)/scn3me_subm/tech
tech load SCN3ME_SUBM.30
tech load SCN3ME_SUBM.30 -noprompt
scalegrid 1 4
set GND gnd
set VDD vdd

14
technology/scn3me_subm/mag_lib/convertall.sh Executable file
View File

@ -0,0 +1,14 @@
magic -dnull -noconsole << EOF
load dff
gds write dff.gds
load cell_6t
gds write cell_6t.gds
load replica_cell_6t
gds write replica_cell_6t.gds
load sense_amp
gds write sense_amp.gds
load tri_gate
gds write tri_gate.gds
load write_driver
gds write write_driver.gds
EOF

28
technology/scn3me_subm/sp_lib/dff.sp vendored
View File

@ -1,47 +1,27 @@
*********************** "dff" ******************************
* Positive edge-triggered FF
.subckt dff D Q clk vdd gnd
.SUBCKT dff D Q clk vdd gnd
M0 vdd clk a_2_6# vdd p w=12u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M1 a_17_74# D vdd vdd p w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M9 vdd Q a_76_84# vdd p w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M10 gnd clk a_2_6# gnd n w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M11 Q a_66_6# vdd vdd p w=12u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M12 a_17_6# D gnd gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M20 gnd Q a_76_6# gnd n w=3u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M21 Q a_66_6# gnd gnd n w=6u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
.ends dff
.ENDS dff

99
technology/scn3me_subm/tech/tech.py
View File

@ -50,17 +50,18 @@ layer["blockage"] = 83
###################################################
##DRC/LVS Rules Setup
###################################################
_lambda_ = 0.3
#technology parameter
parameter={}
parameter["min_tx_size"] = 1.2
parameter["min_tx_size"] = 4*_lambda_
parameter["beta"] = 2
drclvs_home=os.environ.get("DRCLVS_HOME")
drc={}
#grid size is 1/2 a lambda
drc["grid"]=0.15
drc["grid"]=0.5*_lambda_
#DRC/LVS test set_up
drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
@ -68,52 +69,52 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
# minwidth_tx with contact (no dog bone transistors)
drc["minwidth_tx"] = 1.2
drc["minlength_channel"] = 0.6
drc["minwidth_tx"] = 4*_lambda_
drc["minlength_channel"] = 2*_lambda_
# 1.3 Minimum spacing between wells of same type (if both are drawn)
drc["well_to_well"] = 1.8
drc["well_to_well"] = 6*_lambda_
# 1.4 Minimum spacing between wells of different type (if both are drawn)
drc["pwell_to_nwell"] = 0
# 1.1 Minimum width
drc["minwidth_well"] = 3.6
drc["minwidth_well"] = 12*_lambda_
# 3.1 Minimum width
drc["minwidth_poly"] = 0.6
drc["minwidth_poly"] = 2*_lambda_
# 3.2 Minimum spacing over active
drc["poly_to_poly"] = 0.9
drc["poly_to_poly"] = 3*_lambda_
# 3.3 Minimum gate extension of active
drc["poly_extend_active"] = 0.6
drc["poly_extend_active"] = 2*_lambda_
# 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
drc["poly_to_polycontact"] = 1.2
drc["poly_to_polycontact"] = 4*_lambda_
# ??
drc["active_enclosure_gate"] = 0.0
# 3.5 Minimum field poly to active
drc["poly_to_active"] = 0.3
drc["poly_to_active"] = _lambda_
# 3.2.a Minimum spacing over field poly
drc["poly_to_field_poly"] = 0.9
drc["poly_to_field_poly"] = 3*_lambda_
# Not a rule
drc["minarea_poly"] = 0.0
# ??
drc["active_to_body_active"] = 1.2 # Fix me
drc["active_to_body_active"] = 4*_lambda_ # Fix me
# 2.1 Minimum width
drc["minwidth_active"] = 0.9
drc["minwidth_active"] = 3*_lambda_
# 2.2 Minimum spacing
drc["active_to_active"] = 0.9
drc["active_to_active"] = 3*_lambda_
# 2.3 Source/drain active to well edge
drc["well_enclosure_active"] = 1.8
drc["well_enclosure_active"] = 6*_lambda_
# Reserved for asymmetric enclosures
drc["well_extend_active"] = 1.8
drc["well_extend_active"] = 6*_lambda_
# Not a rule
drc["minarea_active"] = 0.0
# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
drc["implant_to_channel"] = 0.9
drc["implant_to_channel"] = 3*_lambda_
# 4.2 Minimum select overlap of active
drc["implant_enclosure_active"] = 0.6
drc["implant_enclosure_active"] = 2*_lambda_
# 4.3 Minimum select overlap of contact
drc["implant_enclosure_contact"] = 0.3
drc["implant_enclosure_contact"] = _lambda_
# Not a rule
drc["implant_to_contact"] = 0
# Not a rule
@ -122,70 +123,70 @@ drc["implant_to_implant"] = 0
drc["minwidth_implant"] = 0
# 6.1 Exact contact size
drc["minwidth_contact"] = 0.6
drc["minwidth_contact"] = 2*_lambda_
# 5.3 Minimum contact spacing
drc["contact_to_contact"] = 0.9
drc["contact_to_contact"] = 3*_lambda_
# 6.2.b Minimum active overlap
drc["active_enclosure_contact"] = 0.3
drc["active_enclosure_contact"] = _lambda_
# Reserved for asymmetric enclosure
drc["active_extend_contact"] = 0.3
drc["active_extend_contact"] = _lambda_
# 5.2.b Minimum poly overlap
drc["poly_enclosure_contact"] = 0.3
drc["poly_enclosure_contact"] = _lambda_
# Reserved for asymmetric enclosures
drc["poly_extend_contact"] = 0.3
drc["poly_extend_contact"] = _lambda_
# Reserved for other technologies
drc["contact_to_gate"] = 0.6
drc["contact_to_gate"] = 2*_lambda_
# 5.4 Minimum spacing to gate of transistor
drc["contact_to_poly"] = 0.6
drc["contact_to_poly"] = 2*_lambda_
# 7.1 Minimum width
drc["minwidth_metal1"] = 0.9
drc["minwidth_metal1"] = 3*_lambda_
# 7.2 Minimum spacing
drc["metal1_to_metal1"] = 0.9
drc["metal1_to_metal1"] = 3*_lambda_
# 7.3 Minimum overlap of any contact
drc["metal1_enclosure_contact"] = 0.3
drc["metal1_enclosure_contact"] = _lambda_
# Reserved for asymmetric enclosure
drc["metal1_extend_contact"] = 0.3
drc["metal1_extend_contact"] = _lambda_
# 8.3 Minimum overlap by metal1
drc["metal1_enclosure_via1"] = 0.3
drc["metal1_enclosure_via1"] = _lambda_
# Reserve for asymmetric enclosures
drc["metal1_extend_via1"] = 0.3
drc["metal1_extend_via1"] = _lambda_
# Not a rule
drc["minarea_metal1"] = 0
# 8.1 Exact size
drc["minwidth_via1"] = 0.6
drc["minwidth_via1"] = 2*_lambda_
# 8.2 Minimum via1 spacing
drc["via1_to_via1"] = 0.6
drc["via1_to_via1"] = 3*_lambda_
# 9.1 Minimum width
drc["minwidth_metal2"] = 0.9
drc["minwidth_metal2"] = 3*_lambda_
# 9.2 Minimum spacing
drc["metal2_to_metal2"] = 0.9
drc["metal2_to_metal2"] = 3*_lambda_
# 9.3 Minimum overlap of via1
drc["metal2_extend_via1"] = 0.3
drc["metal2_extend_via1"] = _lambda_
# Reserved for asymmetric enclosures
drc["metal2_enclosure_via1"] = 0.3
drc["metal2_enclosure_via1"] = _lambda_
# 14.3 Minimum overlap by metal2
drc["metal2_extend_via2"] = 0.3
drc["metal2_extend_via2"] = _lambda_
# Reserved for asymmetric enclosures
drc["metal2_enclosure_via2"] = 0.3
drc["metal2_enclosure_via2"] = _lambda_
# Not a rule
drc["minarea_metal2"] = 0
# 14.2 Exact size
drc["minwidth_via2"] = 0.6
# 14.1 Exact size
drc["minwidth_via2"] = 2*_lambda_
# 14.2 Minimum spacing
drc["via2_to_via2"] = 0.9
drc["via2_to_via2"] = 3*_lambda_
# 15.1 Minimum width
drc["minwidth_metal3"] = 1.5
drc["minwidth_metal3"] = 5*_lambda_
# 15.2 Minimum spacing to metal3
drc["metal3_to_metal3"] = 0.9
drc["metal3_to_metal3"] = 3*_lambda_
# 15.3 Minimum overlap of via 2
drc["metal3_extend_via2"] = 0.6
drc["metal3_extend_via2"] = 2*_lambda_
# Reserved for asymmetric enclosures
drc["metal3_enclosure_via2"] = 0.6
drc["metal3_enclosure_via2"] = 2*_lambda_
# Not a rule
drc["minarea_metal3"] = 0

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technology/scn4m_subm/gds_lib/replica_cell_6t.gds Normal file
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technology/scn4m_subm/gds_lib/sense_amp.gds Normal file
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5
technology/scn4m_subm/mag_lib/.magicrc Normal file
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@ -0,0 +1,5 @@
path sys +$::env(OPENRAM_TECH)/scn4m_subm/tech
tech load SCN4M_SUBM.20 -noprompt
scalegrid 1 4
set GND gnd
set VDD vdd

117
technology/scn4m_subm/mag_lib/cell_6t.mag Normal file
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@ -0,0 +1,117 @@
magic
tech scmos
timestamp 1536091415
<< nwell >>
rect -8 29 42 51
<< pwell >>
rect -8 -8 42 29
<< ntransistor >>
rect 7 10 9 18
rect 29 10 31 18
rect 10 3 14 5
rect 24 3 28 5
<< ptransistor >>
rect 7 37 11 40
rect 27 37 31 40
<< ndiffusion >>
rect -2 16 7 18
rect 2 12 7 16
rect -2 10 7 12
rect 9 14 10 18
rect 9 10 14 14
rect 28 14 29 18
rect 24 10 29 14
rect 31 16 36 18
rect 31 12 32 16
rect 31 10 36 12
rect 10 5 14 10
rect 24 5 28 10
rect 10 2 14 3
rect 24 2 28 3
<< pdiffusion >>
rect 2 37 7 40
rect 11 37 12 40
rect 26 37 27 40
rect 31 37 32 40
<< ndcontact >>
rect -2 12 2 16
rect 10 14 14 18
rect 24 14 28 18
rect 32 12 36 16
rect 10 -2 14 2
rect 24 -2 28 2
<< pdcontact >>
rect -2 36 2 40
rect 12 36 16 40
rect 22 36 26 40
rect 32 36 36 40
<< psubstratepcontact >>
rect -2 22 2 26
rect 32 22 36 26
<< nsubstratencontact >>
rect 32 44 36 48
<< polysilicon >>
rect 7 40 11 42
rect 27 40 31 42
rect 7 35 11 37
rect 7 21 9 35
rect 27 34 31 37
rect 15 33 31 34
rect 19 32 31 33
rect 7 20 21 21
rect 7 19 24 20
rect 7 18 9 19
rect 29 18 31 32
rect 7 8 9 10
rect 17 5 21 6
rect 29 8 31 10
rect -2 3 10 5
rect 14 3 24 5
rect 28 3 36 5
<< polycontact >>
rect 15 29 19 33
rect 21 20 25 24
rect 17 6 21 10
<< metal1 >>
rect -2 44 15 48
rect 19 44 32 48
rect -2 40 2 44
rect 32 40 36 44
rect 11 36 12 40
rect 26 36 27 40
rect -2 26 2 29
rect -2 16 2 22
rect 11 18 15 36
rect 23 24 27 36
rect 25 20 27 24
rect 14 14 15 18
rect 23 18 27 20
rect 32 26 36 29
rect 23 14 24 18
rect 32 16 36 22
rect -2 6 17 9
rect 21 6 36 9
rect -2 5 36 6
<< m2contact >>
rect 15 44 19 48
rect -2 29 2 33
rect 32 29 36 33
rect 6 -2 10 2
rect 20 -2 24 2
<< metal2 >>
rect -2 33 2 48
rect -2 -2 2 29
rect 6 2 10 48
rect 24 -2 28 48
rect 32 33 36 48
rect 32 -2 36 29
<< bb >>
rect 0 0 34 46
<< labels >>
rlabel metal2 0 0 0 0 1 gnd
rlabel metal2 34 0 34 0 1 gnd
rlabel m2contact 17 46 17 46 5 vdd
rlabel metal2 8 43 8 43 1 bl
rlabel metal2 26 43 26 43 1 br
rlabel metal1 4 7 4 7 1 wl
<< end >>

14
technology/scn4m_subm/mag_lib/convertall.sh Executable file
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@ -0,0 +1,14 @@
magic -dnull -noconsole << EOF
load dff
gds write dff.gds
load cell_6t
gds write cell_6t.gds
load replica_cell_6t
gds write replica_cell_6t.gds
load sense_amp
gds write sense_amp.gds
load tri_gate
gds write tri_gate.gds
load write_driver
gds write write_driver.gds
EOF

279
technology/scn4m_subm/mag_lib/dff.mag Normal file
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@ -0,0 +1,279 @@
magic
tech scmos
timestamp 1536089597
<< nwell >>
rect 0 48 109 103
<< pwell >>
rect 0 -3 109 48
<< ntransistor >>
rect 11 6 13 26
rect 19 6 21 16
rect 24 6 26 16
rect 33 6 35 16
rect 38 6 40 16
rect 47 6 49 16
rect 63 6 65 16
rect 68 6 70 16
rect 78 6 80 16
rect 83 6 85 16
rect 91 6 93 26
<< ptransistor >>
rect 11 54 13 94
rect 19 74 21 94
rect 25 74 27 94
rect 33 74 35 94
rect 39 74 41 94
rect 47 74 49 94
rect 63 74 65 94
rect 68 74 70 94
rect 78 84 80 94
rect 83 84 85 94
rect 91 54 93 94
<< ndiffusion >>
rect 6 25 11 26
rect 10 6 11 25
rect 13 25 18 26
rect 13 6 14 25
rect 86 25 91 26
rect 18 6 19 16
rect 21 6 24 16
rect 26 15 33 16
rect 26 6 28 15
rect 32 6 33 15
rect 35 6 38 16
rect 40 15 47 16
rect 40 6 41 15
rect 45 6 47 15
rect 49 15 54 16
rect 49 6 50 15
rect 58 15 63 16
rect 62 6 63 15
rect 65 6 68 16
rect 70 15 78 16
rect 70 6 72 15
rect 76 6 78 15
rect 80 6 83 16
rect 85 6 86 16
rect 90 6 91 25
rect 93 25 98 26
rect 93 6 94 25
<< pdiffusion >>
rect 6 93 11 94
rect 10 54 11 93
rect 13 55 14 94
rect 18 74 19 94
rect 21 74 25 94
rect 27 93 33 94
rect 27 74 28 93
rect 32 74 33 93
rect 35 74 39 94
rect 41 93 47 94
rect 41 74 42 93
rect 46 74 47 93
rect 49 93 54 94
rect 49 74 50 93
rect 58 93 63 94
rect 62 74 63 93
rect 65 74 68 94
rect 70 93 78 94
rect 70 74 72 93
rect 76 84 78 93
rect 80 84 83 94
rect 85 93 91 94
rect 85 84 86 93
rect 76 74 77 84
rect 13 54 18 55
rect 90 54 91 93
rect 93 93 98 94
rect 93 54 94 93
<< ndcontact >>
rect 6 6 10 25
rect 14 6 18 25
rect 28 6 32 15
rect 41 6 45 15
rect 50 6 54 15
rect 58 6 62 15
rect 72 6 76 15
rect 86 6 90 25
rect 94 6 98 25
<< pdcontact >>
rect 6 54 10 93
rect 14 55 18 94
rect 28 74 32 93
rect 42 74 46 93
rect 50 74 54 93
rect 58 74 62 93
rect 72 74 76 93
rect 86 54 90 93
rect 94 54 98 93
<< psubstratepcontact >>
rect 102 6 106 10
<< nsubstratencontact >>
rect 102 89 106 93
<< polysilicon >>
rect 11 94 13 96
rect 19 94 21 96
rect 25 94 27 96
rect 33 94 35 96
rect 39 94 41 96
rect 47 94 49 96
rect 63 94 65 96
rect 68 94 70 96
rect 78 94 80 96
rect 83 94 85 96
rect 91 94 93 96
rect 11 37 13 54
rect 19 46 21 74
rect 11 26 13 33
rect 19 16 21 42
rect 25 38 27 74
rect 33 54 35 74
rect 33 29 35 50
rect 24 27 35 29
rect 39 71 41 74
rect 24 16 26 27
rect 39 23 41 67
rect 47 61 49 74
rect 63 73 65 74
rect 54 71 65 73
rect 34 19 35 23
rect 33 16 35 19
rect 38 19 39 23
rect 38 16 40 19
rect 47 16 49 57
rect 53 19 55 67
rect 68 63 70 74
rect 78 67 80 84
rect 76 65 80 67
rect 63 61 70 63
rect 61 24 63 33
rect 68 31 70 61
rect 83 53 85 84
rect 79 51 85 53
rect 78 31 80 47
rect 91 45 93 54
rect 89 41 93 45
rect 68 29 75 31
rect 61 22 70 24
rect 53 17 65 19
rect 63 16 65 17
rect 68 16 70 22
rect 73 19 75 29
rect 78 27 79 31
rect 73 17 80 19
rect 78 16 80 17
rect 83 16 85 31
rect 91 26 93 41
rect 11 4 13 6
rect 19 4 21 6
rect 24 4 26 6
rect 33 4 35 6
rect 38 4 40 6
rect 47 4 49 6
rect 63 4 65 6
rect 68 4 70 6
rect 78 4 80 6
rect 83 4 85 6
rect 91 4 93 6
<< polycontact >>
rect 17 42 21 46
rect 10 33 14 37
rect 31 50 35 54
rect 25 34 29 38
rect 39 67 43 71
rect 45 57 49 61
rect 30 19 34 23
rect 39 19 43 23
rect 53 67 57 71
rect 59 59 63 63
rect 74 61 78 65
rect 59 33 63 37
rect 77 47 81 51
rect 85 41 89 45
rect 79 27 83 31
<< metal1 >>
rect 0 97 109 103
rect 14 94 18 97
rect 6 93 10 94
rect 28 93 32 94
rect 22 74 28 77
rect 42 93 46 97
rect 50 93 54 94
rect 58 93 62 97
rect 71 93 77 94
rect 71 74 72 93
rect 76 74 77 93
rect 86 93 90 97
rect 50 71 53 74
rect 43 68 53 71
rect 26 57 45 60
rect 52 60 59 63
rect 52 54 55 60
rect 71 56 74 65
rect 10 50 31 52
rect 35 51 55 54
rect 62 53 74 56
rect 94 93 98 94
rect 102 93 106 97
rect 6 49 34 50
rect 21 43 38 46
rect 18 34 25 37
rect 62 37 65 53
rect 94 51 98 54
rect 81 48 94 51
rect 74 41 85 44
rect 29 34 59 37
rect 6 25 10 26
rect 14 25 18 26
rect 31 23 34 34
rect 63 34 65 37
rect 94 31 98 47
rect 83 28 98 31
rect 94 25 98 28
rect 43 19 53 22
rect 50 16 53 19
rect 22 15 32 16
rect 22 13 28 15
rect 41 15 46 16
rect 45 6 46 15
rect 50 15 54 16
rect 58 15 62 16
rect 70 15 77 16
rect 70 13 72 15
rect 71 6 72 13
rect 76 6 77 15
rect 14 3 18 6
rect 41 3 46 6
rect 58 3 62 6
rect 86 3 90 6
rect 102 3 106 6
rect 0 -3 109 3
<< m2contact >>
rect 22 70 26 74
rect 70 70 74 74
rect 22 57 26 61
rect 6 50 10 54
rect 38 43 42 47
rect 14 33 18 37
rect 94 47 98 51
rect 70 40 74 44
rect 6 26 10 30
rect 22 16 26 20
rect 70 16 74 20
<< metal2 >>
rect 22 61 26 70
rect 6 30 10 50
rect 22 20 26 57
rect 70 44 74 70
rect 70 20 74 40
<< bb >>
rect 0 0 109 100
<< labels >>
rlabel m2contact 15 34 15 34 4 clk
rlabel m2contact 40 45 40 45 4 D
rlabel m2contact 96 49 96 49 4 Q
rlabel metal1 32 98 32 98 4 vdd
rlabel metal1 44 1 44 1 4 gnd
<< properties >>
string path 0.000 0.000 900.000 0.000 900.000 900.000 0.000 900.000 0.000 0.000
<< end >>

118
technology/scn4m_subm/mag_lib/replica_cell_6t.mag Normal file
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@ -0,0 +1,118 @@
magic
tech scmos
timestamp 1536091380
<< nwell >>
rect -8 29 42 51
<< pwell >>
rect -8 -8 42 29
<< ntransistor >>
rect 7 10 9 18
rect 29 10 31 18
rect 10 3 14 5
rect 24 3 28 5
<< ptransistor >>
rect 7 37 11 40
rect 27 37 31 40
<< ndiffusion >>
rect -2 16 7 18
rect 2 12 7 16
rect -2 10 7 12
rect 9 14 10 18
rect 9 10 14 14
rect 28 14 29 18
rect 24 10 29 14
rect 31 16 36 18
rect 31 12 32 16
rect 31 10 36 12
rect 10 5 14 10
rect 24 5 28 10
rect 10 2 14 3
rect 24 2 28 3
<< pdiffusion >>
rect 2 37 7 40
rect 11 37 12 40
rect 26 37 27 40
rect 31 37 32 40
<< ndcontact >>
rect -2 12 2 16
rect 10 14 14 18
rect 24 14 28 18
rect 32 12 36 16
rect 10 -2 14 2
rect 24 -2 28 2
<< pdcontact >>
rect -2 36 2 40
rect 12 36 16 40
rect 22 36 26 40
rect 32 36 36 40
<< psubstratepcontact >>
rect -2 22 2 26
rect 32 22 36 26
<< nsubstratencontact >>
rect 32 44 36 48
<< polysilicon >>
rect 7 40 11 42
rect 27 40 31 42
rect 7 35 11 37
rect 7 21 9 35
rect 27 34 31 37
rect 15 33 31 34
rect 19 32 31 33
rect 7 20 21 21
rect 7 19 24 20
rect 7 18 9 19
rect 29 18 31 32
rect 7 8 9 10
rect 17 5 21 6
rect 29 8 31 10
rect -2 3 10 5
rect 14 3 24 5
rect 28 3 36 5
<< polycontact >>
rect 15 29 19 33
rect 21 20 25 24
rect 17 6 21 10
<< metal1 >>
rect -2 44 15 48
rect 19 44 32 48
rect -2 40 2 44
rect 32 40 36 44
rect 11 36 12 40
rect 26 36 27 40
rect -2 26 2 29
rect 11 22 15 36
rect 23 24 27 36
rect -2 18 15 22
rect 25 20 27 24
rect -2 16 2 18
rect 14 14 15 18
rect 23 18 27 20
rect 32 26 36 29
rect 23 14 24 18
rect 32 16 36 22
rect -2 6 17 9
rect 21 6 36 9
rect -2 5 36 6
<< m2contact >>
rect 15 44 19 48
rect -2 29 2 33
rect 32 29 36 33
rect 6 -2 10 2
rect 20 -2 24 2
<< metal2 >>
rect -2 33 2 48
rect -2 -2 2 29
rect 6 2 10 48
rect 24 -2 28 48
rect 32 33 36 48
rect 32 -2 36 29
<< bb >>
rect 0 0 34 46
<< labels >>
rlabel metal2 0 0 0 0 1 gnd
rlabel metal2 34 0 34 0 1 gnd
rlabel m2contact 17 46 17 46 5 vdd
rlabel metal2 8 43 8 43 1 bl
rlabel metal2 26 43 26 43 1 br
rlabel metal1 4 7 4 7 1 wl
<< end >>

136
technology/scn4m_subm/mag_lib/sense_amp.mag Normal file
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@ -0,0 +1,136 @@
magic
tech scmos
timestamp 1536089670
<< nwell >>
rect 0 0 40 102
<< pwell >>
rect 0 102 40 163
<< ntransistor >>
rect 21 130 23 139
rect 12 108 14 117
rect 20 108 22 117
<< ptransistor >>
rect 12 78 14 96
rect 20 78 22 96
rect 11 20 13 44
rect 27 20 29 44
<< ndiffusion >>
rect 20 130 21 139
rect 23 130 24 139
rect 11 108 12 117
rect 14 108 15 117
rect 19 108 20 117
rect 22 108 23 117
<< pdiffusion >>
rect 7 94 12 96
rect 11 80 12 94
rect 7 78 12 80
rect 14 94 20 96
rect 14 80 15 94
rect 19 80 20 94
rect 14 78 20 80
rect 22 94 27 96
rect 22 80 23 94
rect 22 78 27 80
rect 10 20 11 44
rect 13 20 14 44
rect 26 20 27 44
rect 29 20 30 44
<< ndcontact >>
rect 16 130 20 139
rect 24 130 28 139
rect 7 108 11 117
rect 15 108 19 117
rect 23 108 27 117
<< pdcontact >>
rect 7 80 11 94
rect 15 80 19 94
rect 23 80 27 94
rect 6 20 10 44
rect 14 20 18 44
rect 22 20 26 44
rect 30 20 34 44
<< psubstratepcontact >>
rect 32 137 36 141
<< nsubstratencontact >>
rect 27 70 31 74
<< polysilicon >>
rect 21 139 23 149
rect 21 129 23 130
rect 3 127 23 129
rect 3 47 5 127
rect 12 122 34 124
rect 12 117 14 122
rect 20 117 22 119
rect 12 96 14 108
rect 20 96 22 108
rect 32 105 34 122
rect 30 101 34 105
rect 12 76 14 78
rect 20 69 22 78
rect 13 67 22 69
rect 9 55 11 65
rect 32 55 34 101
rect 33 51 34 55
rect 3 45 13 47
rect 11 44 13 45
rect 27 44 29 46
rect 11 19 13 20
rect 27 19 29 20
rect 11 17 29 19
<< polycontact >>
rect 20 149 24 153
rect 26 101 30 105
rect 9 65 13 69
rect 9 51 13 55
rect 29 51 33 55
<< metal1 >>
rect -2 149 20 153
rect 24 149 36 153
rect 28 133 32 137
rect 16 117 19 130
rect 7 94 11 108
rect 23 105 27 108
rect 23 101 26 105
rect 7 69 11 80
rect 15 94 19 96
rect 15 78 19 80
rect 23 94 27 101
rect 23 78 27 80
rect 15 75 18 78
rect 15 74 31 75
rect 15 72 27 74
rect 7 65 9 69
rect 6 44 9 54
rect 33 51 34 55
rect 31 44 34 51
rect 3 20 6 23
rect 3 15 7 20
<< m2contact >>
rect 32 133 36 137
rect 27 66 31 70
rect 13 44 17 48
rect 22 44 26 48
rect 3 11 7 15
<< metal2 >>
rect 10 48 14 163
rect 20 48 24 163
rect 32 129 36 133
rect 27 62 31 66
rect 10 44 13 48
rect 20 44 22 48
rect 3 0 7 11
rect 10 0 14 44
rect 20 0 24 44
<< bb >>
rect 0 0 34 163
<< labels >>
flabel metal1 0 149 0 149 4 FreeSans 26 0 0 0 en
rlabel metal2 34 131 34 131 1 gnd
rlabel metal2 29 64 29 64 1 vdd
rlabel metal2 12 161 12 161 5 bl
rlabel metal2 22 161 22 161 5 br
rlabel metal2 5 3 5 3 1 dout
<< properties >>
string path 270.000 468.000 270.000 486.000 288.000 486.000 288.000 468.000 270.000 468.000
<< end >>

98
technology/scn4m_subm/mag_lib/tri_gate.mag Normal file
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@ -0,0 +1,98 @@
magic
tech scmos
timestamp 1536089695
<< nwell >>
rect -2 45 38 73
<< pwell >>
rect -2 0 38 45
<< ntransistor >>
rect 9 27 11 31
rect 17 27 19 31
rect 25 27 27 31
<< ptransistor >>
rect 9 53 11 61
rect 17 53 19 61
rect 25 53 27 61
<< ndiffusion >>
rect 8 27 9 31
rect 11 27 12 31
rect 16 27 17 31
rect 19 27 20 31
rect 24 27 25 31
rect 27 27 28 31
<< pdiffusion >>
rect 8 53 9 61
rect 11 53 12 61
rect 16 53 17 61
rect 19 53 20 61
rect 24 53 25 61
rect 27 53 28 61
<< ndcontact >>
rect 4 27 8 31
rect 12 27 16 31
rect 20 27 24 31
rect 28 27 32 31
<< pdcontact >>
rect 4 53 8 61
rect 12 53 16 61
rect 20 53 24 61
rect 28 53 32 61
<< psubstratepcontact >>
rect 12 19 16 23
<< nsubstratencontact >>
rect 12 65 16 69
<< polysilicon >>
rect 25 63 35 65
rect 9 61 11 63
rect 17 61 19 63
rect 25 61 27 63
rect 9 50 11 53
rect 9 31 11 46
rect 17 42 19 53
rect 25 51 27 53
rect 17 31 19 38
rect 25 31 27 33
rect 9 25 11 27
rect 17 25 19 27
rect 25 16 27 27
rect 33 8 35 63
rect 32 6 35 8
<< polycontact >>
rect 9 46 13 50
rect 16 38 20 42
rect 25 12 29 16
rect 28 4 32 8
<< metal1 >>
rect 16 65 23 69
rect 12 61 16 65
rect 3 53 4 61
rect 3 42 6 53
rect 13 46 15 50
rect 3 38 16 42
rect 3 31 6 38
rect 29 31 32 53
rect 3 27 4 31
rect 12 23 16 27
rect 16 19 24 23
rect 0 12 25 16
rect 29 12 36 16
rect 0 4 28 8
rect 32 4 36 8
<< m2contact >>
rect 23 65 27 69
rect 15 46 19 50
rect 25 34 29 38
rect 24 19 28 23
<< metal2 >>
rect 15 34 25 38
rect 15 0 19 34
<< bb >>
rect 0 0 34 73
<< labels >>
rlabel metal1 0 12 0 12 3 en
rlabel metal1 0 4 0 4 2 en_bar
rlabel metal2 16 1 16 1 1 out
rlabel m2contact 26 21 26 21 1 gnd
rlabel m2contact 25 67 25 67 1 vdd
rlabel m2contact 17 48 17 48 1 in
<< end >>

224
technology/scn4m_subm/mag_lib/write_driver.mag Normal file
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magic
tech scmos
timestamp 1536089714
<< nwell >>
rect -3 101 37 138
rect -3 0 37 51
<< pwell >>
rect -3 138 37 202
rect -3 51 37 101
<< ntransistor >>
rect 9 177 11 189
rect 17 177 19 189
rect 15 162 27 164
rect 9 144 11 148
rect 17 144 19 148
rect 10 82 12 89
rect 18 82 20 89
rect 8 57 10 64
rect 16 57 18 64
rect 24 60 26 64
<< ptransistor >>
rect 9 125 11 132
rect 17 125 19 132
rect 10 107 12 114
rect 18 107 20 114
rect 8 38 10 45
rect 16 38 18 45
rect 24 38 26 45
<< ndiffusion >>
rect 8 177 9 189
rect 11 177 12 189
rect 16 177 17 189
rect 19 177 20 189
rect 15 164 27 165
rect 15 161 27 162
rect 12 157 15 160
rect 12 156 16 157
rect 8 144 9 148
rect 11 144 12 148
rect 16 144 17 148
rect 19 144 20 148
rect 9 82 10 89
rect 12 82 13 89
rect 17 82 18 89
rect 20 82 21 89
rect 25 82 26 86
rect 7 57 8 64
rect 10 57 11 64
rect 15 57 16 64
rect 18 57 19 64
rect 23 60 24 64
rect 26 60 27 64
<< pdiffusion >>
rect 8 125 9 132
rect 11 125 12 132
rect 16 125 17 132
rect 19 125 20 132
rect 12 122 16 125
rect 9 107 10 114
rect 12 107 13 114
rect 17 107 18 114
rect 20 107 21 114
rect 7 38 8 45
rect 10 38 11 45
rect 15 38 16 45
rect 18 38 19 45
rect 23 38 24 45
rect 26 38 27 45
rect 3 35 7 38
<< ndcontact >>
rect 4 177 8 189
rect 12 177 16 189
rect 20 177 24 189
rect 15 165 27 169
rect 15 157 27 161
rect 4 144 8 148
rect 12 144 16 148
rect 20 144 24 148
rect 5 82 9 89
rect 13 82 17 89
rect 21 82 25 89
rect 3 57 7 64
rect 11 57 15 64
rect 19 57 23 64
rect 27 60 31 64
<< pdcontact >>
rect 4 125 8 132
rect 12 125 16 132
rect 20 125 24 132
rect 5 107 9 114
rect 13 107 17 114
rect 21 107 25 114
rect 3 38 7 45
rect 11 38 15 45
rect 19 38 23 45
rect 27 38 31 45
<< psubstratepcontact >>
rect 12 152 16 156
rect 26 82 30 86
<< nsubstratencontact >>
rect 12 118 16 122
rect 3 31 7 35
<< polysilicon >>
rect 9 194 30 196
rect 9 189 11 194
rect 17 189 19 191
rect 28 185 30 194
rect 9 175 11 177
rect 17 172 19 177
rect 6 170 19 172
rect 6 167 8 170
rect 13 162 15 164
rect 27 162 33 164
rect 9 148 11 150
rect 17 148 19 150
rect 9 132 11 144
rect 17 132 19 144
rect 9 124 11 125
rect 2 122 11 124
rect 17 124 19 125
rect 17 122 28 124
rect 2 75 4 122
rect 10 114 12 116
rect 18 114 20 116
rect 10 89 12 107
rect 18 106 20 107
rect 16 104 20 106
rect 16 92 18 104
rect 26 100 28 122
rect 27 96 28 100
rect 16 90 20 92
rect 18 89 20 90
rect 10 81 12 82
rect 10 79 13 81
rect 2 71 3 75
rect 11 71 13 79
rect 18 79 20 82
rect 18 77 23 79
rect 31 71 33 162
rect 11 69 33 71
rect 11 67 13 69
rect 8 65 13 67
rect 8 64 10 65
rect 16 64 18 66
rect 24 64 26 66
rect 8 45 10 57
rect 16 52 18 57
rect 24 52 26 60
rect 16 50 26 52
rect 16 45 18 50
rect 24 45 26 50
rect 8 28 10 38
rect 16 14 18 38
rect 24 36 26 38
<< polycontact >>
rect 28 181 32 185
rect 4 163 8 167
rect 23 96 27 100
rect 3 71 7 75
rect 23 75 27 79
rect 7 24 11 28
rect 15 10 19 14
<< metal1 >>
rect 5 192 10 196
rect 5 189 8 192
rect 32 181 33 185
rect 13 169 16 177
rect 13 165 15 169
rect 4 148 8 163
rect 12 157 15 161
rect 12 156 16 157
rect 12 148 16 152
rect 4 132 8 144
rect 20 142 24 144
rect 30 142 33 181
rect 20 138 33 142
rect 20 132 24 138
rect 12 122 16 125
rect 13 114 17 118
rect 5 104 9 107
rect 21 104 25 107
rect 5 101 25 104
rect 5 89 9 101
rect 21 100 25 101
rect 21 96 23 100
rect 25 82 26 90
rect 4 64 7 71
rect 27 64 31 79
rect 3 51 7 57
rect 3 48 15 51
rect 11 45 15 48
rect 27 45 31 60
rect 3 35 7 38
rect 19 35 23 38
rect 7 31 19 35
rect 0 24 7 28
rect 11 24 36 28
<< m2contact >>
rect 10 192 14 196
rect 20 189 24 193
rect 23 153 27 157
rect 16 118 20 122
rect 26 86 30 90
rect 19 64 23 68
rect 19 31 23 35
rect 15 6 19 10
<< metal2 >>
rect 10 196 14 202
rect 20 193 24 202
rect 20 177 24 189
rect 15 0 19 6
<< bb >>
rect 0 0 34 202
<< labels >>
rlabel metal2 15 1 15 1 1 din
rlabel metal1 2 25 2 25 3 en
rlabel metal2 12 200 12 200 5 bl
rlabel metal2 22 200 22 200 5 br
rlabel m2contact 21 66 21 66 1 gnd
rlabel m2contact 28 88 28 88 1 gnd
rlabel m2contact 21 33 21 33 1 vdd
rlabel m2contact 18 120 18 120 1 vdd
rlabel m2contact 25 155 25 155 1 gnd
<< end >>

10
technology/scn4m_subm/models/ff/nmos.sp vendored Normal file
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@ -0,0 +1,10 @@
*********************************************
* Transistor Models
* Note: These models are approximate
* and should be substituted with actual
* models from MOSIS or SCN4ME
*********************************************
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
+ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0)

9
technology/scn4m_subm/models/ff/pmos.sp vendored Normal file
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@ -0,0 +1,9 @@
*********************************************
* Transistor Models
* Note: These models are approximate
* and should be substituted with actual
* models from MOSIS or SCN4ME
*********************************************
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)

9
technology/scn4m_subm/models/nom/nmos.sp vendored Normal file
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@ -0,0 +1,9 @@
*********************************************
* Transistor Models
* Note: These models are approximate
* and should be substituted with actual
* models from MOSIS or SCN4ME
*********************************************
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
+ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0)

9
technology/scn4m_subm/models/nom/pmos.sp vendored Normal file
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@ -0,0 +1,9 @@
*********************************************
* Transistor Models
* Note: These models are approximate
* and should be substituted with actual
* models from MOSIS or SCN4ME
*********************************************
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)

10
technology/scn4m_subm/models/ss/nmos.sp vendored Normal file
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@ -0,0 +1,10 @@
*********************************************
* Transistor Models
* Note: These models are approximate
* and should be substituted with actual
* models from MOSIS or SCN4ME
*********************************************
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
+ NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0)

9
technology/scn4m_subm/models/ss/pmos.sp vendored Normal file
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@ -0,0 +1,9 @@
*********************************************
* Transistor Models
* Note: These models are approximate
* and should be substituted with actual
* models from MOSIS or SCN4ME
*********************************************
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)

13
technology/scn4m_subm/sp_lib/cell_6t.sp vendored Normal file
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*********************** "cell_6t" ******************************
.SUBCKT cell_6t bl br wl vdd gnd
* SPICE3 file created from cell_6t.ext - technology: scmos
M1000 a_36_40# a_28_32# vdd vdd p w=0.6u l=0.8u
M1001 vdd a_36_40# a_28_32# vdd p w=0.6u l=0.8u
M1002 a_36_40# a_28_32# gnd gnd n w=1.6u l=0.4u
M1003 gnd a_36_40# a_28_32# gnd n w=1.6u l=0.4u
M1004 a_36_40# wl bl gnd n w=0.8u l=0.4u
M1005 a_28_32# wl br gnd n w=0.8u l=0.4u
.ENDS

30
technology/scn4m_subm/sp_lib/dff.sp vendored Normal file
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@ -0,0 +1,30 @@
*********************** "dff" ******************************
* Positive edge-triggered FF
.SUBCKT dff D Q clk vdd gnd
* SPICE3 file created from dff.ext - technology: scmos
M1000 vdd clk a_24_24# vdd p w=8u l=0.4u
M1001 a_84_296# D vdd vdd p w=4u l=0.4u
M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u
M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u
M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u
M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u
M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u
M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u
M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u
M1009 vdd Q a_320_336# vdd p w=2u l=0.4u
M1010 gnd clk a_24_24# gnd n w=4u l=0.4u
M1011 Q a_280_24# vdd vdd p w=8u l=0.4u
M1012 a_84_24# D gnd gnd n w=2u l=0.4u
M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u
M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u
M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u
M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u
M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u
M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u
M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u
M1020 gnd Q a_320_24# gnd n w=2u l=0.4u
M1021 Q a_280_24# gnd gnd n w=4u l=0.4u
.ENDS

14
technology/scn4m_subm/sp_lib/replica_cell_6t.sp vendored Normal file
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@ -0,0 +1,14 @@
*********************** "cell_6t" ******************************
.SUBCKT replica_cell_6t bl br wl vdd gnd
* SPICE3 file created from replica_cell_6t.ext - technology: scmos
M1000 gnd a_28_32# vdd vdd p w=0.6u l=0.8u
M1001 vdd gnd a_28_32# vdd p w=0.6u l=0.8u
** SOURCE/DRAIN TIED
M1002 gnd a_28_32# gnd gnd n w=1.6u l=0.4u
M1003 gnd gnd a_28_32# gnd n w=1.6u l=0.4u
M1004 gnd wl bl gnd n w=0.8u l=0.4u
M1005 a_28_32# wl br gnd n w=0.8u l=0.4u
.ENDS

15
technology/scn4m_subm/sp_lib/sense_amp.sp vendored Normal file
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@ -0,0 +1,15 @@
*********************** "sense_amp" ******************************
.SUBCKT sense_amp bl br dout en vdd gnd
* SPICE3 file created from sense_amp.ext - technology: scmos
M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u
M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u
M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u
M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u
M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u
M1005 bl en dout vdd p w=4.8u l=0.4u
M1006 a_48_304# en br vdd p w=4.8u l=0.4u
.ENDS

14
technology/scn4m_subm/sp_lib/tri_gate.sp vendored Normal file
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@ -0,0 +1,14 @@
*********************** tri_gate ******************************
.SUBCKT tri_gate in out en en_bar vdd gnd
* SPICE3 file created from tri_gate.ext - technology: scmos
M1000 vdd in a_16_108# vdd p w=1.6u l=0.4u
M1001 a_76_212# a_16_108# vdd vdd p w=1.6u l=0.4u
M1002 out en_bar a_76_212# vdd p w=1.6u l=0.4u
M1003 gnd in a_16_108# gnd n w=0.8u l=0.4u
M1004 a_76_108# a_16_108# gnd gnd n w=0.8u l=0.4u
M1005 out en a_76_108# gnd n w=0.8u l=0.4u
.ENDS

23
technology/scn4m_subm/sp_lib/write_driver.sp vendored Normal file
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@ -0,0 +1,23 @@
*********************** Write_Driver ******************************
.SUBCKT write_driver din bl br en vdd gnd
* SPICE3 file created from write_driver.ext - technology: scmos
M1000 a_44_708# a_36_700# bl gnd n w=2.4u l=0.4u
M1001 br a_16_500# a_44_708# gnd n w=2.4u l=0.4u
M1002 a_44_708# en gnd gnd n w=2.4u l=0.4u
M1003 gnd a_8_284# a_16_500# gnd n w=0.8u l=0.4u
M1004 a_36_700# a_20_328# gnd gnd n w=0.8u l=0.4u
M1005 vdd a_8_284# a_16_500# vdd p w=1.4u l=0.4u
M1006 a_36_700# a_20_328# vdd vdd p w=1.4u l=0.4u
M1007 vdd en a_20_328# vdd p w=1.4u l=0.4u
M1008 a_20_328# a_64_360# vdd vdd p w=1.4u l=0.4u
M1009 a_48_328# en a_20_328# gnd n w=1.4u l=0.4u
M1010 gnd a_64_360# a_48_328# gnd n w=1.4u l=0.4u
M1011 a_40_228# en a_8_284# gnd n w=1.4u l=0.4u
M1012 gnd din a_40_228# gnd n w=1.4u l=0.4u
M1013 a_64_360# din gnd gnd n w=0.8u l=0.4u
M1014 a_8_284# en vdd vdd p w=1.4u l=0.4u
M1015 vdd din a_8_284# vdd p w=1.4u l=0.4u
M1016 a_64_360# din vdd vdd p w=1.4u l=0.4u
.ENDS

46
technology/scn4m_subm/sue_lib/cell_6t.sue Normal file
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# SUE version MMI_SUE5.0.7
proc SCHEMATIC_cell_6t {} {
make inout -name BL -origin {190 360}
make inout -name BR -origin {830 360}
make input -name WL -origin {240 120}
make global -orient RXY -name vdd -origin {520 160}
make global -name gnd -origin {510 600}
make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230}
make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230}
make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360}
make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360}
make nmos -W 2.4u -L 0.6u -origin {630 490}
make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490}
make_wire 630 550 630 530
make_wire 400 530 400 550
make_wire 400 190 400 170
make_wire 630 170 630 190
make_wire 400 360 400 270
make_wire 310 360 400 360
make_wire 630 360 630 450
make_wire 630 360 700 360
make_wire 270 300 270 120
make_wire 270 120 740 120
make_wire 740 120 740 300
make_wire 230 360 190 360
make_wire 780 360 830 360
make_wire 510 550 400 550
make_wire 510 550 630 550
make_wire 510 550 510 600
make_wire 520 170 400 170
make_wire 520 170 630 170
make_wire 520 160 520 170
make_wire 240 120 270 120
make_wire 460 290 630 290
make_wire 460 290 460 490
make_wire 460 290 460 230
make_wire 630 290 630 360
make_wire 630 290 630 270
make_wire 570 420 400 420
make_wire 570 420 570 490
make_wire 570 420 570 230
make_wire 400 420 400 360
make_wire 400 420 400 450
}

84
technology/scn4m_subm/sue_lib/ms_flop.sue Normal file
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# SUE version MMI_SUE5.0.7
proc SCHEMATIC_ms_flop {} {
make pmos -orient R90X -W 1.8u -L 0.6u -origin {40 250}
make nmos -orient R270 -W 0.9u -L 0.6u -origin {40 380}
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {-270 540}
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {310 310}
make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {430 730}
make pmos -orient R90X -W 1.8u -L 0.6u -origin {190 670}
make nmos -orient R270 -W 0.9u -L 0.6u -origin {190 780}
make input -name clk -origin {-380 540}
make input -name din -origin {-370 320}
make pmos -orient R90X -W 1.8u -L 0.6u -origin {720 250}
make nmos -orient R270 -W 0.9u -L 0.6u -origin {720 380}
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {990 310}
make pmos -orient R90X -W 1.8u -L 0.6u -origin {870 670}
make nmos -orient R270 -W 0.9u -L 0.6u -origin {870 780}
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {620 540}
make output -name dout -origin {1410 310}
make output -name dout_bar -origin {1430 930}
make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {1110 730}
make_wire -330 160 40 160
make_wire 40 160 40 190
make_wire -370 320 0 320
make_wire 360 310 480 310
make_wire 460 730 480 730
make_wire 230 730 380 730
make_wire 100 310 100 720
make_wire 100 720 150 720
make_wire 100 310 80 310
make_wire 100 310 280 310
make_wire 0 250 0 320
make_wire 0 320 0 380
make_wire 80 250 80 310
make_wire 80 310 80 380
make_wire 40 440 40 540
make_wire -330 840 190 840
make_wire 230 670 230 730
make_wire 230 730 230 780
make_wire 150 670 150 720
make_wire 150 720 150 780
make_wire 190 540 190 610
make_wire -330 540 -330 840
make_wire -220 540 40 540
make_wire 40 540 190 540
make_wire -380 540 -330 540
make_wire -330 540 -300 540
make_wire -330 540 -330 160
make_wire 720 160 720 190
make_wire 1140 730 1160 730
make_wire 780 310 780 720
make_wire 780 720 830 720
make_wire 780 310 760 310
make_wire 780 310 960 310
make_wire 680 320 680 380
make_wire 760 250 760 310
make_wire 760 310 760 380
make_wire 720 440 720 540
make_wire 910 670 910 730
make_wire 910 730 910 780
make_wire 830 670 830 720
make_wire 830 720 830 780
make_wire 870 540 870 610
make_wire 720 540 870 540
make_wire 670 540 720 540
make_wire 480 310 480 730
make_wire 1160 310 1160 730
make_wire 530 540 530 160
make_wire 530 160 720 160
make_wire 530 540 190 540
make_wire 530 540 590 540
make_wire 530 540 530 840
make_wire 530 840 870 840
make_wire 680 310 480 310
make_wire 680 310 680 250
make_wire 680 310 680 320
make_wire 950 730 910 730
make_wire 950 730 1060 730
make_wire 1040 310 1160 310
make_wire 1160 310 1410 310
make_wire 950 930 1430 930
make_wire 950 730 950 930
}

49
technology/scn4m_subm/sue_lib/replica_cell_6t.sue Normal file
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# SUE version MMI_SUE5.0.7
proc SCHEMATIC_replica_cell_6t {} {
make inout -name BL -origin {190 360}
make inout -name BR -origin {830 360}
make input -name WL -origin {240 120}
make global -orient RXY -name vdd -origin {520 160}
make global -name gnd -origin {510 600}
make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230}
make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230}
make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360}
make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360}
make nmos -W 2.4u -L 0.6u -origin {630 490}
make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490}
make_wire 630 550 630 530
make_wire 400 530 400 550
make_wire 400 190 400 170
make_wire 630 170 630 190
make_wire 400 360 400 270
make_wire 630 360 630 450
make_wire 630 360 700 360
make_wire 270 300 270 120
make_wire 270 120 740 120
make_wire 740 120 740 300
make_wire 230 360 190 360
make_wire 780 360 830 360
make_wire 510 550 400 550
make_wire 510 550 630 550
make_wire 510 550 510 600
make_wire 520 170 400 170
make_wire 520 170 630 170
make_wire 520 160 520 170
make_wire 240 120 270 120
make_wire 460 290 630 290
make_wire 460 290 460 490
make_wire 460 290 460 230
make_wire 630 290 630 360
make_wire 630 290 630 270
make_wire 570 420 400 420
make_wire 570 420 570 490
make_wire 570 420 570 230
make_wire 400 420 400 360
make_wire 400 420 400 450
make_wire 320 360 320 550
make_wire 320 550 400 550
make_wire 320 360 310 360
make_wire 320 360 400 360
}

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# SUE version MMI_SUE5.0.7
proc SCHEMATIC_sense_amp {} {
make inout -name BL -origin {260 10}
make global -orient RXY -name vdd -origin {490 170}
make global -name gnd -origin {480 660}
make input -name sclk -origin {180 610}
make nmos -W 3.9u -L 0.6u -origin {600 500}
make nmos -orient RX -W 3.9u -L 0.6u -origin {370 500}
make pmos -orient RY -W 3u -L 0.6u -origin {600 240}
make pmos -orient RXY -W 3u -L 0.6u -origin {370 240}
make nmos -W 3.9u -L 0.6u -origin {480 610}
make inout -name BR -origin {710 20}
make pmos -W 3.9u -L 0.6u -origin {710 90}
make pmos -orient RX -W 3.9u -L 0.6u -origin {260 90}
make output -orient RXY -name dout -origin {110 370}
make_wire 600 560 600 540
make_wire 370 540 370 560
make_wire 370 200 370 180
make_wire 600 180 600 200
make_wire 490 180 370 180
make_wire 490 180 600 180
make_wire 490 170 490 180
make_wire 430 300 600 300
make_wire 430 300 430 500
make_wire 430 300 430 240
make_wire 600 300 600 280
make_wire 540 430 370 430
make_wire 540 430 540 500
make_wire 540 430 540 240
make_wire 370 430 370 460
make_wire 480 560 600 560
make_wire 480 560 370 560
make_wire 480 560 480 570
make_wire 480 650 480 660
make_wire 420 610 180 610
make_wire 650 90 320 90
make_wire 600 360 710 360
make_wire 710 360 710 130
make_wire 600 360 600 300
make_wire 600 360 600 460
make_wire 370 370 260 370
make_wire 260 370 260 130
make_wire 370 370 370 430
make_wire 370 370 370 280
make_wire 260 10 260 50
make_wire 710 20 710 50
make_wire 320 90 180 90
make_wire 180 90 180 610
make_wire 110 370 260 370
}

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# SUE version MMI_SUE5.0.7
proc SCHEMATIC_tri_gate {} {
make global -orient RXY -name vdd -origin {630 150}
make global -name gnd -origin {630 570}
make input -name tri_in -origin {320 340}
make output -name tri_out -origin {690 360}
make input -name en -origin {570 410}
make input -name en_bar -origin {570 310}
make nmos -W 1.2u -L 0.6u -origin {630 490}
make nmos -W 1.2u -L 0.6u -origin {630 410}
make pmos -orient RY -W 2.4u -L 0.6u -origin {630 310}
make pmos -orient RY -W 2.4u -L 0.6u -origin {630 230}
make pmos -orient RY -W 2.4u -L 0.6u -origin {380 290}
make nmos -W 1.2u -L 0.6u -origin {380 400}
make_wire 570 490 470 490
make_wire 470 230 570 230
make_wire 630 550 380 550
make_wire 380 550 380 440
make_wire 630 550 630 570
make_wire 630 550 630 530
make_wire 630 170 380 170
make_wire 380 170 380 250
make_wire 630 170 630 190
make_wire 630 170 630 150
make_wire 320 340 320 400
make_wire 320 340 320 290
make_wire 380 340 470 340
make_wire 380 340 380 330
make_wire 380 340 380 360
make_wire 470 340 470 490
make_wire 470 340 470 230
make_wire 630 360 630 350
make_wire 630 360 630 370
make_wire 630 360 690 360
}

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# SUE version MMI_SUE5.0.7
proc SCHEMATIC_write_driver {} {
make inout -name BL -origin {550 260}
make inout -name BR -origin {830 250}
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {280 520}
make nand2 -WP 2.1u -WN 2.1u -origin {90 360}
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {270 360}
make nmos -W 3.6u -L 0.6u -origin {830 410}
make nmos -W 3.6u -L 0.6u -origin {710 610}
make global -name gnd -origin {710 690}
make nand2 -WP 2.1u -WN 2.1u -origin {90 520}
make nmos -W 3.6u -L 0.6u -origin {550 410}
make input -name wen -origin {-290 340}
make input -name din -origin {-290 380}
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {-80 540}
make_wire 160 360 240 360
make_wire 830 250 830 370
make_wire 550 260 550 370
make_wire 550 450 550 560
make_wire 550 560 710 560
make_wire 710 560 710 570
make_wire 710 560 830 560
make_wire 830 560 830 450
make_wire 710 650 710 690
make_wire 250 520 160 520
make_wire 770 410 770 520
make_wire 770 520 330 520
make_wire 320 360 490 360
make_wire 490 360 490 410
make_wire -180 380 -290 380
make_wire -180 380 70 380
make_wire -180 540 -110 540
make_wire -180 380 -180 540
make_wire -30 540 70 540
make_wire 20 340 20 500
make_wire 20 500 70 500
make_wire 20 340 70 340
make_wire -240 340 -240 610
make_wire -240 610 650 610
make_wire -240 340 20 340
make_wire -240 340 -290 340
}

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The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following
license information:
---------------------------------------------------------------
Tim Edwards
Open Circuit Design
v1.0 April 2013
v1.1 May 2015
v1.2 April 2017
---------------------------------------------------------------
GPL Copyright (c) 2017

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technology/scn4m_subm/tech/SCN4M_SUBM.20.tech Normal file
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technology/scn4m_subm/tech/__init__.py Executable file
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"""
Import tech specific modules.
"""
from tech import *

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import os
"""
File containing the process technology parameters for SCMOS 3me, subm, 180nm.
"""
info={}
info["name"]="scn3me_subm"
info["body_tie_down"] = 0
info["has_pwell"] = True
info["has_nwell"] = True
#GDS file info
GDS={}
# gds units
GDS["unit"]=(0.001,1e-6)
# default label zoom
GDS["zoom"] = 0.5
###################################################
##GDS Layer Map
###################################################
# create the GDS layer map
layer={}
layer["vtg"] = -1
layer["vth"] = -1
layer["contact"] = 47
layer["pwell"] = 41
layer["nwell"] = 42
layer["active"] = 43
layer["pimplant"] = 44
layer["nimplant"] = 45
layer["poly"] = 46
layer["active_contact"] = 48
layer["metal1"] = 49
layer["via1"] = 50
layer["metal2"] = 51
layer["via2"] = 61
layer["metal3"] = 62
layer["via3"] = 30
layer["metal4"] = 31
layer["text"] = 63
layer["boundary"] = 63
layer["blockage"] = 83
###################################################
##END GDS Layer Map
###################################################
###################################################
##DRC/LVS Rules Setup
###################################################
_lambda_ = 0.2
#technology parameter
parameter={}
parameter["min_tx_size"] = 4*_lambda_
parameter["beta"] = 2
drclvs_home=os.environ.get("DRCLVS_HOME")
drc={}
#grid size is 1/2 a lambda
drc["grid"]=0.5*_lambda_
#DRC/LVS test set_up
drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
# minwidth_tx with contact (no dog bone transistors)
drc["minwidth_tx"] = 4*_lambda_
drc["minlength_channel"] = 2*_lambda_
# 1.3 Minimum spacing between wells of same type (if both are drawn)
drc["well_to_well"] = 6*_lambda_
# 1.4 Minimum spacing between wells of different type (if both are drawn)
drc["pwell_to_nwell"] = 0
# 1.1 Minimum width
drc["minwidth_well"] = 12*_lambda_
# 3.1 Minimum width
drc["minwidth_poly"] = 2*_lambda_
# 3.2 Minimum spacing over active
drc["poly_to_poly"] = 3*_lambda_
# 3.3 Minimum gate extension of active
drc["poly_extend_active"] = 2*_lambda_
# 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
drc["poly_to_polycontact"] = 4*_lambda_
# ??
drc["active_enclosure_gate"] = 0.0
# 3.5 Minimum field poly to active
drc["poly_to_active"] = _lambda_
# 3.2.a Minimum spacing over field poly
drc["poly_to_field_poly"] = 3*_lambda_
# Not a rule
drc["minarea_poly"] = 0.0
# ??
drc["active_to_body_active"] = 4*_lambda_ # Fix me
# 2.1 Minimum width
drc["minwidth_active"] = 3*_lambda_
# 2.2 Minimum spacing
drc["active_to_active"] = 3*_lambda_
# 2.3 Source/drain active to well edge
drc["well_enclosure_active"] = 6*_lambda_
# Reserved for asymmetric enclosures
drc["well_extend_active"] = 6*_lambda_
# Not a rule
drc["minarea_active"] = 0.0
# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
drc["implant_to_channel"] = 3*_lambda_
# 4.2 Minimum select overlap of active
drc["implant_enclosure_active"] = 2*_lambda_
# 4.3 Minimum select overlap of contact
drc["implant_enclosure_contact"] = _lambda_
# Not a rule
drc["implant_to_contact"] = 0
# Not a rule
drc["implant_to_implant"] = 0
# Not a rule
drc["minwidth_implant"] = 0
# 6.1 Exact contact size
drc["minwidth_contact"] = 2*_lambda_
# 5.3 Minimum contact spacing
drc["contact_to_contact"] = 3*_lambda_
# 6.2.b Minimum active overlap
drc["active_enclosure_contact"] = _lambda_
# Reserved for asymmetric enclosure
drc["active_extend_contact"] = _lambda_
# 5.2.b Minimum poly overlap
drc["poly_enclosure_contact"] = _lambda_
# Reserved for asymmetric enclosures
drc["poly_extend_contact"] = _lambda_
# Reserved for other technologies
drc["contact_to_gate"] = 2*_lambda_
# 5.4 Minimum spacing to gate of transistor
drc["contact_to_poly"] = 2*_lambda_
# 7.1 Minimum width
drc["minwidth_metal1"] = 3*_lambda_
# 7.2 Minimum spacing
drc["metal1_to_metal1"] = 3*_lambda_
# 7.3 Minimum overlap of any contact
drc["metal1_enclosure_contact"] = _lambda_
# Reserved for asymmetric enclosure
drc["metal1_extend_contact"] = _lambda_
# 8.3 Minimum overlap by metal1
drc["metal1_enclosure_via1"] = _lambda_
# Reserve for asymmetric enclosures
drc["metal1_extend_via1"] = _lambda_
# Not a rule
drc["minarea_metal1"] = 0
# 8.1 Exact size
drc["minwidth_via1"] = 2*_lambda_
# 8.2 Minimum via1 spacing
drc["via1_to_via1"] = 3*_lambda_
# 9.1 Minimum width
drc["minwidth_metal2"] = 3*_lambda_
# 9.2 Minimum spacing
drc["metal2_to_metal2"] = 3*_lambda_
# 9.3 Minimum overlap of via1
drc["metal2_extend_via1"] = _lambda_
# Reserved for asymmetric enclosures
drc["metal2_enclosure_via1"] = _lambda_
# 14.3 Minimum overlap by metal2
drc["metal2_extend_via2"] = _lambda_
# Reserved for asymmetric enclosures
drc["metal2_enclosure_via2"] = _lambda_
# Not a rule
drc["minarea_metal2"] = 0
# 14.1 Exact size
drc["minwidth_via2"] = 2*_lambda_
# 14.2 Minimum spacing
drc["via2_to_via2"] = 3*_lambda_
# 15.1 Minimum width
drc["minwidth_metal3"] = 3*_lambda_
# 15.2 Minimum spacing to metal3
drc["metal3_to_metal3"] = 3*_lambda_
# 15.3 Minimum overlap of via 2
drc["metal3_extend_via2"] = _lambda_
# Reserved for asymmetric enclosures
drc["metal3_enclosure_via2"] = _lambda_
# 21.3 Minimum overlap by metal3
drc["metal3_extend_via3"] = _lambda_
# Reserved for asymmetric enclosures
drc["metal3_enclosure_via3"] = _lambda_
# Not a rule
drc["minarea_metal3"] = 0
# 21.1 Exact size
drc["minwidth_via3"] = 2*_lambda_
# 21.2 Minimum spacing
drc["via3_to_via3"] = 3*_lambda_
# 22.1 Minimum width
drc["minwidth_metal4"] = 6*_lambda_
# 22.2 Minimum spacing to metal4
drc["metal4_to_metal4"] = 6*_lambda_
# 22.3 Minimum overlap of via 3
drc["metal4_extend_via3"] = 2*_lambda_
# Reserved for asymmetric enclosures
drc["metal4_enclosure_via3"] = 2*_lambda_
# Not a rule
drc["minarea_metal4"] = 0
###################################################
##END DRC/LVS Rules
###################################################
###################################################
##Spice Simulation Parameters
###################################################
# spice model info
spice={}
spice["nmos"]="n"
spice["pmos"]="p"
# This is a map of corners to model files
SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
# FIXME: Uncomment when we have the new spice models
#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] }
spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
"FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
"FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
"SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
"SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"] }
#spice stimulus related variables
spice["feasible_period"] = 5 # estimated feasible period in ns
spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts]
spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts]
spice["rise_time"] = 0.05 # rise time in [Nano-seconds]
spice["fall_time"] = 0.05 # fall time in [Nano-seconds]
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
#sram signal names
#FIXME: We don't use these everywhere...
spice["vdd_name"] = "vdd"
spice["gnd_name"] = "gnd"
spice["control_signals"] = ["CSB", "WEB"]
spice["data_name"] = "DATA"
spice["addr_name"] = "ADDR"
spice["minwidth_tx"] = drc["minwidth_tx"]
spice["channel"] = drc["minlength_channel"]
spice["clk"] = "clk"
# analytical delay parameters
# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2
spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff
spice["msflop_setup"] = 9 # DFF setup time in ps
spice["msflop_hold"] = 1 # DFF hold time in ps
spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
spice["dff_setup"] = 9 # DFF setup time in ps
spice["dff_hold"] = 1 # DFF hold time in ps
spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
# analytical power parameters, many values are temporary
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
spice["flop_transition_prob"] = .5 # Transition probability of inverter.
spice["inv_transition_prob"] = .5 # Transition probability of inverter.
spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand.
spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand.
spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor.
###################################################
##END Spice Simulation Parameters
###################################################

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technology/scn4m_subm/tf/LICENSE Normal file
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The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004,
2006. Users are free to use or modify the NCSU CDK as appropriate as long
as this notice appears in the modified package. The NCSU CDK is
provided with NO WARRANTY.

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technology/scn4m_subm/tf/README Normal file
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;; NCSU CDK v. 1.6.0.beta
;; Last Modified: 2007-07-12
The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004,
2006, 2007. Users are free to use or modify the NCSU CDK as appropriate as long
as this notice appears in the modified package. The NCSU CDK is
provided with NO WARRANTY.
As of version 1.5.1, all documentation for the NCSU CDK is provided
by the NCSU EDA Wiki which can be found at:
http://www.eda.ncsu.edu/
This beta release of the kit is to be used in migrating to Cadence Virtuoso 6.1
for OpenAccess. Details of the conversion of the CDK from the CDB version can
be found in the file cdb2oa/OA_Conversion.txt.
This kit is not yet fully supported. Please post problems and solutions at
http://www.chiptalk.org -> Forums -> NCSU CDK -> NCSU CDK 1.6.0.beta for Virtuoso 6.1
Modified 2018 by MRG to contain SCN4ME Via3/Metal4 layers.

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technology/scn4m_subm/tf/display.drf Normal file
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drDefineDisplay(
;( DisplayName )
( display )
)
drDefineColor(
;( DisplayName ColorsName Red Green Blue )
( display white 255 255 255 )
( display yellow 255 255 0 )
( display silver 217 230 255 )
( display cream 255 255 204 )
( display pink 255 191 242 )
( display magenta 255 0 255 )
( display lime 0 255 0 )
( display tan 255 230 191 )
( display cyan 0 255 255 )
( display cadetBlue 57 191 255 )
( display orange 255 128 0 )
( display red 255 51 51 )
( display purple 153 0 230 )
( display green 0 204 102 )
( display brown 191 64 38 )
( display blue 51 77 255 )
( display slate 140 140 166 )
( display gold 217 204 0 )
( display maroon 230 31 13 )
( display violet 94 0 230 )
( display forest 38 140 107 )
( display chocolate 128 38 38 )
( display navy 51 51 153 )
( display black 0 0 0 )
( display gray 204 204 217 )
( display winColor1 166 166 166 )
( display winColor2 115 115 115 )
( display winColor3 189 204 204 )
( display winColor4 204 204 204 )
( display winColor5 199 199 199 )
( display blinkRed 255 0 0 t )
( display blinkYellow 255 255 0 t )
( display blinkWhite 255 255 255 t )
( display winBack 224 224 224 )
( display winFore 128 0 0 )
( display winText 51 51 51 )
)
drDefineStipple(
;( DisplayName StippleName Bitmap )
( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
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( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
( display dots4 ( ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) ) )
( display dats5 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
)
drDefineLineStyle(
;( DisplayName LineStyle Size Pattern )
( display solid 1 (1 ) )
( display dashed 1 (1 1 1 0 0 1 1 1 ) )
( display dots 1 (1 0 0 ) )
( display dashDot 1 (1 1 1 0 0 1 0 0 ) )
( display shortDash 1 (1 1 0 0 ) )
( display doubleDash 1 (1 1 1 1 0 0 1 1 0 0 ) )
( display hidden 1 (1 0 0 0 ) )
( display thickLine 3 (1 1 1 ) )
( display lineStyle0 1 (1 ) )
( display lineStyle1 1 (1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 ) )
)
drDefinePacket(
;( DisplayName PacketName Stipple LineStyle Fill Outline [FillStyle])
( display NwellNet dots4 thickLine slate slate outlineStipple)
( display border stipple0 solid tan tan solid )
( display y8 stipple0 solid gold gold solid )
( display background stipple1 lineStyle0 black black outlineStipple)
( display y9 stipple0 solid silver silver solid )
( display Metal3Net dots4 solid navy navy outlineStipple)
( display Metal3Net dots4 solid tan tan outlineStipple)
( display A1 stipple0 lineStyle0 winBack winBack solid )
( display pin solid lineStyle0 red red solid )
( display XPNet blank solid yellow yellow outline )
( display hardFence stipple0 solid red red solid )
( display PbaseNet dots4 solid yellow yellow outlineStipple)
( display designFlow3 stipple1 lineStyle0 pink pink outlineStipple)
( display A2 stipple0 lineStyle0 winBack winBack solid )
( display Unrouted1 stipple0 lineStyle1 brown brown solid )
( display RowLbl blank solid cyan cyan outline )
( display edgeLayerPin stipple0 solid yellow yellow solid )
( display instance blank solid winBack red outline )
( display Nselect dots4 solid green green outlineStipple)
( display snap stipple0 solid yellow yellow solid )
( display pinAnt stipple0 solid red red solid )
( display winAttentionText solid solid winText winText solid )
( display designFlow2 stipple1 lineStyle0 purple purple outlineStipple)
( display Unrouted2 stipple0 lineStyle1 red red solid )
( display hilite blank solid white white outline )
( display P2Con solid lineStyle0 orange orange solid )
( display designFlow1 stipple1 lineStyle0 red red outlineStipple)
( display grid1 stipple0 solid gray gray solid )
( display Unrouted3 stipple0 lineStyle1 pink pink solid )
( display ViaNet x solid magenta magenta outlineStipple)
( display select stipple0 solid tan tan solid )
( display Poly2Net dots4 lineStyle0 orange orange outlineStipple)
( display winText solid solid winText winText solid )
( display Unrouted4 stipple0 lineStyle1 orange orange solid )
( display wireLbl solid lineStyle0 cyan cyan solid )
( display designFlow7 stipple1 lineStyle0 cyan cyan outlineStipple)
( display align stipple0 solid tan tan solid )
( display Poly2Pin blank solid yellow yellow outline )
( display Unrouted5 stipple0 lineStyle1 green green solid )
( display unset stipple0 solid forest forest solid )
( display Poly1Net dots4 lineStyle0 red red outlineStipple)
( display Resistor dots2 lineStyle0 cyan cyan outlineStipple)
( display DiodeNet dots4 lineStyle0 cream cream outlineStipple)
( display designFlow6 stipple1 lineStyle0 tan tan outlineStipple)
( display Unrouted6 stipple0 lineStyle1 blue blue solid )
( display resist stipple0 solid cyan cyan solid )
( display designFlow5 stipple1 lineStyle0 silver silver outlineStipple)
( display CapWellNet brick solid slate slate outlineStipple)
( display Unrouted7 stipple0 lineStyle1 purple purple solid )
( display CannotoccupyBnd blank solid red red outline )
( display winTopShadow solid solid white white solid )
( display designFlow4 stipple1 lineStyle0 black black outlineStipple)
( display softFence stipple0 solid yellow yellow solid )
( display ResistorNet dots4 solid cyan cyan outlineStipple)
( display winError solid solid winColor5 winColor5 solid )
( display changedLayerTl1 stipple0 solid yellow yellow solid )
( display prBoundaryLbl stipple0 solid purple purple solid )
( display ActXNet x solid yellow yellow outlineStipple)
( display Pbase stipple10 lineStyle0 yellow yellow outlineStipple)
( display Active dots2 lineStyle0 yellow yellow outlineStipple)
( display changedLayerTl0 stipple0 solid red red solid )
( display spike stipple0 solid purple purple solid )
( display Metal3 grid solid navy violet outlineStipple)
( display Metal4 grid solid tan tan outlineStipple)
( display text blank solid white white outline )
( display Poly1Pin stipple0 lineStyle0 red red solid )
( display Row blank solid cyan cyan outline )
( display Pwell stipple9 lineStyle0 slate slate outlineStipple)
( display Metal2 stipple5 lineStyle0 magenta magenta outlineStipple)
( display wire solid lineStyle0 cyan cyan solid )
( display ActX solid solid yellow yellow solid )
( display Metal1 stipple6 lineStyle0 cadetBlue cadetBlue outlineStipple)
( display Cannotoccupy blank solid red red outline )
( display GroupLbl stipple0 solid green green solid )
( display axis stipple0 solid slate slate solid )
( display SiBlockNet x dashed tan tan outlineStipple)
( display edgeLayer stipple0 solid gray gray solid )
( display annotate2 stipple0 solid lime lime solid )
( display Metal1Pin stipple0 lineStyle0 blue blue solid )
( display Diode stipple7 lineStyle0 cream cream outlineStipple)
( display Glass X lineStyle0 white white X )
( display ViaXNet x solid magenta magenta outlineStipple)
( display annotate3 stipple0 solid cyan cyan solid )
( display Poly2 dots1 lineStyle0 orange orange outlineStipple)
( display deviceAnt stipple0 solid yellow yellow solid )
( display winBottomShadow solid solid winColor1 winColor1 solid )
( display PselectNet dots4 solid brown brown outlineStipple)
( display comment stipple0 lineStyle0 winBack winBack outline )
( display Poly1 dots lineStyle0 red red outlineStipple)
( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid )
( display stretch stipple0 solid yellow yellow solid )
( display XP blank lineStyle0 winBack gold outline )
( display annotate1 stipple0 solid pink pink solid )
( display Group stipple2 solid green green outlineStipple)
( display deviceLbl stipple0 solid green green solid )
( display annotate6 stipple0 solid silver silver solid )
( display GlassNet blank solid yellow yellow outline )
( display Canplace blank solid cyan cyan outline )
( display annotate7 stipple0 solid red red solid )
( display Via2 solid solid navy navy solid )
( display Metal2Pin stipple0 lineStyle0 magenta magenta solid )
( display annotate4 stipple0 solid yellow yellow solid )
( display device1 stipple1 lineStyle0 green green outlineStipple)
( display "90" blank solid white white outline )
( display markerWarn x solid yellow yellow outlineStipple)
( display text2 stipple1 lineStyle0 white white outlineStipple)
( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple)
( display designFlow stipple1 lineStyle0 green green outlineStipple)
( display hilite1 stipple0 solid silver silver solid )
( display device blank solid green green outline )
( display prBoundary stipple0 solid purple purple solid )
( display annotate5 stipple0 solid white white solid )
( display text1 stipple0 dashed white white solid )
( display Via solid solid magenta magenta solid )
( display Capacitor stipple7 lineStyle0 tan tan outlineStipple)
( display markerErr x solid white white outlineStipple)
( display unknown stipple0 solid yellow yellow solid )
( display annotate stipple0 solid orange orange solid )
( display P1ConNet x solid red red outlineStipple)
( display hilite3 stipple0 solid cyan cyan solid )
( display winActiveBanner solid solid winColor3 winColor3 solid )
( display pinLbl stipple0 solid red red solid )
( display device2 stipple0 lineStyle1 green green solid )
( display grid stipple0 solid slate slate solid )
( display winBackground solid solid winBack winBack solid )
( display Metal1Net dots4 lineStyle0 blue blue outlineStipple)
( display hilite2 stipple0 solid tan tan solid )
( display annotate8 stipple0 solid tan tan solid )
( display hilite5 stipple0 solid lime lime solid )
( display annotate9 stipple0 solid green green solid )
( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple)
( display Metal3Pin stipple0 solid navy navy solid )
( display Metal4Pin stipple0 solid tan tan solid )
( display hilite4 stipple0 solid gray gray solid )
( display y0 stipple0 solid gray gray solid )
( display supply stipple0 solid lime lime solid )
( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple)
( display hilite7 stipple0 solid cream cream solid )
( display y1 stipple0 solid brown brown solid )
( display defaultPacket x solid chocolate winColor2 outlineStipple)
( display Via2Net cross solid navy navy outlineStipple)
( display NselectNet dots4 solid green green outlineStipple)
( display Unrouted8 stipple0 lineStyle1 gold gold solid )
( display hilite6 stipple0 solid orange orange solid )
( display y2 stipple0 solid red red solid )
( display winBorder solid solid winColor2 winColor2 solid )
( display Nwell dats5 thickLine slate slate outlineStipple)
( display Unrouted9 stipple0 lineStyle1 silver silver solid )
( display hilite9 stipple0 solid pink pink solid )
( display SiBlock blank dashed tan tan outline )
( display y3 stipple0 solid orange orange solid )
( display prBoundaryBnd stipple0 solid cyan cyan solid )
( display winForeground solid solid winFore winFore solid )
( display hilite8 stipple0 solid magenta magenta solid )
( display y4 stipple0 solid yellow yellow solid )
( display Pselect dots1 solid brown brown outlineStipple)
( display winInactiveBanner solid solid winColor4 winColor4 solid )
( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple)
( display winButton solid solid winFore winFore solid )
( display y5 stipple0 solid green green solid )
( display hiz stipple0 solid orange orange solid )
( display drive stipple0 solid blue blue solid )
( display wireFlt stipple0 dashed red red solid )
( display instanceLbl stipple0 solid gold gold solid )
( display P2ConNet x lineStyle0 orange orange outlineStipple)
( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple)
( display y6 stipple0 solid blue blue solid )
( display PwellNet dots4 lineStyle0 slate slate outlineStipple)
( display P1Con solid solid red red solid )
( display CapWell dagger solid slate slate outlineStipple)
( display y7 stipple0 solid purple purple solid )
( display ViaX solid solid magenta magenta solid )
( display HR x solid chocolate winColor2 outlineStipple)
( display HRnet x solid chocolate winColor2 outlineStipple)
)

7
technology/scn4m_subm/tf/glade_scn4me_subm.py Normal file
View File

@ -0,0 +1,7 @@
import os
CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf"
ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map")

4
technology/scn3me_subm/layers.map → technology/scn4m_subm/tf/layers.map
View File

@ -12,5 +12,7 @@ Via drawing 50 0
Metal2 drawing 51 0
Via2 drawing 61 0
Metal3 drawing 62 0
Via3 drawing 30 0
Metal4 drawing 31 0
Glass drawing 52 0
text drawing 83 0
comment drawing 63 0

850
technology/scn4m_subm/tf/mosis.tf Normal file
View File

@ -0,0 +1,850 @@
; Generated on Sep 28 16:05:23 1998
; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $
;
; Matt Clapp fixed: October 10, 2002
; added via devices, deleted useless app-specific crap,
; added lxExtractRules so undo in layout editor doesn't
; complain.
;********************************
; LAYER DEFINITION
;********************************
layerDefinitions(
techLayers(
;( LayerName Layer# Abbreviation )
;( --------- ------ ------------ )
;User-Defined Layers:
( P2Con 3 P2Con )
( Poly2 7 Poly2 )
( Pbase 10 Pbase )
( Resistor 16 Resisto )
( Capacitor 17 Capacit )
( Diode 18 Diode )
( SiBlock 29 SiBlock )
( HR 34 HR )
( Pwell 41 Pwell )
( Nwell 42 Nwell )
( Active 43 Active )
( Pselect 44 Pselect )
( Nselect 45 Nselect )
( Poly1 46 Poly1 )
( P1Con 47 P1Con )
( ActX 48 ActX )
( Metal1 49 Metal1 )
( Via 50 Via )
( Metal2 51 Metal2 )
( Glass 52 Glass )
( CapWell 59 CapWell )
( XP 60 XP )
( Via2 61 Via2 )
( Metal3 62 Metal3 )
( Via3 30 Via3 )
( Metal4 31 Metal4 )
( A1 80 A1 )
( A2 81 A2 )
( comment 117 comment )
;System-Reserved Layers:
( Unrouted 200 Unroute )
( Row 201 Row )
( Group 202 Group )
( Cannotoccupy 203 Cannoto )
( Canplace 204 Canplac )
( hardFence 205 hardFen )
( softFence 206 softFen )
( y0 207 y0 )
( y1 208 y1 )
( y2 209 y2 )
( y3 210 y3 )
( y4 211 y4 )
( y5 212 y5 )
( y6 213 y6 )
( y7 214 y7 )
( y8 215 y8 )
( y9 216 y9 )
( designFlow 217 designF )
( stretch 218 stretch )
( edgeLayer 219 edgeLay )
( changedLayer 220 changed )
( unset 221 unset )
( unknown 222 unknown )
( spike 223 spike )
( hiz 224 hiz )
( resist 225 resist )
( drive 226 drive )
( supply 227 supply )
( wire 228 wire )
( pin 229 pin )
( text 230 text )
( device 231 device )
( border 232 border )
( snap 233 snap )
( align 234 align )
( prBoundary 235 prBound )
( instance 236 instanc )
( annotate 237 annotat )
( marker 238 marker )
( select 239 select )
( grid 251 grid )
( axis 252 axis )
( hilite 253 hilite )
( background 254 backgro )
) ;techLayers
techPurposes(
;( PurposeName Purpose# Abbreviation )
;( ----------- -------- ------------ )
;User-Defined Purposes:
;System-Reserved Purposes:
( warning 234 wng )
( tool1 235 tl1 )
( tool0 236 tl0 )
( label 237 lbl )
( flight 238 flt )
( error 239 err )
( annotate 240 ant )
( drawing1 241 dr1 )
( drawing2 242 dr2 )
( drawing3 243 dr3 )
( drawing4 244 dr4 )
( drawing5 245 dr5 )
( drawing6 246 dr6 )
( drawing7 247 dr7 )
( drawing8 248 dr8 )
( drawing9 249 dr9 )
( boundary 250 bnd )
( pin 251 pin )
( drawing 252 drw )
( net 253 net )
( cell 254 cel )
( all 255 all )
) ;techPurposes
techLayerPurposePriorities(
;layers are ordered from lowest to highest priority
; (higher priority is drawn on top of lower priority)
;( LayerName Purpose )
;( --------- ------- )
( background drawing )
( grid drawing )
( grid drawing1 )
( Nwell drawing )
( Pwell drawing )
( CapWell drawing )
( Pselect drawing )
( Nselect drawing )
( Active drawing )
( ActX drawing )
( SiBlock drawing )
( HR drawing )
( Poly1 drawing )
( P1Con drawing )
( Poly2 drawing )
( P2Con drawing )
( Metal1 drawing )
( Via drawing )
( Metal2 drawing )
( Via2 drawing )
( Metal3 drawing )
( annotate drawing )
( annotate drawing1 )
( annotate drawing2 )
( annotate drawing3 )
( annotate drawing4 )
( annotate drawing5 )
( annotate drawing6 )
( annotate drawing7 )
( annotate drawing8 )
( annotate drawing9 )
( Poly1 pin )
( Metal1 pin )
( Metal2 pin )
( Metal3 pin )
( Glass drawing )
( XP drawing )
( prBoundary drawing )
( prBoundary boundary )
( instance drawing )
( prBoundary label )
( instance label )
( Row drawing )
( Nwell net )
( align drawing )
( Pwell net )
( CapWell net )
( hardFence drawing )
( Active net )
( softFence drawing )
( Row label )
( Group drawing )
( Group label )
( Cannotoccupy drawing )
( Cannotoccupy boundary )
( Canplace drawing )
( ActX net )
( A2 drawing )
( A1 drawing )
( comment drawing )
( border drawing )
( Pselect net )
( Nselect net )
( SiBlock net )
( HR net )
( wire drawing )
( Poly1 net )
( wire label )
( P1Con net )
( wire flight )
( Metal1 net )
( device annotate )
( Metal2 net )
( device label )
( Via net )
( Metal3 net )
( Via2 net )
( pin label )
( text drawing )
( pin drawing )
( text drawing1 )
( pin annotate )
( device drawing )
( axis drawing )
( edgeLayer drawing )
( edgeLayer pin )
( snap drawing )
( stretch drawing )
( y0 drawing )
( y1 drawing )
( y2 drawing )
( y3 drawing )
( y4 drawing )
( y5 drawing )
( y6 drawing )
( y7 drawing )
( y8 drawing )
( y9 drawing )
( hilite drawing )
( hilite drawing1 )
( hilite drawing2 )
( hilite drawing3 )
( hilite drawing4 )
( hilite drawing5 )
( hilite drawing6 )
( hilite drawing7 )
( hilite drawing8 )
( hilite drawing9 )
( select drawing )
( drive drawing )
( hiz drawing )
( resist drawing )
( spike drawing )
( supply drawing )
( unknown drawing )
( unset drawing )
( designFlow drawing )
( designFlow drawing1 )
( designFlow drawing2 )
( designFlow drawing3 )
( designFlow drawing4 )
( designFlow drawing5 )
( designFlow drawing6 )
( designFlow drawing7 )
( designFlow drawing8 )
( designFlow drawing9 )
( changedLayer tool0 )
( changedLayer tool1 )
( marker warning )
( marker error )
( device drawing1 )
( Pbase drawing )
( Pbase net )
( Resistor net )
( Resistor drawing )
( Capacitor net )
( Capacitor drawing )
( Diode net )
( Diode drawing )
( Poly2 net )
( P2Con net )
( device drawing2 )
( Unrouted drawing )
( text drawing2 )
( Unrouted drawing1 )
( Unrouted drawing2 )
( Unrouted drawing3 )
( Unrouted drawing4 )
( Unrouted drawing5 )
( Unrouted drawing6 )
( Unrouted drawing7 )
( Unrouted drawing8 )
( Unrouted drawing9 )
) ;techLayerPurposePriorities
techDisplays(
;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid )
;( --------- ------- ------ --- --- --------- ------- ----- )
( background drawing background t nil nil nil nil )
( grid drawing grid t nil nil nil nil )
( grid drawing1 grid1 t nil nil nil nil )
( Nwell drawing Nwell t t t t t )
( Pwell drawing Pwell t t t t nil )
( Active drawing Active t t t t t )
( ActX drawing ActX t t t t t )
( Pselect drawing Pselect t t t t t )
( Nselect drawing Nselect t t t t t )
( SiBlock drawing SiBlock t t t t t )
( HR drawing HR t t t t t )
( CapWell drawing CapWell t t t t t )
( Poly1 drawing Poly1 t t t t t )
( P1Con drawing P1Con t t t t t )
( Metal1 drawing Metal1 t t t t t )
( Via drawing Via t t t t t )
( Metal2 drawing Metal2 t t t t t )
( annotate drawing annotate t t nil t nil )
( annotate drawing1 annotate1 t t nil t nil )
( annotate drawing2 annotate2 t t nil t nil )
( annotate drawing3 annotate3 t t nil t nil )
( annotate drawing4 annotate4 t t nil t nil )
( annotate drawing5 annotate5 t t nil t nil )
( annotate drawing6 annotate6 t t nil t nil )
( annotate drawing7 annotate7 t t nil t nil )
( annotate drawing8 annotate8 t t nil t nil )
( annotate drawing9 annotate9 t t nil t nil )
( Via2 drawing Via2 t t t t t )
( Metal3 drawing Metal3 t t t t t )
( Glass drawing Glass t t t nil t )
( XP drawing XP t t t nil t )
( Metal1 pin Metal1Pin t t t nil t )
( Metal2 pin Metal2Pin t t t nil t )
( Metal3 pin Metal3Pin t t t nil t )
( Poly1 pin Poly1Pin t t t nil t )
( prBoundary drawing prBoundary t t nil t nil )
( prBoundary boundary prBoundaryBnd t t nil t nil )
( instance drawing instance t t nil t t )
( prBoundary label prBoundaryLbl t t t t nil )
( instance label instanceLbl t t t t nil )
( Row drawing Row t t t t nil )
( Nwell net NwellNet t t t nil nil )
( align drawing align t t nil t nil )
( Pwell net PwellNet t t t nil nil )
( CapWell net CapWellNet t t t nil nil )
( SiBlock net SiBlockNet t t t nil nil )
( HR net HRnet t t t nil nil )
( hardFence drawing hardFence t t t t nil )
( Active net ActiveNet t t t nil nil )
( softFence drawing softFence t t t t nil )
( Row label RowLbl t t t t nil )
( Group drawing Group t t t t nil )
( Group label GroupLbl t t t t nil )
( Cannotoccupy drawing Cannotoccupy t t t t nil )
( Cannotoccupy boundary CannotoccupyBnd t t t t nil )
( Canplace drawing Canplace t t t t nil )
( ActX net ActXNet t t t nil nil )
( A2 drawing A2 t t t t nil )
( A1 drawing A1 t t t t nil )
( comment drawing comment t t t t nil )
( border drawing border t t t t nil )
( Pselect net PselectNet t t t nil nil )
( Nselect net NselectNet t t t nil nil )
( wire drawing wire t t t t nil )
( Poly1 net Poly1Net t t t nil nil )
( wire label wireLbl t t t t nil )
( P1Con net P1ConNet t t t nil nil )
( wire flight wireFlt t t t t nil )
( Metal1 net Metal1Net t t t nil nil )
( device annotate deviceAnt t t t t nil )
( Metal2 net Metal2Net t t t nil nil )
( Metal3 net Metal3Net t t t nil nil )
( device label deviceLbl t t t t nil )
( Via net ViaNet t t t nil nil )
( Via2 net Via2Net t t t nil nil )
( pin label pinLbl t t t t nil )
( text drawing text t t t t t )
( pin drawing pin t t t t nil )
( text drawing1 text1 t t t t nil )
( pin annotate pinAnt t t t t nil )
( device drawing device t t t t nil )
( axis drawing axis t t t t nil )
( edgeLayer drawing edgeLayer t t nil t nil )
( edgeLayer pin edgeLayerPin t t nil t nil )
( snap drawing snap t t nil t nil )
( stretch drawing stretch t t nil t nil )
( y0 drawing y0 t t nil t nil )
( y1 drawing y1 t t nil t nil )
( y2 drawing y2 t t nil t nil )
( y3 drawing y3 t t nil t nil )
( y4 drawing y4 t t nil t nil )
( y5 drawing y5 t t nil t nil )
( y6 drawing y6 t t nil t nil )
( y7 drawing y7 t t nil t nil )
( y8 drawing y8 t t nil t nil )
( y9 drawing y9 t t nil t nil )
( hilite drawing hilite t t nil t nil )
( hilite drawing1 hilite1 t t t t nil )
( hilite drawing2 hilite2 t t nil t nil )
( hilite drawing3 hilite3 t t t t nil )
( hilite drawing4 hilite4 t t t t nil )
( hilite drawing5 hilite5 t t t t nil )
( hilite drawing6 hilite6 t t t t nil )
( hilite drawing7 hilite7 t t t t nil )
( hilite drawing8 hilite8 t t t t nil )
( hilite drawing9 hilite9 t t t t nil )
( select drawing select t t nil t nil )
( drive drawing drive t t t t nil )
( hiz drawing hiz t t t t nil )
( resist drawing resist t t t t nil )
( spike drawing spike t t t t nil )
( supply drawing supply t t t t nil )
( unknown drawing unknown t t t t nil )
( unset drawing unset t t t t nil )
( designFlow drawing designFlow t t t nil nil )
( designFlow drawing1 designFlow1 t t t nil nil )
( designFlow drawing2 designFlow2 t t t nil nil )
( designFlow drawing3 designFlow3 t t t nil nil )
( designFlow drawing4 designFlow4 t t t nil nil )
( designFlow drawing5 designFlow5 t t t nil nil )
( designFlow drawing6 designFlow6 t t t nil nil )
( designFlow drawing7 designFlow7 t t t nil nil )
( designFlow drawing8 designFlow8 t t t nil nil )
( designFlow drawing9 designFlow9 t t t nil nil )
( changedLayer tool0 changedLayerTl0 nil nil nil nil nil )
( changedLayer tool1 changedLayerTl1 nil nil t nil nil )
( marker warning markerWarn t t t t nil )
( marker error markerErr t t t t nil )
( device drawing1 device1 t t t t nil )
( Poly2 net Poly2Net t t t nil nil )
( Poly2 drawing Poly2 t t t t t )
( P2Con net P2ConNet t t t nil nil )
( P2Con drawing P2Con t t t t t )
( Pbase net PbaseNet t t t nil nil )
( Pbase drawing Pbase t t t t t )
( Resistor net ResistorNet t t t nil nil )
( Resistor drawing Resistor t t t t t )
( Capacitor net CapacitorNet t t t nil nil )
( Capacitor drawing Capacitor t t t t t )
( Diode net DiodeNet t t t nil nil )
( Diode drawing Diode t t t t t )
( device drawing2 device2 t t t t nil )
( Unrouted drawing Unrouted t t t t nil )
( text drawing2 text2 t t t t nil )
( Unrouted drawing1 Unrouted1 t t t t nil )
( Unrouted drawing2 Unrouted2 t t t t nil )
( Unrouted drawing3 Unrouted3 t t t t nil )
( Unrouted drawing4 Unrouted4 t t t t nil )
( Unrouted drawing5 Unrouted5 t t t t nil )
( Unrouted drawing6 Unrouted6 t t t t nil )
( Unrouted drawing7 Unrouted7 t t t t nil )
( Unrouted drawing8 Unrouted8 t t t t nil )
( Unrouted drawing9 Unrouted9 t t t t nil )
) ;techDisplays
; I don't think the following is necessary (or used!)
techLayerProperties(
;( PropName Layer1 [ Layer2 ] PropValue )
( contactLimit P2Con 10000 )
( eqPinLimit P2Con 10000 )
( horizontalJogLength P2Con 2147483648.000000 )
( routingGrid P2Con 1.000000 )
( verticalJogLength P2Con 2147483648.000000 )
( routingGrid Poly2 1.000000 )
( contactLimit Active 10000 )
( eqPinLimit Active 10000 )
( horizontalJogLength Active 2147483648.000000 )
( routingGrid Active 1.000000 )
( verticalJogLength Active 2147483648.000000 )
( routingGrid Poly1 1.000000 )
( contactLimit P1Con 10000 )
( eqPinLimit P1Con 10000 )
( horizontalJogLength P1Con 2147483648.000000 )
( routingGrid P1Con 1.000000 )
( verticalJogLength P1Con 2147483648.000000 )
( contactLimit ActX 10000 )
( eqPinLimit ActX 10000 )
( horizontalJogLength ActX 2147483648.000000 )
( routingGrid ActX 1.000000 )
( verticalJogLength ActX 2147483648.000000 )
( routingGrid Metal1 1.000000 )
( contactLimit Via 10000 )
( eqPinLimit Via 10000 )
( horizontalJogLength Via 2147483648.000000 )
( routingGrid Via 1.000000 )
( verticalJogLength Via 2147483648.000000 )
( routingGrid Metal2 1.000000 )
)
) ;layerDefinitions
;********************************
; DEVICE RULES
;********************************
devices(
tcCreateCDSDeviceClass()
symContactDevice(
;( deviceName viaLayer viaPurpose
( VIA Via drawing
; layer1 purpose1 [implant1]
Metal1 drawing
; layer2 purpose2 [implant2]
Metal2 drawing
; width length [( row column xPitch yPitch xBias yBias )]
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
2 2
; encLayer1 encLayer2 legalRegion )
1 1 _NA_)
) ;symContactDevice
symContactDevice(
;( deviceName viaLayer viaPurpose
( VIA2 Via2 drawing
; layer1 purpose1 [implant1]
Metal2 drawing
; layer2 purpose2 [implant2]
Metal3 drawing
; width length [( row column xPitch yPitch xBias yBias )]
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
2 2
; encLayer1 encLayer2 legalRegion )
1 2 _NA_)
) ;symContactDevice
) ;devices
;********************************
; LAYER RULES
;********************************
layerRules(
streamLayers(
;( layer streamNumber dataType translate )
;( ----- ------------ -------- --------- )
( ("background" "drawing") 0 0 nil )
( ("grid" "drawing") 0 0 nil )
( ("grid" "drawing1") 0 0 nil )
( ("Nwell" "drawing") 42 0 t )
( ("Pwell" "drawing") 41 0 t )
( ("Active" "drawing") 43 0 t )
( ("ActX" "drawing") 48 0 t )
( ("Pselect" "drawing") 44 0 t )
( ("Nselect" "drawing") 45 0 t )
( ("Poly1" "drawing") 46 0 t )
( ("P1Con" "drawing") 47 0 t )
( ("Metal1" "drawing") 49 0 t )
( ("Metal2" "drawing") 51 0 t )
( ("annotate" "drawing") 0 0 nil )
( ("annotate" "drawing1") 0 0 nil )
( ("annotate" "drawing2") 0 0 nil )
( ("annotate" "drawing3") 0 0 nil )
( ("annotate" "drawing4") 0 0 nil )
( ("annotate" "drawing5") 0 0 nil )
( ("annotate" "drawing6") 0 0 nil )
( ("annotate" "drawing7") 0 0 nil )
( ("annotate" "drawing8") 0 0 nil )
( ("annotate" "drawing9") 0 0 nil )
( ("Via" "drawing") 50 0 t )
( ("Glass" "drawing") 52 0 t )
( ("XP" "drawing") 60 0 t )
( ("Metal2" "pin") 0 0 nil )
( ("Poly1" "pin") 0 0 nil )
( ("prBoundary" "drawing") 0 0 nil )
( ("Metal1" "pin") 0 0 nil )
( ("prBoundary" "boundary") 0 0 nil )
( ("instance" "drawing") 246 0 nil )
( ("instance" "label") 0 0 nil )
( ("Nwell" "net") 0 0 nil )
( ("align" "drawing") 0 0 nil )
( ("Pwell" "net") 0 0 nil )
( ("hardFence" "drawing") 0 0 nil )
( ("Active" "net") 0 0 nil )
( ("softFence" "drawing") 0 0 nil )
( ("ActX" "net") 0 0 nil )
( ("A2" "drawing") 5 0 nil )
( ("A1" "drawing") 2 0 nil )
( ("comment" "drawing") 0 0 nil )
( ("border" "drawing") 0 0 nil )
( ("Pselect" "net") 0 0 nil )
( ("Nselect" "net") 0 0 nil )
( ("wire" "drawing") 0 0 nil )
( ("Poly1" "net") 0 0 nil )
( ("P1Con" "net") 0 0 nil )
( ("Metal1" "net") 0 0 nil )
( ("Metal2" "net") 0 0 nil )
( ("device" "label") 0 0 nil )
( ("Via" "net") 0 0 nil )
( ("pin" "label") 0 0 nil )
( ("text" "drawing") 63 0 t )
( ("pin" "drawing") 0 0 nil )
( ("device" "drawing") 0 0 nil )
( ("axis" "drawing") 0 0 nil )
( ("edgeLayer" "drawing") 0 0 nil )
( ("edgeLayer" "pin") 0 0 nil )
( ("snap" "drawing") 0 0 nil )
( ("stretch" "drawing") 0 0 nil )
( ("y0" "drawing") 0 0 nil )
( ("y1" "drawing") 0 0 nil )
( ("y2" "drawing") 0 0 nil )
( ("y3" "drawing") 0 0 nil )
( ("y4" "drawing") 0 0 nil )
( ("y5" "drawing") 0 0 nil )
( ("y6" "drawing") 0 0 nil )
( ("y7" "drawing") 0 0 nil )
( ("y8" "drawing") 0 0 nil )
( ("y9" "drawing") 0 0 nil )
( ("hilite" "drawing") 0 0 nil )
( ("hilite" "drawing2") 0 0 nil )
( ("select" "drawing") 0 0 nil )
( ("drive" "drawing") 0 0 nil )
( ("hiz" "drawing") 0 0 nil )
( ("resist" "drawing") 0 0 nil )
( ("spike" "drawing") 0 0 nil )
( ("supply" "drawing") 0 0 nil )
( ("unknown" "drawing") 0 0 nil )
( ("unset" "drawing") 0 0 nil )
( ("changedLayer" "tool0") 0 0 nil )
( ("Resistor" "net") 0 0 nil )
( ("Resistor" "drawing") 0 0 nil )
( ("Capacitor" "net") 0 0 nil )
( ("Capacitor" "drawing") 0 0 nil )
( ("Diode" "net") 0 0 nil )
( ("Diode" "drawing") 0 0 nil )
( ("Poly2" "net") 0 0 nil )
( ("Poly2" "drawing") 0 0 nil )
( ("P2Con" "net") 0 0 nil )
( ("P2Con" "drawing") 0 0 nil )
( ("Pbase" "drawing") 0 0 nil )
( ("Pbase" "net") 0 0 nil )
( P2Con 0 0 nil )
( Poly2 0 0 nil )
( Pwell 0 0 nil )
( Nwell 0 0 nil )
( Active 0 0 nil )
( Pselect 0 0 nil )
( Nselect 0 0 nil )
( Poly1 0 0 nil )
( P1Con 0 0 nil )
( ActX 0 0 nil )
( Metal1 0 0 nil )
( Via 0 0 nil )
( Metal2 0 0 nil )
( Glass 0 0 nil )
( XP 0 0 nil )
( ("Via2" "drawing") 50 0 t )
( ("Via2" "net") 0 0 nil )
( ("Metal3" "drawing") 50 0 t )
( ("Metal3" "net") 0 0 nil )
( ("Metal3" "pin") 0 0 nil )
( ("CapWell" "drawing") 0 0 nil )
( ("CapWell" "net") 0 0 nil )
( ("SiBlock" "drawing") 0 0 nil )
( ("SiBlock" "net") 0 0 nil )
( ("HR" "drawing") 0 0 nil )
( ("HR" "net") 0 0 nil )
) ;streamLayers
viaLayers(
;( layer1 viaLayer layer2 )
;( ------ -------- ------ )
( Metal2 Via2 Metal3 )
( Metal1 Via Metal2 )
( Active ActX Poly1 )
( Poly1 P1Con Metal1 )
( Poly2 P2Con Metal1 )
) ;viaLayers
) ;layerRules
;********************************
; PHYSICAL RULES
;********************************
physicalRules(
orderedSpacingRules(
;( rule layer1 layer2 value )
;( ---- ------ ------ ----- )
( minEnclosure "prBoundary" "Metal1" 0.0 )
( minEnclosure "Metal2" "Via" 1.0 )
( minEnclosure "Metal1" "Via" 1.0 )
( minEnclosure "Metal1" "P1Con" 1.0 )
( minEnclosure "Metal1" "ActX" 1.0 )
( minEnclosure "Nselect" "Active" 2.0 )
( minEnclosure "Pselect" "Active" 2.0 )
( minEnclosure "Active" "ActX" 1.0 )
( minEnclosure "Pwell" "Active" 5.0 )
( minEnclosure "Nwell" "Active" 5.0 )
) ;orderedSpacingRules
spacingRules(
;( rule layer1 layer2 value )
;( ---- ------ ------ ----- )
( minSpacing "P2Con" 2.0 )
( minSpacing "Poly2" 3.0 )
( minSpacing "Pwell" 9.0 )
( minSpacing "Nwell" 9.0 )
( minSpacing "Active" 3.0 )
( minSpacing "Pselect" 2.0 )
( minSpacing "Nselect" 2.0 )
( minSpacing "Poly1" 2.0 )
( minSpacing "P1Con" 2.0 )
( minSpacing "ActX" 2.0 )
( minSpacing "Metal1" 3.0 )
( minSpacing "Via" 3.0 )
( minSpacing "Via2" 3.0 )
( minSpacing "Metal2" 3.0 )
( minSpacing "Metal3" 4.0 )
( minSpacing "Glass" 75.0 )
( minSpacing "XP" 100.0 )
( minSpacing "Metal2" 4.0 )
( minSpacing "P1Con" "Via" 2.0 )
( minSpacing "ActX" "Via" 2.0 )
( minSpacing "ActX" "P2Con" 2.0 )
( minSpacing "Poly2" "P2Con" 4.0 )
( minSpacing "Poly1" "P1Con" 4.0 )
( minSpacing "ActX" "P1Con" 2.0 )
( minSpacing "Active" "P1Con" 2.0 )
( minSpacing "Active" "Poly2" 2.0 )
( minSpacing "Poly1" "Poly2" 2.0 )
( minSpacing "Active" "Poly1" 2.0 )
( minSpacing "ActX" "Poly1" 2.0 )
( minSpacing "Pselect" "Nselect" 0.0 )
( minSpacing "Nwell" "Pwell" 9.0 )
( minWidth "P2Con" 2.0 )
( minWidth "Poly2" 3.0 )
( minWidth "Pwell" 10.0 )
( minWidth "Nwell" 10.0 )
( minWidth "Active" 3.0 )
( minWidth "Pselect" 2.0 )
( minWidth "Nselect" 2.0 )
( minWidth "Poly1" 2.0 )
( minWidth "P1Con" 2.0 )
( minWidth "ActX" 2.0 )
( minWidth "Metal1" 4.0 )
( minWidth "Via" 2.0 )
( minWidth "Metal2" 4.0 )
( minWidth "Glass" 75.0 )
( minWidth "XP" 100.0 )
( minWidth "Metal3" 6.0 )
) ;spacingRules
mfgGridResolution(
( 1.000000 )
) ;mfgGridResolution
) ;physicalRules
;********************************
; ELECTRICAL RULES
;********************************
electricalRules(
characterizationRules(
;( rule layer1 layer2 value )
;( ---- ------ ------ ----- )
( areaCap "P2Con" 0.0 )
( areaCap "Poly2" 0.0 )
( areaCap "Active" 0.0 )
( areaCap "Poly1" 6e-05 )
( areaCap "P1Con" 0.0 )
( areaCap "ActX" 0.0 )
( areaCap "Metal1" 2.6e-05 )
( areaCap "Via" 0.0 )
( areaCap "Metal2" 1.6e-05 )
( edgeCapacitance "P2Con" 0.0 )
( edgeCapacitance "Poly2" 0.0 )
( edgeCapacitance "Active" 0.0 )
( edgeCapacitance "Poly1" 0.0 )
( edgeCapacitance "P1Con" 0.0 )
( edgeCapacitance "ActX" 0.0 )
( edgeCapacitance "Metal1" 0.0 )
( edgeCapacitance "Via" 0.0 )
( edgeCapacitance "Metal2" 0.0 )
( sheetRes "P2Con" 0.0 )
( sheetRes "Poly2" 0.0 )
( sheetRes "Active" 0.0 )
( sheetRes "Poly1" 23.0 )
( sheetRes "P1Con" 0.0 )
( sheetRes "ActX" 0.0 )
( sheetRes "Metal1" 0.04 )
( sheetRes "Via" 0.0 )
( sheetRes "Metal2" 0.07 )
( currentDensity "P2Con" 1.0 )
( currentDensity "Poly2" 1.0 )
( currentDensity "Active" 1.0 )
( currentDensity "Poly1" 1.0 )
( currentDensity "P1Con" 1.0 )
( currentDensity "ActX" 1.0 )
( currentDensity "Metal1" 1.0 )
( currentDensity "Via" 1.0 )
( currentDensity "Metal2" 1.0 )
) ;characterizationRules
) ;electricalRules
;********************************
; LAYOUT EDITOR RULES
;********************************
; specifies the ordering of the layers in the LSW
leRules(
leLswLayers(
;( layer purpose )
; ----- ------- )
( Nwell drawing )
( Pselect drawing )
( Nselect drawing )
( Active drawing )
( ActX drawing )
( Poly1 drawing )
( P1Con drawing )
( Metal1 drawing )
( Via drawing )
( Metal2 drawing )
( Via2 drawing )
( Metal3 drawing )
( Poly1 pin )
( Metal1 pin )
( Metal2 pin )
( Metal3 pin )
( Poly2 drawing )
( P2Con drawing )
( instance drawing )
( text drawing )
( CapWell drawing )
( SiBlock drawing )
( HR drawing )
( Pbase drawing )
( Resistor drawing )
( Capacitor drawing )
( Diode drawing )
( Glass drawing )
( XP drawing )
) ;leLswLayers
) ;leRules
;********************************
; VIRTUOSO XL RULES
;********************************
; specifies the ordering of the layers in the LSW
lxRules(
lxExtractLayers(
(Metal1 Metal2 Metal3)
) ;lxExtractLayers
) ;lxRules

41
technology/setup_scripts/setup_openram_scn4m_subm.py Normal file
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@ -0,0 +1,41 @@
#!/usr/bin/python
"""
This type of setup script should be placed in the setup_scripts directory in the trunk
"""
import sys
import os
TECHNOLOGY = "scn4m_subm"
##########################
# CDK paths
# os.environ["CDK_DIR"] = CDK_DIR #PDK path
# os.environ["SYSTEM_CDS_LIB_DIR"] = "{0}/cdssetup".format(CDK_DIR)
# os.environ["CDS_SITE"] = CDK_DIR
os.environ["MGC_TMPDIR"] = "/tmp"
###########################
# OpenRAM Paths
try:
DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME"))
except:
OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech"
os.environ["DRCLVS_HOME"] = DRCLVS_HOME
# try:
# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
# except:
OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
##########################
# Paths required for OPENRAM to function
LOCAL = "{0}/..".format(os.path.dirname(__file__))
sys.path.append("{0}/{1}/tech".format(LOCAL,TECHNOLOGY))