From 30a77f8527fa72da8e721ebbe67b5b193895d0ae Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 11:01:30 -0700 Subject: [PATCH 01/14] Convert scn3me_subm tech to lambda rules --- technology/scn3me_subm/tech/tech.py | 97 +++++++++++++++-------------- 1 file changed, 49 insertions(+), 48 deletions(-) diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 463f4243..52c602cf 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -50,17 +50,18 @@ layer["blockage"] = 83 ################################################### ##DRC/LVS Rules Setup ################################################### +_lambda_ = 0.3 #technology parameter parameter={} -parameter["min_tx_size"] = 1.2 +parameter["min_tx_size"] = 4*_lambda_ parameter["beta"] = 2 drclvs_home=os.environ.get("DRCLVS_HOME") drc={} #grid size is 1/2 a lambda -drc["grid"]=0.15 +drc["grid"]=0.5*_lambda_ #DRC/LVS test set_up drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul" drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul" @@ -68,52 +69,52 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" # minwidth_tx with contact (no dog bone transistors) -drc["minwidth_tx"] = 1.2 -drc["minlength_channel"] = 0.6 +drc["minwidth_tx"] = 4*_lambda_ +drc["minlength_channel"] = 2*_lambda_ # 1.3 Minimum spacing between wells of same type (if both are drawn) -drc["well_to_well"] = 1.8 +drc["well_to_well"] = 6*_lambda_ # 1.4 Minimum spacing between wells of different type (if both are drawn) drc["pwell_to_nwell"] = 0 # 1.1 Minimum width -drc["minwidth_well"] = 3.6 +drc["minwidth_well"] = 12*_lambda_ # 3.1 Minimum width -drc["minwidth_poly"] = 0.6 +drc["minwidth_poly"] = 2*_lambda_ # 3.2 Minimum spacing over active -drc["poly_to_poly"] = 0.9 +drc["poly_to_poly"] = 3*_lambda_ # 3.3 Minimum gate extension of active -drc["poly_extend_active"] = 0.6 +drc["poly_extend_active"] = 2*_lambda_ # 5.5.b Minimum spacing between poly contact and other poly (alternative rules) -drc["poly_to_polycontact"] = 1.2 +drc["poly_to_polycontact"] = 4*_lambda_ # ?? drc["active_enclosure_gate"] = 0.0 # 3.5 Minimum field poly to active -drc["poly_to_active"] = 0.3 +drc["poly_to_active"] = _lambda_ # 3.2.a Minimum spacing over field poly -drc["poly_to_field_poly"] = 0.9 +drc["poly_to_field_poly"] = 3*_lambda_ # Not a rule drc["minarea_poly"] = 0.0 # ?? -drc["active_to_body_active"] = 1.2 # Fix me +drc["active_to_body_active"] = 4*_lambda_ # Fix me # 2.1 Minimum width -drc["minwidth_active"] = 0.9 +drc["minwidth_active"] = 3*_lambda_ # 2.2 Minimum spacing -drc["active_to_active"] = 0.9 +drc["active_to_active"] = 3*_lambda_ # 2.3 Source/drain active to well edge -drc["well_enclosure_active"] = 1.8 +drc["well_enclosure_active"] = 6*_lambda_ # Reserved for asymmetric enclosures -drc["well_extend_active"] = 1.8 +drc["well_extend_active"] = 6*_lambda_ # Not a rule drc["minarea_active"] = 0.0 # 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width -drc["implant_to_channel"] = 0.9 +drc["implant_to_channel"] = 3*_lambda_ # 4.2 Minimum select overlap of active -drc["implant_enclosure_active"] = 0.6 +drc["implant_enclosure_active"] = 2*_lambda_ # 4.3 Minimum select overlap of contact -drc["implant_enclosure_contact"] = 0.3 +drc["implant_enclosure_contact"] = _lambda_ # Not a rule drc["implant_to_contact"] = 0 # Not a rule @@ -122,70 +123,70 @@ drc["implant_to_implant"] = 0 drc["minwidth_implant"] = 0 # 6.1 Exact contact size -drc["minwidth_contact"] = 0.6 +drc["minwidth_contact"] = 2*_lambda_ # 5.3 Minimum contact spacing -drc["contact_to_contact"] = 0.9 +drc["contact_to_contact"] = 3*_lambda_ # 6.2.b Minimum active overlap -drc["active_enclosure_contact"] = 0.3 +drc["active_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosure -drc["active_extend_contact"] = 0.3 +drc["active_extend_contact"] = _lambda_ # 5.2.b Minimum poly overlap -drc["poly_enclosure_contact"] = 0.3 +drc["poly_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosures -drc["poly_extend_contact"] = 0.3 +drc["poly_extend_contact"] = _lambda_ # Reserved for other technologies -drc["contact_to_gate"] = 0.6 +drc["contact_to_gate"] = 2*_lambda_ # 5.4 Minimum spacing to gate of transistor -drc["contact_to_poly"] = 0.6 +drc["contact_to_poly"] = 2*_lambda_ # 7.1 Minimum width -drc["minwidth_metal1"] = 0.9 +drc["minwidth_metal1"] = 3*_lambda_ # 7.2 Minimum spacing -drc["metal1_to_metal1"] = 0.9 +drc["metal1_to_metal1"] = 3*_lambda_ # 7.3 Minimum overlap of any contact -drc["metal1_enclosure_contact"] = 0.3 +drc["metal1_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosure -drc["metal1_extend_contact"] = 0.3 +drc["metal1_extend_contact"] = _lambda_ # 8.3 Minimum overlap by metal1 -drc["metal1_enclosure_via1"] = 0.3 +drc["metal1_enclosure_via1"] = _lambda_ # Reserve for asymmetric enclosures -drc["metal1_extend_via1"] = 0.3 +drc["metal1_extend_via1"] = _lambda_ # Not a rule drc["minarea_metal1"] = 0 # 8.1 Exact size -drc["minwidth_via1"] = 0.6 +drc["minwidth_via1"] = 2*_lambda_ # 8.2 Minimum via1 spacing -drc["via1_to_via1"] = 0.6 +drc["via1_to_via1"] = 2*_lambda_ # 9.1 Minimum width -drc["minwidth_metal2"] = 0.9 +drc["minwidth_metal2"] = 3*_lambda_ # 9.2 Minimum spacing -drc["metal2_to_metal2"] = 0.9 +drc["metal2_to_metal2"] = 3*_lambda_ # 9.3 Minimum overlap of via1 -drc["metal2_extend_via1"] = 0.3 +drc["metal2_extend_via1"] = _lambda_ # Reserved for asymmetric enclosures -drc["metal2_enclosure_via1"] = 0.3 +drc["metal2_enclosure_via1"] = _lambda_ # 14.3 Minimum overlap by metal2 -drc["metal2_extend_via2"] = 0.3 +drc["metal2_extend_via2"] = _lambda_ # Reserved for asymmetric enclosures -drc["metal2_enclosure_via2"] = 0.3 +drc["metal2_enclosure_via2"] = _lambda_ # Not a rule drc["minarea_metal2"] = 0 # 14.2 Exact size -drc["minwidth_via2"] = 0.6 +drc["minwidth_via2"] = 2*_lambda_ # 14.2 Minimum spacing -drc["via2_to_via2"] = 0.9 +drc["via2_to_via2"] = 3*_lambda_ # 15.1 Minimum width -drc["minwidth_metal3"] = 1.5 +drc["minwidth_metal3"] = 5*_lambda_ # 15.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 0.9 +drc["metal3_to_metal3"] = 3*_lambda_ # 15.3 Minimum overlap of via 2 -drc["metal3_extend_via2"] = 0.6 +drc["metal3_extend_via2"] = 2*_lambda_ # Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = 0.6 +drc["metal3_enclosure_via2"] = 2*_lambda_ # Not a rule drc["minarea_metal3"] = 0 From f8fc7c12b3a026b079345685217b3afc39402eb1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 11:02:28 -0700 Subject: [PATCH 02/14] Remove ms_flop and replace with dff. Might break setup_hold tests. --- compiler/characterizer/setup_hold.py | 6 +- compiler/modules/dff.py | 19 ++++ compiler/modules/ms_flop.py | 50 --------- compiler/modules/ms_flop_array.py | 136 ----------------------- technology/freepdk45/gds_lib/ms_flop.gds | Bin 40960 -> 0 bytes technology/freepdk45/sp_lib/ms_flop.sp | 29 ----- technology/scn3me_subm/layers.map | 16 --- technology/scn3me_subm/mag_lib/.magicrc | 5 +- technology/scn3me_subm/sp_lib/dff.sp | 28 +---- 9 files changed, 30 insertions(+), 259 deletions(-) delete mode 100644 compiler/modules/ms_flop.py delete mode 100644 compiler/modules/ms_flop_array.py delete mode 100644 technology/freepdk45/gds_lib/ms_flop.gds delete mode 100644 technology/freepdk45/sp_lib/ms_flop.sp delete mode 100644 technology/scn3me_subm/layers.map diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index ee35af46..eaef6bac 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -3,7 +3,7 @@ import tech from .stimuli import * import debug from .charutils import * -import ms_flop +import dff from globals import OPTS @@ -16,8 +16,8 @@ class setup_hold(): def __init__(self, corner): # This must match the spice model order self.pins = ["data", "dout", "dout_bar", "clk", "vdd", "gnd"] - self.model_name = "ms_flop" - self.model_location = OPTS.openram_tech + "sp_lib/ms_flop.sp" + self.model_name = "dff" + self.model_location = OPTS.openram_tech + "sp_lib/dff.sp" self.period = tech.spice["feasible_period"] debug.info(2,"Feasible period from technology file: {0} ".format(self.period)) diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 62e424cb..d72aae2e 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -21,6 +21,25 @@ class dff(design.design): self.height = dff.height self.pin_map = dff.pin_map + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + from tech import spice + c_eff = self.calculate_effective_capacitance(load) + f = spice["default_event_rate"] + power_dyn = c_eff*vdd*vdd*f + power_leak = spice["msflop_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + from tech import spice, parameter + c_load = load + c_para = spice["flop_para_cap"]#ff + transition_prob = spice["flop_transition_prob"] + return transition_prob*(c_load + c_para) + def analytical_delay(self, slew, load = 0.0): # dont know how to calculate this now, use constant in tech file from tech import spice diff --git a/compiler/modules/ms_flop.py b/compiler/modules/ms_flop.py deleted file mode 100644 index bb8e2ca2..00000000 --- a/compiler/modules/ms_flop.py +++ /dev/null @@ -1,50 +0,0 @@ -import globals -import design -from math import log -import design -from tech import GDS,layer -import utils - -class ms_flop(design.design): - """ - Memory address flip-flop - """ - - pin_names = ["din", "dout", "dout_bar", "clk", "vdd", "gnd"] - (width,height) = utils.get_libcell_size("ms_flop", GDS["unit"], layer["boundary"]) - pin_map = utils.get_libcell_pins(pin_names, "ms_flop", GDS["unit"], layer["boundary"]) - - def __init__(self, name="ms_flop"): - design.design.__init__(self, name) - - self.width = ms_flop.width - self.height = ms_flop.height - self.pin_map = ms_flop.pin_map - - def analytical_delay(self, slew, load = 0.0): - # dont know how to calculate this now, use constant in tech file - from tech import spice - result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"]) - return result - - def analytical_power(self, proc, vdd, temp, load): - """Returns dynamic and leakage power. Results in nW""" - from tech import spice - c_eff = self.calculate_effective_capacitance(load) - f = spice["default_event_rate"] - power_dyn = c_eff*vdd*vdd*f - power_leak = spice["msflop_leakage"] - - total_power = self.return_power(power_dyn, power_leak) - return total_power - - def calculate_effective_capacitance(self, load): - """Computes effective capacitance. Results in fF""" - from tech import spice, parameter - c_load = load - c_para = spice["flop_para_cap"]#ff - transition_prob = spice["flop_transition_prob"] - return transition_prob*(c_load + c_para) - - - \ No newline at end of file diff --git a/compiler/modules/ms_flop_array.py b/compiler/modules/ms_flop_array.py deleted file mode 100644 index 061ad9be..00000000 --- a/compiler/modules/ms_flop_array.py +++ /dev/null @@ -1,136 +0,0 @@ -import debug -import design -from tech import drc -from math import log -from vector import vector -from globals import OPTS - -class ms_flop_array(design.design): - """ - An Array of D-Flipflops used for to store Data_in & Data_out of - Write_driver & Sense_amp, address inputs of column_mux & - hierdecoder - """ - - def __init__(self, columns, word_size, name=""): - self.columns = columns - self.word_size = word_size - if name=="": - name = "flop_array_c{0}_w{1}".format(columns,word_size) - design.design.__init__(self, name) - debug.info(1, "Creating {}".format(self.name)) - - self.words_per_row = int(self.columns / self.word_size) - - self.create_netlist() - if not OPTS.netlist_only: - self.create_layout() - - def create_netlist(self): - self.add_modules() - self.add_pins() - self.create_ms_flop_array() - - def create_layout(self): - self.width = self.columns * self.ms.width - self.height = self.ms.height - - self.place_ms_flop_array() - self.add_layout_pins() - self.DRC_LVS() - - def add_modules(self): - from importlib import reload - c = reload(__import__(OPTS.ms_flop)) - self.mod_ms_flop = getattr(c, OPTS.ms_flop) - self.ms = self.mod_ms_flop("ms_flop") - self.add_mod(self.ms) - - def add_pins(self): - for i in range(self.word_size): - self.add_pin("din[{0}]".format(i)) - for i in range(self.word_size): - self.add_pin("dout[{0}]".format(i)) - self.add_pin("dout_bar[{0}]".format(i)) - self.add_pin("clk") - self.add_pin("vdd") - self.add_pin("gnd") - - def create_ms_flop_array(self): - self.ms_inst={} - for i in range(0,self.columns,self.words_per_row): - name = "Xdff{0}".format(i) - index = int(i/self.words_per_row) - self.ms_inst[index]=self.add_inst(name=name, - mod=self.ms) - self.connect_inst(["din[{0}]".format(index), - "dout[{0}]".format(index), - "dout_bar[{0}]".format(index), - "clk", - "vdd", "gnd"]) - - def place_ms_flop_array(self): - for i in range(0,self.columns,self.words_per_row): - index = int(i/self.words_per_row) - if (i % 2 == 0 or self.words_per_row>1): - base = vector(i*self.ms.width,0) - mirror = "R0" - else: - base = vector((i+1)*self.ms.width,0) - mirror = "MY" - self.ms_inst[index].place(offset=base, - mirror=mirror) - - def add_layout_pins(self): - - for i in range(self.word_size): - - # Route both supplies - for n in ["vdd", "gnd"]: - for supply_pin in self.ms_inst[i].get_pins(n): - pin_pos = supply_pin.center() - self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=pin_pos) - self.add_layout_pin_rect_center(text=n, - layer="metal3", - offset=pin_pos) - - - din_pins = self.ms_inst[i].get_pins("din") - for din_pin in din_pins: - self.add_layout_pin(text="din[{}]".format(i), - layer=din_pin.layer, - offset=din_pin.ll(), - width=din_pin.width(), - height=din_pin.height()) - - dout_pin = self.ms_inst[i].get_pin("dout") - self.add_layout_pin(text="dout[{}]".format(i), - layer="metal2", - offset=dout_pin.ll(), - width=dout_pin.width(), - height=dout_pin.height()) - - doutbar_pin = self.ms_inst[i].get_pin("dout_bar") - self.add_layout_pin(text="dout_bar[{}]".format(i), - layer="metal2", - offset=doutbar_pin.ll(), - width=doutbar_pin.width(), - height=doutbar_pin.height()) - - - # Continous clk rail along with label. - self.add_layout_pin(text="clk", - layer="metal1", - offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1), - width=self.width, - height=drc["minwidth_metal1"]) - - - - - - - def analytical_delay(self, slew, load=0.0): - return self.ms.analytical_delay(slew=slew, load=load) - diff --git a/technology/freepdk45/gds_lib/ms_flop.gds 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-mtmP1 din clk int1 vdd PMOS_VTG W=180.0n L=50n m=1 -mtmN1 din clk_bar int1 gnd NMOS_VTG W=90n L=50n m=1 - -*foward inverter -mPff3 dout_bar int1 vdd vdd PMOS_VTG W=180.0n L=50n m=1 -mNff3 dout_bar int1 gnd gnd NMOS_VTG W=90n L=50n m=1 - -*backward inverter -mPff4 dout dout_bar vdd vdd PMOS_VTG W=180.0n L=50n m=1 -mNf4 dout dout_bar gnd gnd NMOS_VTG W=90n L=50n m=1 - -*transmission gate 2 -mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1 -mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1 -.ENDS dlatch - -.SUBCKT ms_flop din dout dout_bar clk vdd gnd -xmaster din mout mout_bar clk clk_bar vdd gnd dlatch -xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch -.ENDS flop - diff --git a/technology/scn3me_subm/layers.map b/technology/scn3me_subm/layers.map deleted file mode 100644 index d10d5f2d..00000000 --- a/technology/scn3me_subm/layers.map +++ /dev/null @@ -1,16 +0,0 @@ -Pwell drawing 41 0 -Nwell drawing 42 0 -Active drawing 43 0 -Poly1 drawing 46 0 -Pselect drawing 45 0 -Nselect drawing 44 0 -contact drawing 25 0 -P1Con drawing 47 0 -ActX drawing 48 0 -Metal1 drawing 49 0 -Via drawing 50 0 -Metal2 drawing 51 0 -Via2 drawing 61 0 -Metal3 drawing 62 0 -Glass drawing 52 0 -text drawing 83 0 diff --git a/technology/scn3me_subm/mag_lib/.magicrc b/technology/scn3me_subm/mag_lib/.magicrc index d6068ec3..f52d0592 100644 --- a/technology/scn3me_subm/mag_lib/.magicrc +++ b/technology/scn3me_subm/mag_lib/.magicrc @@ -1,2 +1,5 @@ path sys +$::env(OPENRAM_TECH)/scn3me_subm/tech -tech load SCN3ME_SUBM.30 +tech load SCN3ME_SUBM.30 -noprompt +scalegrid 1 4 +set GND gnd +set VDD vdd diff --git a/technology/scn3me_subm/sp_lib/dff.sp b/technology/scn3me_subm/sp_lib/dff.sp index 61515ab6..d3fa7635 100644 --- a/technology/scn3me_subm/sp_lib/dff.sp +++ b/technology/scn3me_subm/sp_lib/dff.sp @@ -1,47 +1,27 @@ +*********************** "dff" ****************************** * Positive edge-triggered FF -.subckt dff D Q clk vdd gnd +.SUBCKT dff D Q clk vdd gnd M0 vdd clk a_2_6# vdd p w=12u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd p w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M10 gnd clk a_2_6# gnd n w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd p w=12u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd gnd n w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u -.ends dff + +.ENDS dff From 6ab4f5363aec9db5f10399bc6fb5cef1238f420c Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 11:03:35 -0700 Subject: [PATCH 03/14] Initial scn4me_subm cells and rules. --- technology/scn4me_subm/gds_lib/cell_6t.gds | Bin 0 -> 5660 bytes technology/scn4me_subm/gds_lib/dff.gds | Bin 0 -> 16558 bytes .../scn4me_subm/gds_lib/replica_cell_6t.gds | Bin 0 -> 5804 bytes technology/scn4me_subm/gds_lib/sense_amp.gds | Bin 0 -> 8248 bytes technology/scn4me_subm/gds_lib/tri_gate.gds | Bin 0 -> 4512 bytes .../scn4me_subm/gds_lib/write_driver.gds | Bin 0 -> 11740 bytes technology/scn4me_subm/mag_lib/.magicrc | 5 + technology/scn4me_subm/mag_lib/cell_6t.mag | 117 + technology/scn4me_subm/mag_lib/dff.mag | 279 + .../scn4me_subm/mag_lib/replica_cell_6t.mag | 118 + technology/scn4me_subm/mag_lib/sense_amp.mag | 136 + technology/scn4me_subm/mag_lib/tri_gate.mag | 98 + .../scn4me_subm/mag_lib/write_driver.mag | 224 + technology/scn4me_subm/models/ff/nmos.sp | 10 + technology/scn4me_subm/models/ff/pmos.sp | 9 + technology/scn4me_subm/models/nom/nmos.sp | 9 + technology/scn4me_subm/models/nom/pmos.sp | 9 + technology/scn4me_subm/models/ss/nmos.sp | 10 + technology/scn4me_subm/models/ss/pmos.sp | 9 + technology/scn4me_subm/sp_lib/cell_6t.sp | 13 + technology/scn4me_subm/sp_lib/dff.sp | 30 + .../scn4me_subm/sp_lib/replica_cell_6t.sp | 14 + technology/scn4me_subm/sp_lib/sense_amp.sp | 15 + technology/scn4me_subm/sp_lib/tri_gate.sp | 14 + technology/scn4me_subm/sp_lib/write_driver.sp | 23 + technology/scn4me_subm/sue_lib/cell_6t.sue | 46 + technology/scn4me_subm/sue_lib/ms_flop.sue | 84 + .../scn4me_subm/sue_lib/replica_cell_6t.sue | 49 + technology/scn4me_subm/sue_lib/sense_amp.sue | 52 + technology/scn4me_subm/sue_lib/tri_gate.sue | 37 + .../scn4me_subm/sue_lib/write_driver.sue | 44 + technology/scn4me_subm/tech/LICENSE.txt | 10 + .../scn4me_subm/tech/SCN4M_SUBM.20.tech | 10329 ++++++++++++++++ technology/scn4me_subm/tech/__init__.py | 6 + technology/scn4me_subm/tech/tech.py | 295 + technology/scn4me_subm/tf/LICENSE | 4 + technology/scn4me_subm/tf/README | 21 + technology/scn4me_subm/tf/display.drf | 717 ++ .../scn4me_subm/tf/glade_scn4me_subm.py | 7 + technology/scn4me_subm/tf/layers.map | 18 + technology/scn4me_subm/tf/mosis.tf | 850 ++ 41 files changed, 13711 insertions(+) create mode 100644 technology/scn4me_subm/gds_lib/cell_6t.gds create mode 100644 technology/scn4me_subm/gds_lib/dff.gds create mode 100644 technology/scn4me_subm/gds_lib/replica_cell_6t.gds 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0 HcmV?d00001 diff --git a/technology/scn4me_subm/mag_lib/.magicrc b/technology/scn4me_subm/mag_lib/.magicrc new file mode 100644 index 00000000..2778c5e7 --- /dev/null +++ b/technology/scn4me_subm/mag_lib/.magicrc @@ -0,0 +1,5 @@ +path sys +$::env(OPENRAM_TECH)/scn4me_subm/tech +tech load SCN4ME_SUBM.20 -noprompt +scalegrid 1 4 +set GND gnd +set VDD vdd diff --git a/technology/scn4me_subm/mag_lib/cell_6t.mag b/technology/scn4me_subm/mag_lib/cell_6t.mag new file mode 100644 index 00000000..f2e9906a --- /dev/null +++ b/technology/scn4me_subm/mag_lib/cell_6t.mag @@ -0,0 +1,117 @@ +magic +tech scmos +timestamp 1536091415 +<< nwell >> +rect -8 29 42 51 +<< pwell >> +rect -8 -8 42 29 +<< ntransistor >> +rect 7 10 9 18 +rect 29 10 31 18 +rect 10 3 14 5 +rect 24 3 28 5 +<< ptransistor >> +rect 7 37 11 40 +rect 27 37 31 40 +<< ndiffusion >> +rect -2 16 7 18 +rect 2 12 7 16 +rect -2 10 7 12 +rect 9 14 10 18 +rect 9 10 14 14 +rect 28 14 29 18 +rect 24 10 29 14 +rect 31 16 36 18 +rect 31 12 32 16 +rect 31 10 36 12 +rect 10 5 14 10 +rect 24 5 28 10 +rect 10 2 14 3 +rect 24 2 28 3 +<< pdiffusion >> +rect 2 37 7 40 +rect 11 37 12 40 +rect 26 37 27 40 +rect 31 37 32 40 +<< ndcontact >> +rect -2 12 2 16 +rect 10 14 14 18 +rect 24 14 28 18 +rect 32 12 36 16 +rect 10 -2 14 2 +rect 24 -2 28 2 +<< pdcontact >> +rect -2 36 2 40 +rect 12 36 16 40 +rect 22 36 26 40 +rect 32 36 36 40 +<< psubstratepcontact >> +rect -2 22 2 26 +rect 32 22 36 26 +<< nsubstratencontact >> +rect 32 44 36 48 +<< polysilicon >> +rect 7 40 11 42 +rect 27 40 31 42 +rect 7 35 11 37 +rect 7 21 9 35 +rect 27 34 31 37 +rect 15 33 31 34 +rect 19 32 31 33 +rect 7 20 21 21 +rect 7 19 24 20 +rect 7 18 9 19 +rect 29 18 31 32 +rect 7 8 9 10 +rect 17 5 21 6 +rect 29 8 31 10 +rect -2 3 10 5 +rect 14 3 24 5 +rect 28 3 36 5 +<< polycontact >> +rect 15 29 19 33 +rect 21 20 25 24 +rect 17 6 21 10 +<< metal1 >> +rect -2 44 15 48 +rect 19 44 32 48 +rect -2 40 2 44 +rect 32 40 36 44 +rect 11 36 12 40 +rect 26 36 27 40 +rect -2 26 2 29 +rect -2 16 2 22 +rect 11 18 15 36 +rect 23 24 27 36 +rect 25 20 27 24 +rect 14 14 15 18 +rect 23 18 27 20 +rect 32 26 36 29 +rect 23 14 24 18 +rect 32 16 36 22 +rect -2 6 17 9 +rect 21 6 36 9 +rect -2 5 36 6 +<< m2contact >> +rect 15 44 19 48 +rect -2 29 2 33 +rect 32 29 36 33 +rect 6 -2 10 2 +rect 20 -2 24 2 +<< metal2 >> +rect -2 33 2 48 +rect -2 -2 2 29 +rect 6 2 10 48 +rect 24 -2 28 48 +rect 32 33 36 48 +rect 32 -2 36 29 +<< bb >> +rect 0 0 34 46 +<< labels >> +rlabel metal2 0 0 0 0 1 gnd +rlabel metal2 34 0 34 0 1 gnd +rlabel m2contact 17 46 17 46 5 vdd +rlabel metal2 8 43 8 43 1 bl +rlabel metal2 26 43 26 43 1 br +rlabel metal1 4 7 4 7 1 wl +<< end >> diff --git a/technology/scn4me_subm/mag_lib/dff.mag b/technology/scn4me_subm/mag_lib/dff.mag new file mode 100644 index 00000000..46d22c84 --- /dev/null +++ b/technology/scn4me_subm/mag_lib/dff.mag @@ -0,0 +1,279 @@ +magic +tech scmos +timestamp 1536089597 +<< nwell >> +rect 0 48 109 103 +<< pwell >> +rect 0 -3 109 48 +<< ntransistor >> +rect 11 6 13 26 +rect 19 6 21 16 +rect 24 6 26 16 +rect 33 6 35 16 +rect 38 6 40 16 +rect 47 6 49 16 +rect 63 6 65 16 +rect 68 6 70 16 +rect 78 6 80 16 +rect 83 6 85 16 +rect 91 6 93 26 +<< ptransistor >> +rect 11 54 13 94 +rect 19 74 21 94 +rect 25 74 27 94 +rect 33 74 35 94 +rect 39 74 41 94 +rect 47 74 49 94 +rect 63 74 65 94 +rect 68 74 70 94 +rect 78 84 80 94 +rect 83 84 85 94 +rect 91 54 93 94 +<< ndiffusion >> +rect 6 25 11 26 +rect 10 6 11 25 +rect 13 25 18 26 +rect 13 6 14 25 +rect 86 25 91 26 +rect 18 6 19 16 +rect 21 6 24 16 +rect 26 15 33 16 +rect 26 6 28 15 +rect 32 6 33 15 +rect 35 6 38 16 +rect 40 15 47 16 +rect 40 6 41 15 +rect 45 6 47 15 +rect 49 15 54 16 +rect 49 6 50 15 +rect 58 15 63 16 +rect 62 6 63 15 +rect 65 6 68 16 +rect 70 15 78 16 +rect 70 6 72 15 +rect 76 6 78 15 +rect 80 6 83 16 +rect 85 6 86 16 +rect 90 6 91 25 +rect 93 25 98 26 +rect 93 6 94 25 +<< pdiffusion >> +rect 6 93 11 94 +rect 10 54 11 93 +rect 13 55 14 94 +rect 18 74 19 94 +rect 21 74 25 94 +rect 27 93 33 94 +rect 27 74 28 93 +rect 32 74 33 93 +rect 35 74 39 94 +rect 41 93 47 94 +rect 41 74 42 93 +rect 46 74 47 93 +rect 49 93 54 94 +rect 49 74 50 93 +rect 58 93 63 94 +rect 62 74 63 93 +rect 65 74 68 94 +rect 70 93 78 94 +rect 70 74 72 93 +rect 76 84 78 93 +rect 80 84 83 94 +rect 85 93 91 94 +rect 85 84 86 93 +rect 76 74 77 84 +rect 13 54 18 55 +rect 90 54 91 93 +rect 93 93 98 94 +rect 93 54 94 93 +<< ndcontact >> +rect 6 6 10 25 +rect 14 6 18 25 +rect 28 6 32 15 +rect 41 6 45 15 +rect 50 6 54 15 +rect 58 6 62 15 +rect 72 6 76 15 +rect 86 6 90 25 +rect 94 6 98 25 +<< pdcontact >> +rect 6 54 10 93 +rect 14 55 18 94 +rect 28 74 32 93 +rect 42 74 46 93 +rect 50 74 54 93 +rect 58 74 62 93 +rect 72 74 76 93 +rect 86 54 90 93 +rect 94 54 98 93 +<< psubstratepcontact >> +rect 102 6 106 10 +<< nsubstratencontact >> +rect 102 89 106 93 +<< polysilicon >> +rect 11 94 13 96 +rect 19 94 21 96 +rect 25 94 27 96 +rect 33 94 35 96 +rect 39 94 41 96 +rect 47 94 49 96 +rect 63 94 65 96 +rect 68 94 70 96 +rect 78 94 80 96 +rect 83 94 85 96 +rect 91 94 93 96 +rect 11 37 13 54 +rect 19 46 21 74 +rect 11 26 13 33 +rect 19 16 21 42 +rect 25 38 27 74 +rect 33 54 35 74 +rect 33 29 35 50 +rect 24 27 35 29 +rect 39 71 41 74 +rect 24 16 26 27 +rect 39 23 41 67 +rect 47 61 49 74 +rect 63 73 65 74 +rect 54 71 65 73 +rect 34 19 35 23 +rect 33 16 35 19 +rect 38 19 39 23 +rect 38 16 40 19 +rect 47 16 49 57 +rect 53 19 55 67 +rect 68 63 70 74 +rect 78 67 80 84 +rect 76 65 80 67 +rect 63 61 70 63 +rect 61 24 63 33 +rect 68 31 70 61 +rect 83 53 85 84 +rect 79 51 85 53 +rect 78 31 80 47 +rect 91 45 93 54 +rect 89 41 93 45 +rect 68 29 75 31 +rect 61 22 70 24 +rect 53 17 65 19 +rect 63 16 65 17 +rect 68 16 70 22 +rect 73 19 75 29 +rect 78 27 79 31 +rect 73 17 80 19 +rect 78 16 80 17 +rect 83 16 85 31 +rect 91 26 93 41 +rect 11 4 13 6 +rect 19 4 21 6 +rect 24 4 26 6 +rect 33 4 35 6 +rect 38 4 40 6 +rect 47 4 49 6 +rect 63 4 65 6 +rect 68 4 70 6 +rect 78 4 80 6 +rect 83 4 85 6 +rect 91 4 93 6 +<< polycontact >> +rect 17 42 21 46 +rect 10 33 14 37 +rect 31 50 35 54 +rect 25 34 29 38 +rect 39 67 43 71 +rect 45 57 49 61 +rect 30 19 34 23 +rect 39 19 43 23 +rect 53 67 57 71 +rect 59 59 63 63 +rect 74 61 78 65 +rect 59 33 63 37 +rect 77 47 81 51 +rect 85 41 89 45 +rect 79 27 83 31 +<< metal1 >> +rect 0 97 109 103 +rect 14 94 18 97 +rect 6 93 10 94 +rect 28 93 32 94 +rect 22 74 28 77 +rect 42 93 46 97 +rect 50 93 54 94 +rect 58 93 62 97 +rect 71 93 77 94 +rect 71 74 72 93 +rect 76 74 77 93 +rect 86 93 90 97 +rect 50 71 53 74 +rect 43 68 53 71 +rect 26 57 45 60 +rect 52 60 59 63 +rect 52 54 55 60 +rect 71 56 74 65 +rect 10 50 31 52 +rect 35 51 55 54 +rect 62 53 74 56 +rect 94 93 98 94 +rect 102 93 106 97 +rect 6 49 34 50 +rect 21 43 38 46 +rect 18 34 25 37 +rect 62 37 65 53 +rect 94 51 98 54 +rect 81 48 94 51 +rect 74 41 85 44 +rect 29 34 59 37 +rect 6 25 10 26 +rect 14 25 18 26 +rect 31 23 34 34 +rect 63 34 65 37 +rect 94 31 98 47 +rect 83 28 98 31 +rect 94 25 98 28 +rect 43 19 53 22 +rect 50 16 53 19 +rect 22 15 32 16 +rect 22 13 28 15 +rect 41 15 46 16 +rect 45 6 46 15 +rect 50 15 54 16 +rect 58 15 62 16 +rect 70 15 77 16 +rect 70 13 72 15 +rect 71 6 72 13 +rect 76 6 77 15 +rect 14 3 18 6 +rect 41 3 46 6 +rect 58 3 62 6 +rect 86 3 90 6 +rect 102 3 106 6 +rect 0 -3 109 3 +<< m2contact >> +rect 22 70 26 74 +rect 70 70 74 74 +rect 22 57 26 61 +rect 6 50 10 54 +rect 38 43 42 47 +rect 14 33 18 37 +rect 94 47 98 51 +rect 70 40 74 44 +rect 6 26 10 30 +rect 22 16 26 20 +rect 70 16 74 20 +<< metal2 >> +rect 22 61 26 70 +rect 6 30 10 50 +rect 22 20 26 57 +rect 70 44 74 70 +rect 70 20 74 40 +<< bb >> +rect 0 0 109 100 +<< labels >> +rlabel m2contact 15 34 15 34 4 clk +rlabel m2contact 40 45 40 45 4 D +rlabel m2contact 96 49 96 49 4 Q +rlabel metal1 32 98 32 98 4 vdd +rlabel metal1 44 1 44 1 4 gnd +<< properties >> +string path 0.000 0.000 900.000 0.000 900.000 900.000 0.000 900.000 0.000 0.000 +<< end >> diff --git a/technology/scn4me_subm/mag_lib/replica_cell_6t.mag b/technology/scn4me_subm/mag_lib/replica_cell_6t.mag new file mode 100644 index 00000000..d0dc472f --- /dev/null +++ b/technology/scn4me_subm/mag_lib/replica_cell_6t.mag @@ -0,0 +1,118 @@ +magic +tech scmos +timestamp 1536091380 +<< nwell >> +rect -8 29 42 51 +<< pwell >> +rect -8 -8 42 29 +<< ntransistor >> +rect 7 10 9 18 +rect 29 10 31 18 +rect 10 3 14 5 +rect 24 3 28 5 +<< ptransistor >> +rect 7 37 11 40 +rect 27 37 31 40 +<< ndiffusion >> +rect -2 16 7 18 +rect 2 12 7 16 +rect -2 10 7 12 +rect 9 14 10 18 +rect 9 10 14 14 +rect 28 14 29 18 +rect 24 10 29 14 +rect 31 16 36 18 +rect 31 12 32 16 +rect 31 10 36 12 +rect 10 5 14 10 +rect 24 5 28 10 +rect 10 2 14 3 +rect 24 2 28 3 +<< pdiffusion >> +rect 2 37 7 40 +rect 11 37 12 40 +rect 26 37 27 40 +rect 31 37 32 40 +<< ndcontact >> +rect -2 12 2 16 +rect 10 14 14 18 +rect 24 14 28 18 +rect 32 12 36 16 +rect 10 -2 14 2 +rect 24 -2 28 2 +<< pdcontact >> +rect -2 36 2 40 +rect 12 36 16 40 +rect 22 36 26 40 +rect 32 36 36 40 +<< psubstratepcontact >> +rect -2 22 2 26 +rect 32 22 36 26 +<< nsubstratencontact >> +rect 32 44 36 48 +<< polysilicon >> +rect 7 40 11 42 +rect 27 40 31 42 +rect 7 35 11 37 +rect 7 21 9 35 +rect 27 34 31 37 +rect 15 33 31 34 +rect 19 32 31 33 +rect 7 20 21 21 +rect 7 19 24 20 +rect 7 18 9 19 +rect 29 18 31 32 +rect 7 8 9 10 +rect 17 5 21 6 +rect 29 8 31 10 +rect -2 3 10 5 +rect 14 3 24 5 +rect 28 3 36 5 +<< polycontact >> +rect 15 29 19 33 +rect 21 20 25 24 +rect 17 6 21 10 +<< metal1 >> +rect -2 44 15 48 +rect 19 44 32 48 +rect -2 40 2 44 +rect 32 40 36 44 +rect 11 36 12 40 +rect 26 36 27 40 +rect -2 26 2 29 +rect 11 22 15 36 +rect 23 24 27 36 +rect -2 18 15 22 +rect 25 20 27 24 +rect -2 16 2 18 +rect 14 14 15 18 +rect 23 18 27 20 +rect 32 26 36 29 +rect 23 14 24 18 +rect 32 16 36 22 +rect -2 6 17 9 +rect 21 6 36 9 +rect -2 5 36 6 +<< m2contact >> +rect 15 44 19 48 +rect -2 29 2 33 +rect 32 29 36 33 +rect 6 -2 10 2 +rect 20 -2 24 2 +<< metal2 >> +rect -2 33 2 48 +rect -2 -2 2 29 +rect 6 2 10 48 +rect 24 -2 28 48 +rect 32 33 36 48 +rect 32 -2 36 29 +<< bb >> +rect 0 0 34 46 +<< labels >> +rlabel metal2 0 0 0 0 1 gnd +rlabel metal2 34 0 34 0 1 gnd +rlabel m2contact 17 46 17 46 5 vdd +rlabel metal2 8 43 8 43 1 bl +rlabel metal2 26 43 26 43 1 br +rlabel metal1 4 7 4 7 1 wl +<< end >> diff --git a/technology/scn4me_subm/mag_lib/sense_amp.mag b/technology/scn4me_subm/mag_lib/sense_amp.mag new file mode 100644 index 00000000..e5fa4373 --- /dev/null +++ b/technology/scn4me_subm/mag_lib/sense_amp.mag @@ -0,0 +1,136 @@ +magic +tech scmos +timestamp 1536089670 +<< nwell >> +rect 0 0 40 102 +<< pwell >> +rect 0 102 40 163 +<< ntransistor >> +rect 21 130 23 139 +rect 12 108 14 117 +rect 20 108 22 117 +<< ptransistor >> +rect 12 78 14 96 +rect 20 78 22 96 +rect 11 20 13 44 +rect 27 20 29 44 +<< ndiffusion >> +rect 20 130 21 139 +rect 23 130 24 139 +rect 11 108 12 117 +rect 14 108 15 117 +rect 19 108 20 117 +rect 22 108 23 117 +<< pdiffusion >> +rect 7 94 12 96 +rect 11 80 12 94 +rect 7 78 12 80 +rect 14 94 20 96 +rect 14 80 15 94 +rect 19 80 20 94 +rect 14 78 20 80 +rect 22 94 27 96 +rect 22 80 23 94 +rect 22 78 27 80 +rect 10 20 11 44 +rect 13 20 14 44 +rect 26 20 27 44 +rect 29 20 30 44 +<< ndcontact >> +rect 16 130 20 139 +rect 24 130 28 139 +rect 7 108 11 117 +rect 15 108 19 117 +rect 23 108 27 117 +<< pdcontact >> +rect 7 80 11 94 +rect 15 80 19 94 +rect 23 80 27 94 +rect 6 20 10 44 +rect 14 20 18 44 +rect 22 20 26 44 +rect 30 20 34 44 +<< psubstratepcontact >> +rect 32 137 36 141 +<< nsubstratencontact >> +rect 27 70 31 74 +<< polysilicon >> +rect 21 139 23 149 +rect 21 129 23 130 +rect 3 127 23 129 +rect 3 47 5 127 +rect 12 122 34 124 +rect 12 117 14 122 +rect 20 117 22 119 +rect 12 96 14 108 +rect 20 96 22 108 +rect 32 105 34 122 +rect 30 101 34 105 +rect 12 76 14 78 +rect 20 69 22 78 +rect 13 67 22 69 +rect 9 55 11 65 +rect 32 55 34 101 +rect 33 51 34 55 +rect 3 45 13 47 +rect 11 44 13 45 +rect 27 44 29 46 +rect 11 19 13 20 +rect 27 19 29 20 +rect 11 17 29 19 +<< polycontact >> +rect 20 149 24 153 +rect 26 101 30 105 +rect 9 65 13 69 +rect 9 51 13 55 +rect 29 51 33 55 +<< metal1 >> +rect -2 149 20 153 +rect 24 149 36 153 +rect 28 133 32 137 +rect 16 117 19 130 +rect 7 94 11 108 +rect 23 105 27 108 +rect 23 101 26 105 +rect 7 69 11 80 +rect 15 94 19 96 +rect 15 78 19 80 +rect 23 94 27 101 +rect 23 78 27 80 +rect 15 75 18 78 +rect 15 74 31 75 +rect 15 72 27 74 +rect 7 65 9 69 +rect 6 44 9 54 +rect 33 51 34 55 +rect 31 44 34 51 +rect 3 20 6 23 +rect 3 15 7 20 +<< m2contact >> +rect 32 133 36 137 +rect 27 66 31 70 +rect 13 44 17 48 +rect 22 44 26 48 +rect 3 11 7 15 +<< metal2 >> +rect 10 48 14 163 +rect 20 48 24 163 +rect 32 129 36 133 +rect 27 62 31 66 +rect 10 44 13 48 +rect 20 44 22 48 +rect 3 0 7 11 +rect 10 0 14 44 +rect 20 0 24 44 +<< bb >> +rect 0 0 34 163 +<< labels >> +flabel metal1 0 149 0 149 4 FreeSans 26 0 0 0 en +rlabel metal2 34 131 34 131 1 gnd +rlabel metal2 29 64 29 64 1 vdd +rlabel metal2 12 161 12 161 5 bl +rlabel metal2 22 161 22 161 5 br +rlabel metal2 5 3 5 3 1 dout +<< properties >> +string path 270.000 468.000 270.000 486.000 288.000 486.000 288.000 468.000 270.000 468.000 +<< end >> diff --git a/technology/scn4me_subm/mag_lib/tri_gate.mag b/technology/scn4me_subm/mag_lib/tri_gate.mag new file mode 100644 index 00000000..bda635c7 --- /dev/null +++ b/technology/scn4me_subm/mag_lib/tri_gate.mag @@ -0,0 +1,98 @@ +magic +tech scmos +timestamp 1536089695 +<< nwell >> +rect -2 45 38 73 +<< pwell >> +rect -2 0 38 45 +<< ntransistor >> +rect 9 27 11 31 +rect 17 27 19 31 +rect 25 27 27 31 +<< ptransistor >> +rect 9 53 11 61 +rect 17 53 19 61 +rect 25 53 27 61 +<< ndiffusion >> +rect 8 27 9 31 +rect 11 27 12 31 +rect 16 27 17 31 +rect 19 27 20 31 +rect 24 27 25 31 +rect 27 27 28 31 +<< pdiffusion >> +rect 8 53 9 61 +rect 11 53 12 61 +rect 16 53 17 61 +rect 19 53 20 61 +rect 24 53 25 61 +rect 27 53 28 61 +<< ndcontact >> +rect 4 27 8 31 +rect 12 27 16 31 +rect 20 27 24 31 +rect 28 27 32 31 +<< pdcontact >> +rect 4 53 8 61 +rect 12 53 16 61 +rect 20 53 24 61 +rect 28 53 32 61 +<< psubstratepcontact >> +rect 12 19 16 23 +<< nsubstratencontact >> +rect 12 65 16 69 +<< polysilicon >> +rect 25 63 35 65 +rect 9 61 11 63 +rect 17 61 19 63 +rect 25 61 27 63 +rect 9 50 11 53 +rect 9 31 11 46 +rect 17 42 19 53 +rect 25 51 27 53 +rect 17 31 19 38 +rect 25 31 27 33 +rect 9 25 11 27 +rect 17 25 19 27 +rect 25 16 27 27 +rect 33 8 35 63 +rect 32 6 35 8 +<< polycontact >> +rect 9 46 13 50 +rect 16 38 20 42 +rect 25 12 29 16 +rect 28 4 32 8 +<< metal1 >> +rect 16 65 23 69 +rect 12 61 16 65 +rect 3 53 4 61 +rect 3 42 6 53 +rect 13 46 15 50 +rect 3 38 16 42 +rect 3 31 6 38 +rect 29 31 32 53 +rect 3 27 4 31 +rect 12 23 16 27 +rect 16 19 24 23 +rect 0 12 25 16 +rect 29 12 36 16 +rect 0 4 28 8 +rect 32 4 36 8 +<< m2contact >> +rect 23 65 27 69 +rect 15 46 19 50 +rect 25 34 29 38 +rect 24 19 28 23 +<< metal2 >> +rect 15 34 25 38 +rect 15 0 19 34 +<< bb >> +rect 0 0 34 73 +<< labels >> +rlabel metal1 0 12 0 12 3 en +rlabel metal1 0 4 0 4 2 en_bar +rlabel metal2 16 1 16 1 1 out +rlabel m2contact 26 21 26 21 1 gnd +rlabel m2contact 25 67 25 67 1 vdd +rlabel m2contact 17 48 17 48 1 in +<< end >> diff --git a/technology/scn4me_subm/mag_lib/write_driver.mag b/technology/scn4me_subm/mag_lib/write_driver.mag new file mode 100644 index 00000000..ab2014aa --- /dev/null +++ b/technology/scn4me_subm/mag_lib/write_driver.mag @@ -0,0 +1,224 @@ +magic +tech scmos +timestamp 1536089714 +<< nwell >> +rect -3 101 37 138 +rect -3 0 37 51 +<< pwell >> +rect -3 138 37 202 +rect -3 51 37 101 +<< ntransistor >> +rect 9 177 11 189 +rect 17 177 19 189 +rect 15 162 27 164 +rect 9 144 11 148 +rect 17 144 19 148 +rect 10 82 12 89 +rect 18 82 20 89 +rect 8 57 10 64 +rect 16 57 18 64 +rect 24 60 26 64 +<< ptransistor >> +rect 9 125 11 132 +rect 17 125 19 132 +rect 10 107 12 114 +rect 18 107 20 114 +rect 8 38 10 45 +rect 16 38 18 45 +rect 24 38 26 45 +<< ndiffusion >> +rect 8 177 9 189 +rect 11 177 12 189 +rect 16 177 17 189 +rect 19 177 20 189 +rect 15 164 27 165 +rect 15 161 27 162 +rect 12 157 15 160 +rect 12 156 16 157 +rect 8 144 9 148 +rect 11 144 12 148 +rect 16 144 17 148 +rect 19 144 20 148 +rect 9 82 10 89 +rect 12 82 13 89 +rect 17 82 18 89 +rect 20 82 21 89 +rect 25 82 26 86 +rect 7 57 8 64 +rect 10 57 11 64 +rect 15 57 16 64 +rect 18 57 19 64 +rect 23 60 24 64 +rect 26 60 27 64 +<< pdiffusion >> +rect 8 125 9 132 +rect 11 125 12 132 +rect 16 125 17 132 +rect 19 125 20 132 +rect 12 122 16 125 +rect 9 107 10 114 +rect 12 107 13 114 +rect 17 107 18 114 +rect 20 107 21 114 +rect 7 38 8 45 +rect 10 38 11 45 +rect 15 38 16 45 +rect 18 38 19 45 +rect 23 38 24 45 +rect 26 38 27 45 +rect 3 35 7 38 +<< ndcontact >> +rect 4 177 8 189 +rect 12 177 16 189 +rect 20 177 24 189 +rect 15 165 27 169 +rect 15 157 27 161 +rect 4 144 8 148 +rect 12 144 16 148 +rect 20 144 24 148 +rect 5 82 9 89 +rect 13 82 17 89 +rect 21 82 25 89 +rect 3 57 7 64 +rect 11 57 15 64 +rect 19 57 23 64 +rect 27 60 31 64 +<< pdcontact >> +rect 4 125 8 132 +rect 12 125 16 132 +rect 20 125 24 132 +rect 5 107 9 114 +rect 13 107 17 114 +rect 21 107 25 114 +rect 3 38 7 45 +rect 11 38 15 45 +rect 19 38 23 45 +rect 27 38 31 45 +<< psubstratepcontact >> +rect 12 152 16 156 +rect 26 82 30 86 +<< nsubstratencontact >> +rect 12 118 16 122 +rect 3 31 7 35 +<< polysilicon >> +rect 9 194 30 196 +rect 9 189 11 194 +rect 17 189 19 191 +rect 28 185 30 194 +rect 9 175 11 177 +rect 17 172 19 177 +rect 6 170 19 172 +rect 6 167 8 170 +rect 13 162 15 164 +rect 27 162 33 164 +rect 9 148 11 150 +rect 17 148 19 150 +rect 9 132 11 144 +rect 17 132 19 144 +rect 9 124 11 125 +rect 2 122 11 124 +rect 17 124 19 125 +rect 17 122 28 124 +rect 2 75 4 122 +rect 10 114 12 116 +rect 18 114 20 116 +rect 10 89 12 107 +rect 18 106 20 107 +rect 16 104 20 106 +rect 16 92 18 104 +rect 26 100 28 122 +rect 27 96 28 100 +rect 16 90 20 92 +rect 18 89 20 90 +rect 10 81 12 82 +rect 10 79 13 81 +rect 2 71 3 75 +rect 11 71 13 79 +rect 18 79 20 82 +rect 18 77 23 79 +rect 31 71 33 162 +rect 11 69 33 71 +rect 11 67 13 69 +rect 8 65 13 67 +rect 8 64 10 65 +rect 16 64 18 66 +rect 24 64 26 66 +rect 8 45 10 57 +rect 16 52 18 57 +rect 24 52 26 60 +rect 16 50 26 52 +rect 16 45 18 50 +rect 24 45 26 50 +rect 8 28 10 38 +rect 16 14 18 38 +rect 24 36 26 38 +<< polycontact >> +rect 28 181 32 185 +rect 4 163 8 167 +rect 23 96 27 100 +rect 3 71 7 75 +rect 23 75 27 79 +rect 7 24 11 28 +rect 15 10 19 14 +<< metal1 >> +rect 5 192 10 196 +rect 5 189 8 192 +rect 32 181 33 185 +rect 13 169 16 177 +rect 13 165 15 169 +rect 4 148 8 163 +rect 12 157 15 161 +rect 12 156 16 157 +rect 12 148 16 152 +rect 4 132 8 144 +rect 20 142 24 144 +rect 30 142 33 181 +rect 20 138 33 142 +rect 20 132 24 138 +rect 12 122 16 125 +rect 13 114 17 118 +rect 5 104 9 107 +rect 21 104 25 107 +rect 5 101 25 104 +rect 5 89 9 101 +rect 21 100 25 101 +rect 21 96 23 100 +rect 25 82 26 90 +rect 4 64 7 71 +rect 27 64 31 79 +rect 3 51 7 57 +rect 3 48 15 51 +rect 11 45 15 48 +rect 27 45 31 60 +rect 3 35 7 38 +rect 19 35 23 38 +rect 7 31 19 35 +rect 0 24 7 28 +rect 11 24 36 28 +<< m2contact >> +rect 10 192 14 196 +rect 20 189 24 193 +rect 23 153 27 157 +rect 16 118 20 122 +rect 26 86 30 90 +rect 19 64 23 68 +rect 19 31 23 35 +rect 15 6 19 10 +<< metal2 >> +rect 10 196 14 202 +rect 20 193 24 202 +rect 20 177 24 189 +rect 15 0 19 6 +<< bb >> +rect 0 0 34 202 +<< labels >> +rlabel metal2 15 1 15 1 1 din +rlabel metal1 2 25 2 25 3 en +rlabel metal2 12 200 12 200 5 bl +rlabel metal2 22 200 22 200 5 br +rlabel m2contact 21 66 21 66 1 gnd +rlabel m2contact 28 88 28 88 1 gnd +rlabel m2contact 21 33 21 33 1 vdd +rlabel m2contact 18 120 18 120 1 vdd +rlabel m2contact 25 155 25 155 1 gnd +<< end >> diff --git a/technology/scn4me_subm/models/ff/nmos.sp b/technology/scn4me_subm/models/ff/nmos.sp new file mode 100644 index 00000000..07ca8dba --- /dev/null +++ b/technology/scn4me_subm/models/ff/nmos.sp @@ -0,0 +1,10 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0) + diff --git a/technology/scn4me_subm/models/ff/pmos.sp b/technology/scn4me_subm/models/ff/pmos.sp new file mode 100644 index 00000000..b4dc9026 --- /dev/null +++ b/technology/scn4me_subm/models/ff/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn4me_subm/models/nom/nmos.sp b/technology/scn4me_subm/models/nom/nmos.sp new file mode 100644 index 00000000..ad4db2b8 --- /dev/null +++ b/technology/scn4me_subm/models/nom/nmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn4me_subm/models/nom/pmos.sp b/technology/scn4me_subm/models/nom/pmos.sp new file mode 100644 index 00000000..9ecb13e1 --- /dev/null +++ b/technology/scn4me_subm/models/nom/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn4me_subm/models/ss/nmos.sp b/technology/scn4me_subm/models/ss/nmos.sp new file mode 100644 index 00000000..3d9bda57 --- /dev/null +++ b/technology/scn4me_subm/models/ss/nmos.sp @@ -0,0 +1,10 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0) + diff --git a/technology/scn4me_subm/models/ss/pmos.sp b/technology/scn4me_subm/models/ss/pmos.sp new file mode 100644 index 00000000..b4dc9026 --- /dev/null +++ b/technology/scn4me_subm/models/ss/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn4me_subm/sp_lib/cell_6t.sp b/technology/scn4me_subm/sp_lib/cell_6t.sp new file mode 100644 index 00000000..846cc371 --- /dev/null +++ b/technology/scn4me_subm/sp_lib/cell_6t.sp @@ -0,0 +1,13 @@ + +*********************** "cell_6t" ****************************** +.SUBCKT cell_6t bl br wl vdd gnd +* SPICE3 file created from cell_6t.ext - technology: scmos + +M1000 a_36_40# a_28_32# vdd vdd p w=0.6u l=0.8u +M1001 vdd a_36_40# a_28_32# vdd p w=0.6u l=0.8u +M1002 a_36_40# a_28_32# gnd gnd n w=1.6u l=0.4u +M1003 gnd a_36_40# a_28_32# gnd n w=1.6u l=0.4u +M1004 a_36_40# wl bl gnd n w=0.8u l=0.4u +M1005 a_28_32# wl br gnd n w=0.8u l=0.4u + +.ENDS diff --git a/technology/scn4me_subm/sp_lib/dff.sp b/technology/scn4me_subm/sp_lib/dff.sp new file mode 100644 index 00000000..d35d5123 --- /dev/null +++ b/technology/scn4me_subm/sp_lib/dff.sp @@ -0,0 +1,30 @@ +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd nfet w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS diff --git a/technology/scn4me_subm/sp_lib/replica_cell_6t.sp b/technology/scn4me_subm/sp_lib/replica_cell_6t.sp new file mode 100644 index 00000000..d26d600f --- /dev/null +++ b/technology/scn4me_subm/sp_lib/replica_cell_6t.sp @@ -0,0 +1,14 @@ + +*********************** "cell_6t" ****************************** +.SUBCKT replica_cell_6t bl br wl vdd gnd +* SPICE3 file created from replica_cell_6t.ext - technology: scmos + +M1000 gnd a_28_32# vdd vdd p w=0.6u l=0.8u +M1001 vdd gnd a_28_32# vdd p w=0.6u l=0.8u +** SOURCE/DRAIN TIED +M1002 gnd a_28_32# gnd gnd n w=1.6u l=0.4u +M1003 gnd gnd a_28_32# gnd n w=1.6u l=0.4u +M1004 gnd wl bl gnd n w=0.8u l=0.4u +M1005 a_28_32# wl br gnd n w=0.8u l=0.4u + +.ENDS diff --git a/technology/scn4me_subm/sp_lib/sense_amp.sp b/technology/scn4me_subm/sp_lib/sense_amp.sp new file mode 100644 index 00000000..70622413 --- /dev/null +++ b/technology/scn4me_subm/sp_lib/sense_amp.sp @@ -0,0 +1,15 @@ +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS diff --git a/technology/scn4me_subm/sp_lib/tri_gate.sp b/technology/scn4me_subm/sp_lib/tri_gate.sp new file mode 100644 index 00000000..451feba3 --- /dev/null +++ b/technology/scn4me_subm/sp_lib/tri_gate.sp @@ -0,0 +1,14 @@ +*********************** tri_gate ****************************** + +.SUBCKT tri_gate in out en en_bar vdd gnd + +* SPICE3 file created from tri_gate.ext - technology: scmos + +M1000 vdd in a_16_108# vdd p w=1.6u l=0.4u +M1001 a_76_212# a_16_108# vdd vdd p w=1.6u l=0.4u +M1002 out en_bar a_76_212# vdd p w=1.6u l=0.4u +M1003 gnd in a_16_108# gnd n w=0.8u l=0.4u +M1004 a_76_108# a_16_108# gnd gnd n w=0.8u l=0.4u +M1005 out en a_76_108# gnd n w=0.8u l=0.4u + +.ENDS diff --git a/technology/scn4me_subm/sp_lib/write_driver.sp b/technology/scn4me_subm/sp_lib/write_driver.sp new file mode 100644 index 00000000..afcf1049 --- /dev/null +++ b/technology/scn4me_subm/sp_lib/write_driver.sp @@ -0,0 +1,23 @@ +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd +* SPICE3 file created from write_driver.ext - technology: scmos + +M1000 a_44_708# a_36_700# bl gnd n w=2.4u l=0.4u +M1001 br a_16_500# a_44_708# gnd n w=2.4u l=0.4u +M1002 a_44_708# en gnd gnd n w=2.4u l=0.4u +M1003 gnd a_8_284# a_16_500# gnd n w=0.8u l=0.4u +M1004 a_36_700# a_20_328# gnd gnd n w=0.8u l=0.4u +M1005 vdd a_8_284# a_16_500# vdd p w=1.4u l=0.4u +M1006 a_36_700# a_20_328# vdd vdd p w=1.4u l=0.4u +M1007 vdd en a_20_328# vdd p w=1.4u l=0.4u +M1008 a_20_328# a_64_360# vdd vdd p w=1.4u l=0.4u +M1009 a_48_328# en a_20_328# gnd n w=1.4u l=0.4u +M1010 gnd a_64_360# a_48_328# gnd n w=1.4u l=0.4u +M1011 a_40_228# en a_8_284# gnd n w=1.4u l=0.4u +M1012 gnd din a_40_228# gnd n w=1.4u l=0.4u +M1013 a_64_360# din gnd gnd n w=0.8u l=0.4u +M1014 a_8_284# en vdd vdd p w=1.4u l=0.4u +M1015 vdd din a_8_284# vdd p w=1.4u l=0.4u +M1016 a_64_360# din vdd vdd p w=1.4u l=0.4u + +.ENDS diff --git a/technology/scn4me_subm/sue_lib/cell_6t.sue b/technology/scn4me_subm/sue_lib/cell_6t.sue new file mode 100644 index 00000000..427b1d05 --- /dev/null +++ b/technology/scn4me_subm/sue_lib/cell_6t.sue @@ -0,0 +1,46 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_cell_6t {} { + make inout -name BL -origin {190 360} + make inout -name BR -origin {830 360} + make input -name WL -origin {240 120} + make global -orient RXY -name vdd -origin {520 160} + make global -name gnd -origin {510 600} + make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230} + make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230} + make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360} + make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360} + make nmos -W 2.4u -L 0.6u -origin {630 490} + make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490} + make_wire 630 550 630 530 + make_wire 400 530 400 550 + make_wire 400 190 400 170 + make_wire 630 170 630 190 + make_wire 400 360 400 270 + make_wire 310 360 400 360 + make_wire 630 360 630 450 + make_wire 630 360 700 360 + make_wire 270 300 270 120 + make_wire 270 120 740 120 + make_wire 740 120 740 300 + make_wire 230 360 190 360 + make_wire 780 360 830 360 + make_wire 510 550 400 550 + make_wire 510 550 630 550 + make_wire 510 550 510 600 + make_wire 520 170 400 170 + make_wire 520 170 630 170 + make_wire 520 160 520 170 + make_wire 240 120 270 120 + make_wire 460 290 630 290 + make_wire 460 290 460 490 + make_wire 460 290 460 230 + make_wire 630 290 630 360 + make_wire 630 290 630 270 + make_wire 570 420 400 420 + make_wire 570 420 570 490 + make_wire 570 420 570 230 + make_wire 400 420 400 360 + make_wire 400 420 400 450 +} + diff --git a/technology/scn4me_subm/sue_lib/ms_flop.sue b/technology/scn4me_subm/sue_lib/ms_flop.sue new file mode 100644 index 00000000..85cc8e03 --- /dev/null +++ b/technology/scn4me_subm/sue_lib/ms_flop.sue @@ -0,0 +1,84 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_ms_flop {} { + make pmos -orient R90X -W 1.8u -L 0.6u -origin {40 250} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {40 380} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {-270 540} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {310 310} + make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {430 730} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {190 670} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {190 780} + make input -name clk -origin {-380 540} + make input -name din -origin {-370 320} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {720 250} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {720 380} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {990 310} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {870 670} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {870 780} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {620 540} + make output -name dout -origin {1410 310} + make output -name dout_bar -origin {1430 930} + make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {1110 730} + make_wire -330 160 40 160 + make_wire 40 160 40 190 + make_wire -370 320 0 320 + make_wire 360 310 480 310 + make_wire 460 730 480 730 + make_wire 230 730 380 730 + make_wire 100 310 100 720 + make_wire 100 720 150 720 + make_wire 100 310 80 310 + make_wire 100 310 280 310 + make_wire 0 250 0 320 + make_wire 0 320 0 380 + make_wire 80 250 80 310 + make_wire 80 310 80 380 + make_wire 40 440 40 540 + make_wire -330 840 190 840 + make_wire 230 670 230 730 + make_wire 230 730 230 780 + make_wire 150 670 150 720 + make_wire 150 720 150 780 + make_wire 190 540 190 610 + make_wire -330 540 -330 840 + make_wire -220 540 40 540 + make_wire 40 540 190 540 + make_wire -380 540 -330 540 + make_wire -330 540 -300 540 + make_wire -330 540 -330 160 + make_wire 720 160 720 190 + make_wire 1140 730 1160 730 + make_wire 780 310 780 720 + make_wire 780 720 830 720 + make_wire 780 310 760 310 + make_wire 780 310 960 310 + make_wire 680 320 680 380 + make_wire 760 250 760 310 + make_wire 760 310 760 380 + make_wire 720 440 720 540 + make_wire 910 670 910 730 + make_wire 910 730 910 780 + make_wire 830 670 830 720 + make_wire 830 720 830 780 + make_wire 870 540 870 610 + make_wire 720 540 870 540 + make_wire 670 540 720 540 + make_wire 480 310 480 730 + make_wire 1160 310 1160 730 + make_wire 530 540 530 160 + make_wire 530 160 720 160 + make_wire 530 540 190 540 + make_wire 530 540 590 540 + make_wire 530 540 530 840 + make_wire 530 840 870 840 + make_wire 680 310 480 310 + make_wire 680 310 680 250 + make_wire 680 310 680 320 + make_wire 950 730 910 730 + make_wire 950 730 1060 730 + make_wire 1040 310 1160 310 + make_wire 1160 310 1410 310 + make_wire 950 930 1430 930 + make_wire 950 730 950 930 +} + diff --git a/technology/scn4me_subm/sue_lib/replica_cell_6t.sue b/technology/scn4me_subm/sue_lib/replica_cell_6t.sue new file mode 100644 index 00000000..56e72056 --- /dev/null +++ b/technology/scn4me_subm/sue_lib/replica_cell_6t.sue @@ -0,0 +1,49 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_replica_cell_6t {} { + make inout -name BL -origin {190 360} + make inout -name BR -origin {830 360} + make input -name WL -origin {240 120} + make global -orient RXY -name vdd -origin {520 160} + make global -name gnd -origin {510 600} + make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230} + make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230} + make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360} + make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360} + make nmos -W 2.4u -L 0.6u -origin {630 490} + make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490} + make_wire 630 550 630 530 + make_wire 400 530 400 550 + make_wire 400 190 400 170 + make_wire 630 170 630 190 + make_wire 400 360 400 270 + make_wire 630 360 630 450 + make_wire 630 360 700 360 + make_wire 270 300 270 120 + make_wire 270 120 740 120 + make_wire 740 120 740 300 + make_wire 230 360 190 360 + make_wire 780 360 830 360 + make_wire 510 550 400 550 + make_wire 510 550 630 550 + make_wire 510 550 510 600 + make_wire 520 170 400 170 + make_wire 520 170 630 170 + make_wire 520 160 520 170 + make_wire 240 120 270 120 + make_wire 460 290 630 290 + make_wire 460 290 460 490 + make_wire 460 290 460 230 + make_wire 630 290 630 360 + make_wire 630 290 630 270 + make_wire 570 420 400 420 + make_wire 570 420 570 490 + make_wire 570 420 570 230 + make_wire 400 420 400 360 + make_wire 400 420 400 450 + make_wire 320 360 320 550 + make_wire 320 550 400 550 + make_wire 320 360 310 360 + make_wire 320 360 400 360 +} + diff --git a/technology/scn4me_subm/sue_lib/sense_amp.sue b/technology/scn4me_subm/sue_lib/sense_amp.sue new file mode 100644 index 00000000..4d29e11a --- /dev/null +++ b/technology/scn4me_subm/sue_lib/sense_amp.sue @@ -0,0 +1,52 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_sense_amp {} { + make inout -name BL -origin {260 10} + make global -orient RXY -name vdd -origin {490 170} + make global -name gnd -origin {480 660} + make input -name sclk -origin {180 610} + make nmos -W 3.9u -L 0.6u -origin {600 500} + make nmos -orient RX -W 3.9u -L 0.6u -origin {370 500} + make pmos -orient RY -W 3u -L 0.6u -origin {600 240} + make pmos -orient RXY -W 3u -L 0.6u -origin {370 240} + make nmos -W 3.9u -L 0.6u -origin {480 610} + make inout -name BR -origin {710 20} + make pmos -W 3.9u -L 0.6u -origin {710 90} + make pmos -orient RX -W 3.9u -L 0.6u -origin {260 90} + make output -orient RXY -name dout -origin {110 370} + make_wire 600 560 600 540 + make_wire 370 540 370 560 + make_wire 370 200 370 180 + make_wire 600 180 600 200 + make_wire 490 180 370 180 + make_wire 490 180 600 180 + make_wire 490 170 490 180 + make_wire 430 300 600 300 + make_wire 430 300 430 500 + make_wire 430 300 430 240 + make_wire 600 300 600 280 + make_wire 540 430 370 430 + make_wire 540 430 540 500 + make_wire 540 430 540 240 + make_wire 370 430 370 460 + make_wire 480 560 600 560 + make_wire 480 560 370 560 + make_wire 480 560 480 570 + make_wire 480 650 480 660 + make_wire 420 610 180 610 + make_wire 650 90 320 90 + make_wire 600 360 710 360 + make_wire 710 360 710 130 + make_wire 600 360 600 300 + make_wire 600 360 600 460 + make_wire 370 370 260 370 + make_wire 260 370 260 130 + make_wire 370 370 370 430 + make_wire 370 370 370 280 + make_wire 260 10 260 50 + make_wire 710 20 710 50 + make_wire 320 90 180 90 + make_wire 180 90 180 610 + make_wire 110 370 260 370 +} + diff --git a/technology/scn4me_subm/sue_lib/tri_gate.sue b/technology/scn4me_subm/sue_lib/tri_gate.sue new file mode 100644 index 00000000..d296171f --- /dev/null +++ b/technology/scn4me_subm/sue_lib/tri_gate.sue @@ -0,0 +1,37 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_tri_gate {} { + make global -orient RXY -name vdd -origin {630 150} + make global -name gnd -origin {630 570} + make input -name tri_in -origin {320 340} + make output -name tri_out -origin {690 360} + make input -name en -origin {570 410} + make input -name en_bar -origin {570 310} + make nmos -W 1.2u -L 0.6u -origin {630 490} + make nmos -W 1.2u -L 0.6u -origin {630 410} + make pmos -orient RY -W 2.4u -L 0.6u -origin {630 310} + make pmos -orient RY -W 2.4u -L 0.6u -origin {630 230} + make pmos -orient RY -W 2.4u -L 0.6u -origin {380 290} + make nmos -W 1.2u -L 0.6u -origin {380 400} + make_wire 570 490 470 490 + make_wire 470 230 570 230 + make_wire 630 550 380 550 + make_wire 380 550 380 440 + make_wire 630 550 630 570 + make_wire 630 550 630 530 + make_wire 630 170 380 170 + make_wire 380 170 380 250 + make_wire 630 170 630 190 + make_wire 630 170 630 150 + make_wire 320 340 320 400 + make_wire 320 340 320 290 + make_wire 380 340 470 340 + make_wire 380 340 380 330 + make_wire 380 340 380 360 + make_wire 470 340 470 490 + make_wire 470 340 470 230 + make_wire 630 360 630 350 + make_wire 630 360 630 370 + make_wire 630 360 690 360 +} + diff --git a/technology/scn4me_subm/sue_lib/write_driver.sue b/technology/scn4me_subm/sue_lib/write_driver.sue new file mode 100644 index 00000000..de3909a7 --- /dev/null +++ b/technology/scn4me_subm/sue_lib/write_driver.sue @@ -0,0 +1,44 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_write_driver {} { + make inout -name BL -origin {550 260} + make inout -name BR -origin {830 250} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {280 520} + make nand2 -WP 2.1u -WN 2.1u -origin {90 360} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {270 360} + make nmos -W 3.6u -L 0.6u -origin {830 410} + make nmos -W 3.6u -L 0.6u -origin {710 610} + make global -name gnd -origin {710 690} + make nand2 -WP 2.1u -WN 2.1u -origin {90 520} + make nmos -W 3.6u -L 0.6u -origin {550 410} + make input -name wen -origin {-290 340} + make input -name din -origin {-290 380} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {-80 540} + make_wire 160 360 240 360 + make_wire 830 250 830 370 + make_wire 550 260 550 370 + make_wire 550 450 550 560 + make_wire 550 560 710 560 + make_wire 710 560 710 570 + make_wire 710 560 830 560 + make_wire 830 560 830 450 + make_wire 710 650 710 690 + make_wire 250 520 160 520 + make_wire 770 410 770 520 + make_wire 770 520 330 520 + make_wire 320 360 490 360 + make_wire 490 360 490 410 + make_wire -180 380 -290 380 + make_wire -180 380 70 380 + make_wire -180 540 -110 540 + make_wire -180 380 -180 540 + make_wire -30 540 70 540 + make_wire 20 340 20 500 + make_wire 20 500 70 500 + make_wire 20 340 70 340 + make_wire -240 340 -240 610 + make_wire -240 610 650 610 + make_wire -240 340 20 340 + make_wire -240 340 -290 340 +} + diff --git a/technology/scn4me_subm/tech/LICENSE.txt b/technology/scn4me_subm/tech/LICENSE.txt new file mode 100644 index 00000000..0d923fcb --- /dev/null +++ b/technology/scn4me_subm/tech/LICENSE.txt @@ -0,0 +1,10 @@ +The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following +license information: +--------------------------------------------------------------- +Tim Edwards +Open Circuit Design +v1.0 April 2013 +v1.1 May 2015 +v1.2 April 2017 +--------------------------------------------------------------- +GPL Copyright (c) 2017 diff --git a/technology/scn4me_subm/tech/SCN4M_SUBM.20.tech b/technology/scn4me_subm/tech/SCN4M_SUBM.20.tech new file mode 100644 index 00000000..7400825c --- /dev/null +++ b/technology/scn4me_subm/tech/SCN4M_SUBM.20.tech @@ -0,0 +1,10329 @@ +tech + format 32 + scmos +end + +version + version 2001a + description "SCMOS: Submit as technology.lambda: SCN4M_SUBM.20 [to process: TSMC35]" +end + +planes + well,w + implant,i + select,s + active,a + metal1,m1 + metal2,m2 + metal3,m3 + metal4,m4 + oxide,ox + comment + xp + contact + via1,v1 + via2,v2 + via3,v3 + fill +end + +types + well nwell,nw + active nwr + well pwell,pw + implant n_field_implant,nfi + implant p_field_implant,pfi + select nselect,ns + select pselect,ps + active ntransistor,nfet + active ptransistor,pfet + active diffusion,diff + active transistor,fet + active ndiffusion,ndif,green + active pdiffusion,pdif,brown + active ndcontact,ndc + active pdcontact,pdc + active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd + active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd + active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc + active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc + active nwsd + active nwsc + active polysilicon,red,poly,p + active polycontact,pcontact,polycut,pc + contact genericcontact,gcontact,gc + metal1 metal1,m1,blue + metal1 pseudo_rmetal1,prm1 + metal1 rmetal1,rm1 + metal1 fillm1,fm1 + metal1 m2contact,m2cut,m2c,via1,v1,via + metal1 pm12contact,pm12c + metal1 pdm12contact,pdm12c + metal1 psm12contact,psm12c,pom12c,pwm12c + metal1 ndm12contact,ndm12c + metal1 nsm12contact,nsm12c,nom12c,nwm12c + metal1 nwsm12contact,nwsm12c + metal2 metal2,m2,purple + metal2 pseudo_rmetal2,prm2 + metal2 rmetal2,rm2 + metal2 fillm2,fm2 + via1 gv1 + metal2 m3contact,m3cut,m3c,via2,v2 + metal2 m123contact,m123c + metal3 metal3,m3,cyan + metal3 pseudo_rmetal3,prm3 + metal3 rmetal3,rm3 + metal3 fillm3,fm3 + via2 gv2 + metal3 m234contact,m234c + metal3 m4contact,m4cut,m4c,via3,v3 + metal4 metal4,m4,yellow + metal4 pseudo_rmetal4,prm4 + metal4 rmetal4,rm4 + metal4 fillm4,fm4 + via3 gv3 + metal4 pad + oxide glass + active silicide_block,sb + active poly_resist,pres + active pseudo_rpoly,prp + active rpoly,rp + active pseudo_rndiffusion,prnd + active rndiffusion,rndiff,rnd + active pseudo_rpdiffusion,prpd + active rpdiffusion,rpdiff,rpd + active pseudo_rnwell,prnwell,prnw + active rnwell,rnw + active pseudo_nwr,pnwr + implant filln,fn + fill filla,fa + fill fillb,fb + active fillp,fp + active fillapm,fapm + active activen_resist,anres + active activep_resist,apres + xp xp + xp m1p + xp m2p + xp m3p + xp m4p + comment comment + comment bb +end + +contact + pc poly metal1 + ndc ndiff metal1 + pdc pdiff metal1 + nsc nsd metal1 + nwsc nwsd metal1 + psc psd metal1 + m2c metal1 metal2 + m3c metal2 metal3 + m4c metal3 metal4 + # pm12c poly metal1 metal2 + # pdm12c pdiff metal1 metal2 + # psm12c psd metal1 metal2 + # ndm12c ndiff metal1 metal2 + # nsm12c nsd metal1 metal2 + # nwsm12c nwsd metal1 metal2 + # m123c metal1 metal2 metal3 + # m234c metal2 metal3 metal4 + stackable pc m2c pm12c + stackable pdc m2c pdm12c + stackable psc m2c psm12c + stackable ndc m2c ndm12c + stackable nsc m2c nsm12c + stackable nwsc m2c nwsm12c + stackable m2c m3c m123c + stackable m3c m4c m234c +end + +styles + styletype mos + nwr 54 + pnwr 53 + nwsd 3 + nwsd 54 + nwsc 3 + nwsc 20 + nwsc 32 + nwsc 54 + nwell 12 + pwell 13 + nfi 53 + pfi 54 + nselect 43 + pselect 44 + diff 25 + tran 2 + tran 4 + ndiff 2 + pdiff 4 + nsd 3 + psd 5 + nfet 6 + nfet 7 + pfet 8 + pfet 9 + ndc 2 + ndc 20 + ndc 32 + pdc 4 + pdc 20 + pdc 32 + nsc 3 + nsc 20 + nsc 32 + psc 5 + psc 20 + psc 32 + poly 1 + pcontact 1 + pcontact 20 + pcontact 32 + gc 32 + metal1 20 + rm1 20 + rm1 48 + prm1 48 + m1p 20 + m1p 34 + fm1 20 + fm1 34 + fp 1 + fp 34 + fa 32 + fb 45 + fb 34 + fn 45 + fn 34 + fapm 1 + fapm 20 + fapm 21 + fapm 34 + gv1 55 + m2contact 20 + m2contact 21 + m2contact 55 + pm12contact 1 + pm12contact 20 + pm12contact 21 + pm12contact 32 + pm12contact 55 + ndm12c 2 + ndm12c 20 + ndm12c 21 + ndm12c 32 + ndm12c 55 + nsm12c 3 + nsm12c 20 + nsm12c 21 + nsm12c 32 + nsm12c 55 + nwsm12c 3 + nwsm12c 20 + nwsm12c 21 + nwsm12c 32 + nwsm12c 55 + nwsm12c 54 + pdm12c 4 + pdm12c 20 + pdm12c 21 + pdm12c 32 + pdm12c 55 + psm12c 5 + psm12c 20 + psm12c 21 + psm12c 32 + psm12c 55 + metal2 21 + rm2 21 + rm2 48 + prm2 48 + m2p 21 + m2p 34 + fm2 21 + fm2 34 + gv2 56 + m3contact 21 + m3contact 22 + m3contact 56 + m123c 20 + m123c 21 + m123c 22 + m123c 55 + m123c 56 + metal3 22 + rm3 22 + rm3 48 + prm3 48 + m3p 22 + m3p 34 + fm3 22 + fm3 34 + gv3 57 + m4contact 22 + m4contact 23 + m4contact 57 + m234contact 21 + m234contact 22 + m234contact 23 + m234contact 56 + m234contact 57 + metal4 23 + rm4 23 + rm4 48 + prm4 48 + m4p 23 + m4p 34 + fm4 23 + fm4 34 + pad 22 + pad 23 + pad 34 + pad 38 + glass 34 + xp 25 + xp 34 + sb 10 + pres 47 + pres 48 + rp 47 + rp 48 + prp 48 + anres 2 + anres 48 + rnd 2 + rnd 48 + prnd 48 + apres 4 + apres 53 + rpd 4 + rpd 53 + prpd 53 + rnw 12 + rnw 53 + prnw 54 + comment 45 + bb 32 + error_p 42 + error_s 42 + error_ps 42 + magnet 54 + rotate 57 + fence 59 +end + +compose + compose nfet poly ndiff + compose pfet poly pdiff + paint diff nselect ndiff + paint diff pselect pdiff + compose tran poly diff + paint tran nselect nfet + paint tran pselect pfet + paint psd ns ndiff + paint nsd ps pdiff + paint ndiff ps psd + paint pdiff ns nsd + paint pad m1 pad + paint pad m2 pad + paint pad m2c pad + paint pfi nwell nfi + paint nfi pwell pfi + paint anres nwell apres + paint apres pwell anres + paint ndc nwell pdc + paint nfet nwell pfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + paint pdc pwell ndc + paint pfet pwell nfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint pad m3 pad + paint pad m4 pad + compose pres poly sb + paint sb poly pres + paint poly sb pres + erase pres sb poly + compose anres ndiff sb + paint sb ndiff anres + paint ndiff sb anres + erase anres sb ndiff + compose apres pdiff sb + paint sb pdiff apres + paint pdiff sb apres + erase apres sb pdiff +#CRE/CRM + compose rm1 prm1 m1 + compose rm2 prm2 m2 + compose rm3 prm3 m3 + compose rm4 prm4 m4 + compose rp prp poly + compose rnd prnd ndiff + compose rpd prpd pdiff + paint nwell rnw space + paint nwell nwr space + paint nwell prnw space + paint poly fp fp + paint m1 fm1 fm1 + paint m2 fm2 fm2 + paint m3 fm3 fm3 + paint m4 fm4 fm4 +end + +connect + nwell,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nsd,nwsd nwell,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nsd,nwsd + pwell,psc/a,psm12c/a,psd pwell,psc/a,psm12c/a,psd + m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + m4,fm4,fapm,m4c/m4,m234c/m4 m4,fm4,fapm,m4c/m4,m234c/m4 + ndiff,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdiff,psd,pdc/a,pdm12c/a,psc/a,psm12c/a ndiff,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdiff,psd,pdc/a,pdm12c/a,psc/a,psm12c/a + poly,fp,nfet,pfet,fet,fapm,pc/a,pm12c/a poly,fp,nfet,pfet,fet,fapm,pc/a,pm12c/a + gc poly,fp,ndiff,pdiff,nsd,nwsd,psd,m1,fm1,fapm,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + gv1 m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2,fm2,fapm,m3c/m2,m123c/m2,m234c/m2 + gv2 m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3,fm3,fapm,m4c/m3,m234c/m3 + gv3 m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4,fm4,fapm + pad m1,fm1,m2,fm2,m3,fm3,m4,fm4 + rm1 prm1 + rm2 prm2 + rm3 prm3 + rm4 prm4 + rnw prnw + nwr pnwr + rp prp + rnd prnd + rpd prpd + pres sb + anres sb + apres sb +end + +cifoutput + +style lambda=0.20(p) + scalefactor 20 10 + + layer CWN nwell,rnw,nwr,nwsd,nwsc + bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 + bloat-or nsd,nsc/a,nsm12c/a * 60 + bloat-or nfi * 80 + grow 60 + shrink 60 + labels nwell,rnw,nwr,nwsd,nwsc + calma 42 0 + + layer CWNR nwsd,nwsc,nwr + grow 140 + calma 91 0 + + layer CWND nwr + labels nwr + calma 92 0 + + layer CAA nwsd,nwsc,nwr + grow 100 + labels nwsd,nwsc + calma 43 0 + + layer CSN + bloat-or nwsd,nwsc * 80 nwr 0 + calma 43 0 + + templayer TNWR + bloat-or nwr * 100 nwsd,nwsc 40 + + templayer TCSB nwsd,nwsc + grow 40 + and-not TNWR + + layer CSB nwsd,nwsc,nwr + grow 140 + and-not TCSB + calma 29 0 + + layer CRNW pnwr + labels pnwr + calma 93 0 + + layer CWP pwell + bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a,nfet * 120 + bloat-or psd,psc/a,psm12c/a * 60 + bloat-or pfi * 80 + grow 60 + shrink 60 + and-not CWN + labels pwell + calma 41 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*40) Or ps +#XDN = (ndiff*40) Or ns +#FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 20 + grow 20 + grow 20 + shrink 20 + +#final nselect + templayer FSN + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 + and-not nwr + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 20 + grow 20 + grow 20 + shrink 20 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + calma 43 0 + + layer CCA nwsc/m1,nwsm12c/m1 + squares 40 40 60 + calma 48 0 + + layer CCA ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 + squares 20 40 60 + calma 48 0 + + layer CCA pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 + squares 20 40 60 + calma 48 0 + + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + calma 46 0 + + layer CCP pc/m1,pm12c/m1 + squares 20 40 60 + calma 47 0 + + layer CCC gc + squares 0 40 60 + calma 25 0 + + layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + squares 20 40 60 + calma 50 0 + + layer CV1 gv1 + squares 0 40 60 + calma 50 0 + + layer CV2 m3c/m2,m123c/m2,m234c/m2 + squares 20 40 60 + calma 61 0 + + layer CV2 gv2 + squares 0 40 60 + calma 61 0 + + layer CV3 m4c/m3,m234c/m3 + squares 20 40 60 + calma 30 0 + + layer CV3 gv3 + squares 0 40 60 + calma 30 0 + + + templayer XPAD1 pad + shrink 120 + + templayer XPAD2 XPAD1 + shrink 120 + + layer CM4 pad + labels pad + calma 31 0 + + layer CV3 XPAD2 + squares 40 40 200 + calma 30 0 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 160 40 200 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 40 40 200 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 104 fm4 + labels fm4 + calma 104 0 + + layer 109 fa + or fb + squares 0 200 80 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 200 80 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 200 80 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 200 80 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 200 80 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer CM4 m4,rm4,m4c/m4,m234c/m4 + labels m4,rm4,m4c/m4,m234c/m4 + calma 31 0 + + layer CMQP m4p + labels m4p + calma 84 0 + +# layer CM4 fm4 + layer CM4 fm4,fapm + + squares 0 200 80 + labels fm4 + calma 31 0 + + layer COG pad + shrink 500 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CSB sb,pres,anres,apres + labels sb,pres,anres,apres + calma 29 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp,pres + labels rp,prp,pres + calma 67 0 + layer CRD rnd,rpd,prnd,prpd,anres,apres + labels rnd,rpd,prnd,prpd,anres,apres + calma 66 0 + layer CRE rnw,rp,rnd,rpd,pres,anres,apres + labels rnw,rp,rnd,rpd,pres,anres,apres + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 + layer CRQ rm4,prm4 + labels rm4,prm4 + calma 74 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + +style fill-only + scalefactor 20 10 + + layer 100 fp + calma 100 0 + + layer 101 fm1 + calma 101 0 + + layer 102 fm2 + calma 102 0 + + layer 103 fm3 + calma 103 0 + + layer 104 fm4 + calma 104 0 + + layer 109 fa + or fb + calma 109 0 + + layer 119 fn + calma 119 0 + +style fapm-boxes + +# this output style creates fill boxes automatically (to meet minimum +# density requirements for poly and metal layers) 5 microns outside of +# drawn layout IF: 1. you have a flattened version of your chip, +# 2. over which you paint the special fill layer 'fa', preferably with +# a size that is a multiple of 10 + n * (10 + 4), 3. set 'cif +# ostype fapm-boxes' and cif out to a file (this actually creates the +# fill boxes on cif/strm layer '110' using the magic 'squares' +# command), 4. cif in the resulting file (which creates boxes on magic +# layer 'fapm') and place this cell onto your chip (and verify absence +# of drc errors or shorts), then 5. cif out under your regular cif out +# style, where the 'fapm' layer creates fill boxes on poly and all +# metal layers. + + scalefactor 20 10 + + templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + or fm1,m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + or fm2,m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + or fm3,m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + or fm4,m4,rm4,m4c/m4,m234c/m4 + or glass,pad + grow 500 + and fa + + layer 110 fa + squares 0 200 80 + and-not CRIT + shrink 90 + grow 90 + or fapm + labels fapm + calma 110 0 + +style fapm-stripes + scalefactor 20 10 + +# this output style creates the above layer 110 as stripes for reduced size +# HOWEVER it requires each 'fa' box to first be an exact multiple as above +# and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box +# to be a 1-lambda wide layer 'fb' box -- else you won't get strips! + + templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + or fm1,m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + or fm2,m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + or fm3,m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + or fm4,m4,rm4,m4c/m4,m234c/m4 + or glass,pad + grow 500 + and fa + + templayer FB fa + or fb + squares 0 200 80 + and-not CRIT + + layer 110 fa + squares 0 200 80 + and-not CRIT + or FB + shrink 90 + grow 90 + or fapm + labels fapm + calma 110 0 + + +style lambda=0.20(cp) + scalefactor 20 10 + + layer CWN nwell,rnw,nwr,nwsd,nwsc + bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 + bloat-or nsd,nsc/a,nsm12c/a * 60 + bloat-or nfi * 80 + grow 60 + shrink 60 + labels nwell,rnw,nwr,nwsd,nwsc + calma 42 0 + + layer CWNR nwsd,nwsc,nwr + grow 140 + calma 91 0 + + layer CWND nwr + labels nwr + calma 92 0 + + layer CAA nwsd,nwsc,nwr + grow 100 + labels nwsd,nwsc + calma 43 0 + + layer CSN + bloat-or nwsd,nwsc * 80 nwr 0 + calma 43 0 + + templayer TNWR + bloat-or nwr * 100 nwsd,nwsc 40 + + templayer TCSB nwsd,nwsc + grow 40 + and-not TNWR + + layer CSB nwsd,nwsc,nwr + grow 140 + and-not TCSB + calma 29 0 + + layer CRNW pnwr + labels pnwr + calma 93 0 + + layer CWP pwell + bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a,nfet * 120 + bloat-or psd,psc/a,psm12c/a * 60 + bloat-or pfi * 80 + grow 60 + shrink 60 + and-not CWN + labels pwell + calma 41 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*40) Or ps +#XDN = (ndiff*40) Or ns +#FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 20 + grow 20 + grow 20 + shrink 20 + +#final nselect + templayer FSN + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 + and-not nwr + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 20 + grow 20 + grow 20 + shrink 20 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + calma 43 0 + + layer CCC nwsc/m1,nwsm12c/m1 + squares 40 40 60 + calma 25 0 + + layer CCC ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 + squares 20 40 60 + calma 25 0 + + layer CCC pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 + squares 20 40 60 + calma 25 0 + + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + calma 46 0 + + layer CCC pc/m1,pm12c/m1 + squares 20 40 60 + calma 25 0 + + layer CCC gc + squares 0 40 60 + calma 25 0 + + layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + squares 20 40 60 + calma 50 0 + + layer CV1 gv1 + squares 0 40 60 + calma 50 0 + + layer CV2 m3c/m2,m123c/m2,m234c/m2 + squares 20 40 60 + calma 61 0 + + layer CV2 gv2 + squares 0 40 60 + calma 61 0 + + layer CV3 m4c/m3,m234c/m3 + squares 20 40 60 + calma 30 0 + + layer CV3 gv3 + squares 0 40 60 + calma 30 0 + + + templayer XPAD1 pad + shrink 120 + + templayer XPAD2 XPAD1 + shrink 120 + + layer CM4 pad + labels pad + calma 31 0 + + layer CV3 XPAD2 + squares 40 40 200 + calma 30 0 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 160 40 200 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 40 40 200 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 104 fm4 + labels fm4 + calma 104 0 + + layer 109 fa + or fb + squares 0 200 80 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 200 80 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 200 80 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 200 80 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 200 80 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer CM4 m4,rm4,m4c/m4,m234c/m4 + labels m4,rm4,m4c/m4,m234c/m4 + calma 31 0 + + layer CMQP m4p + labels m4p + calma 84 0 + +# layer CM4 fm4 + layer CM4 fm4,fapm + + squares 0 200 80 + labels fm4 + calma 31 0 + + layer COG pad + shrink 500 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CSB sb,pres,anres,apres + labels sb,pres,anres,apres + calma 29 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp,pres + labels rp,prp,pres + calma 67 0 + layer CRD rnd,rpd,prnd,prpd,anres,apres + labels rnd,rpd,prnd,prpd,anres,apres + calma 66 0 + layer CRE rnw,rp,rnd,rpd,pres,anres,apres + labels rnw,rp,rnd,rpd,pres,anres,apres + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 + layer CRQ rm4,prm4 + labels rm4,prm4 + calma 74 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + + +style lambda=0.20(c) + scalefactor 20 10 + + layer CWN nwell,rnw,nwr,nwsd,nwsc + bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 + bloat-or nsd,nsc/a,nsm12c/a * 60 + bloat-or nfi * 80 + grow 60 + shrink 60 + labels nwell,rnw,nwr,nwsd,nwsc + calma 42 0 + + layer CWNR nwsd,nwsc,nwr + grow 140 + calma 91 0 + + layer CWND nwr + labels nwr + calma 92 0 + + layer CAA nwsd,nwsc,nwr + grow 100 + labels nwsd,nwsc + calma 43 0 + + layer CSN + bloat-or nwsd,nwsc * 80 nwr 0 + calma 43 0 + + templayer TNWR + bloat-or nwr * 100 nwsd,nwsc 40 + + templayer TCSB nwsd,nwsc + grow 40 + and-not TNWR + + layer CSB nwsd,nwsc,nwr + grow 140 + and-not TCSB + calma 29 0 + + layer CRNW pnwr + labels pnwr + calma 93 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*40) Or ps +#XDN = (ndiff*40) Or ns +#FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 20 + grow 20 + grow 20 + shrink 20 + +#final nselect + templayer FSN + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 + and-not nwr + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 20 + grow 20 + grow 20 + shrink 20 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + calma 43 0 + + layer CCC nwsc/m1,nwsm12c/m1 + squares 40 40 60 + calma 25 0 + + layer CCC ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 + squares 20 40 60 + calma 25 0 + + layer CCC pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 + squares 20 40 60 + calma 25 0 + + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + calma 46 0 + + layer CCC pc/m1,pm12c/m1 + squares 20 40 60 + calma 25 0 + + layer CCC gc + squares 0 40 60 + calma 25 0 + + layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + squares 20 40 60 + calma 50 0 + + layer CV1 gv1 + squares 0 40 60 + calma 50 0 + + layer CV2 m3c/m2,m123c/m2,m234c/m2 + squares 20 40 60 + calma 61 0 + + layer CV2 gv2 + squares 0 40 60 + calma 61 0 + + layer CV3 m4c/m3,m234c/m3 + squares 20 40 60 + calma 30 0 + + layer CV3 gv3 + squares 0 40 60 + calma 30 0 + + + templayer XPAD1 pad + shrink 120 + + templayer XPAD2 XPAD1 + shrink 120 + + layer CM4 pad + labels pad + calma 31 0 + + layer CV3 XPAD2 + squares 40 40 200 + calma 30 0 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 160 40 200 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 40 40 200 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 104 fm4 + labels fm4 + calma 104 0 + + layer 109 fa + or fb + squares 0 200 80 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 200 80 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 200 80 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 200 80 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 200 80 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer CM4 m4,rm4,m4c/m4,m234c/m4 + labels m4,rm4,m4c/m4,m234c/m4 + calma 31 0 + + layer CMQP m4p + labels m4p + calma 84 0 + +# layer CM4 fm4 + layer CM4 fm4,fapm + + squares 0 200 80 + labels fm4 + calma 31 0 + + layer COG pad + shrink 500 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CSB sb,pres,anres,apres + labels sb,pres,anres,apres + calma 29 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp,pres + labels rp,prp,pres + calma 67 0 + layer CRD rnd,rpd,prnd,prpd,anres,apres + labels rnd,rpd,prnd,prpd,anres,apres + calma 66 0 + layer CRE rnw,rp,rnd,rpd,pres,anres,apres + labels rnw,rp,rnd,rpd,pres,anres,apres + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 + layer CRQ rm4,prm4 + labels rm4,prm4 + calma 74 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + + +style lambda=0.20() + scalefactor 20 10 + + layer CWN nwell,rnw,nwr,nwsd,nwsc + bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 + bloat-or nsd,nsc/a,nsm12c/a * 60 + bloat-or nfi * 80 + grow 60 + shrink 60 + labels nwell,rnw,nwr,nwsd,nwsc + calma 42 0 + + layer CWNR nwsd,nwsc,nwr + grow 140 + calma 91 0 + + layer CWND nwr + labels nwr + calma 92 0 + + layer CAA nwsd,nwsc,nwr + grow 100 + labels nwsd,nwsc + calma 43 0 + + layer CSN + bloat-or nwsd,nwsc * 80 nwr 0 + calma 43 0 + + templayer TNWR + bloat-or nwr * 100 nwsd,nwsc 40 + + templayer TCSB nwsd,nwsc + grow 40 + and-not TNWR + + layer CSB nwsd,nwsc,nwr + grow 140 + and-not TCSB + calma 29 0 + + layer CRNW pnwr + labels pnwr + calma 93 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*40) Or ps +#XDN = (ndiff*40) Or ns +#FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 20 + grow 20 + grow 20 + shrink 20 + +#final nselect + templayer FSN + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 + and-not nwr + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 20 + grow 20 + grow 20 + shrink 20 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + calma 43 0 + + layer CCA nwsc/m1,nwsm12c/m1 + squares 40 40 60 + calma 48 0 + + layer CCA ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 + squares 20 40 60 + calma 48 0 + + layer CCA pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 + squares 20 40 60 + calma 48 0 + + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + calma 46 0 + + layer CCP pc/m1,pm12c/m1 + squares 20 40 60 + calma 47 0 + + layer CCC gc + squares 0 40 60 + calma 25 0 + + layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + squares 20 40 60 + calma 50 0 + + layer CV1 gv1 + squares 0 40 60 + calma 50 0 + + layer CV2 m3c/m2,m123c/m2,m234c/m2 + squares 20 40 60 + calma 61 0 + + layer CV2 gv2 + squares 0 40 60 + calma 61 0 + + layer CV3 m4c/m3,m234c/m3 + squares 20 40 60 + calma 30 0 + + layer CV3 gv3 + squares 0 40 60 + calma 30 0 + + + templayer XPAD1 pad + shrink 120 + + templayer XPAD2 XPAD1 + shrink 120 + + layer CM4 pad + labels pad + calma 31 0 + + layer CV3 XPAD2 + squares 40 40 200 + calma 30 0 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 160 40 200 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 40 40 200 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 104 fm4 + labels fm4 + calma 104 0 + + layer 109 fa + or fb + squares 0 200 80 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 200 80 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 200 80 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 200 80 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 200 80 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer CM4 m4,rm4,m4c/m4,m234c/m4 + labels m4,rm4,m4c/m4,m234c/m4 + calma 31 0 + + layer CMQP m4p + labels m4p + calma 84 0 + +# layer CM4 fm4 + layer CM4 fm4,fapm + + squares 0 200 80 + labels fm4 + calma 31 0 + + layer COG pad + shrink 500 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CSB sb,pres,anres,apres + labels sb,pres,anres,apres + calma 29 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp,pres + labels rp,prp,pres + calma 67 0 + layer CRD rnd,rpd,prnd,prpd,anres,apres + labels rnd,rpd,prnd,prpd,anres,apres + calma 66 0 + layer CRE rnw,rp,rnd,rpd,pres,anres,apres + labels rnw,rp,rnd,rpd,pres,anres,apres + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 + layer CRQ rm4,prm4 + labels rm4,prm4 + calma 74 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + +end + +cifinput + +style lambda=0.20(p) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and-not CV1 + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and-not CV1 + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and CV1 + and CV2 + and-not CV3 + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and CV1 + and CV2 + and-not CV3 + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and-not CV3 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and-not CV3 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer gv3 CV3 + and-not COP + and-not CM3 + calma CV3 30 * + + layer gv3 CV3 + and-not COP + and-not CM4 + calma CV3 30 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCP + and-not CCA + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + layer m2c CV1 + and CV2 + and CV3 + and-not CCC + and-not CCP + and-not CCA + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and-not CV2 + and CCP + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and-not CV2 + and CCC + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and CV2 + and CV3 + and CCP + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and CV2 + and CV3 + and CCC + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer ndm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and-not CV2 + and CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and-not CV2 + and CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + and-not CV3 + and-not CV1 + and-not XP + grow 20 + and CM3 + and CM2 + grow 10 + shrink 10 + calma CV2 61 * + + layer m123c CV2 + and-not CV3 + and CV1 + and-not XP + grow 20 + and CM3 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer m234c CV3 + + and CV2 + and-not XP + grow 20 + and CM4 + and CM3 + and CM2 + grow 20 + shrink 20 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + and-not XP + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer m4c CV3 + + and-not CV2 + and-not XP + grow 20 + and CM4 + and CM3 + grow 20 + shrink 20 + calma CV3 30 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + +#CRE/CRM + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(s) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and-not CV1 + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and-not CV1 + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and CV1 + and CV2 + and-not CV3 + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and CV1 + and CV2 + and-not CV3 + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and-not CV3 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and-not CV3 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer gv3 CV3 + and-not COP + and-not CM3 + calma CV3 30 * + + layer gv3 CV3 + and-not COP + and-not CM4 + calma CV3 30 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCP + and-not CCA + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + layer m2c CV1 + and CV2 + and CV3 + and-not CCC + and-not CCP + and-not CCA + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and-not CV2 + and CCP + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and-not CV2 + and CCC + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and CV2 + and CV3 + and CCP + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and CV2 + and CV3 + and CCC + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer ndm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and-not CV2 + and CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and-not CV2 + and CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + and-not CV3 + and-not CV1 + and-not XP + grow 20 + and CM3 + and CM2 + grow 10 + shrink 10 + calma CV2 61 * + + layer m123c CV2 + and-not CV3 + and CV1 + and-not XP + grow 20 + and CM3 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer m234c CV3 + + and CV2 + and-not XP + grow 20 + and CM4 + and CM3 + and CM2 + grow 20 + shrink 20 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + and-not XP + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer m4c CV3 + + and-not CV2 + and-not XP + grow 20 + and CM4 + and CM3 + grow 20 + shrink 20 + calma CV3 30 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + +#CRE/CRM + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(ps) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and-not CV1 + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and-not CV1 + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and CV1 + and CV2 + and-not CV3 + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and CV1 + and CV2 + and-not CV3 + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and-not CV3 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and-not CV3 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer gv3 CV3 + and-not COP + and-not CM3 + calma CV3 30 * + + layer gv3 CV3 + and-not COP + and-not CM4 + calma CV3 30 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCP + and-not CCA + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + layer m2c CV1 + and CV2 + and CV3 + and-not CCC + and-not CCP + and-not CCA + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and-not CV2 + and CCP + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and-not CV2 + and CCC + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and CV2 + and CV3 + and CCP + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and CV2 + and CV3 + and CCC + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer ndm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and-not CV2 + and CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and-not CV2 + and CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + and-not CV3 + and-not CV1 + and-not XP + grow 20 + and CM3 + and CM2 + grow 10 + shrink 10 + calma CV2 61 * + + layer m123c CV2 + and-not CV3 + and CV1 + and-not XP + grow 20 + and CM3 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer m234c CV3 + + and CV2 + and-not XP + grow 20 + and CM4 + and CM3 + and CM2 + grow 20 + shrink 20 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + and-not XP + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer m4c CV3 + + and-not CV2 + and-not XP + grow 20 + and CM4 + and CM3 + grow 20 + shrink 20 + calma CV3 30 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + +#CRE/CRM + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20() + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and-not CV1 + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and-not CV1 + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and CV1 + and CV2 + and-not CV3 + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and CV1 + and CV2 + and-not CV3 + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CV3 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CV3 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and-not CV3 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and CV1 + and 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+ and-not COP + and-not CM4 + calma CV3 30 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCP + and-not CCA + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + layer m2c CV1 + and CV2 + and CV3 + and-not CCC + and-not CCP + and-not CCA + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and-not CV2 + and CCP + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and-not CV2 + and CCC + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and CV2 + and CV3 + and CCP + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer pm12c CV1 + and CV2 + and CV3 + and CCC + grow 20 + and CM2 + and CM1 + and CPG + grow 10 + shrink 10 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer ndm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and-not CV2 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and-not CV2 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and-not CV2 + and CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and-not CV2 + and CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer ndm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer pdm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and-not CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer psm12c CAA + and CSP + and CV1 + and CV2 + and CV3 + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and-not CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and CWNR + and-not CTA + and CCA + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer nwsm12c CAA + and CSN + and CV1 + and CV2 + and CV3 + and CWNR + and-not CTA + and CCC + grow 20 + and CM1 + and CM2 + + and CWN + grow 10 + shrink 10 + calma CV1 50 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + and-not CV3 + and-not CV1 + and-not XP + grow 20 + and CM3 + and CM2 + grow 10 + shrink 10 + calma CV2 61 * + + layer m123c CV2 + and-not CV3 + and CV1 + and-not XP + grow 20 + and CM3 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer m234c CV3 + + and CV2 + and-not XP + grow 20 + and CM4 + and CM3 + and CM2 + grow 20 + shrink 20 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + and-not XP + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer m4c CV3 + + and-not CV2 + and-not XP + grow 20 + and CM4 + and CM3 + grow 20 + shrink 20 + calma CV3 30 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + +#CRE/CRM + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(c) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer gv3 CV3 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + +#CRE/CRM + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(cs) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer gv3 CV3 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + +#CRE/CRM + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(cps) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer gv3 CV3 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + +#CRE/CRM + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(cp) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer gv3 CV3 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + +#CRE/CRM + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + +style fill-only + scalefactor 20 +# scalefactor 100 + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + or fb + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + +end + +mzrouter + style irouter +# layer hCost vCost jogCost hintCost + layer metal4 2 1 2 1 + layer metal3 1 2 2 1 + layer metal2 2 1 2 1 + layer metal1 2 3 2 1 + layer poly 10 10 11 1 + contact m4contact metal4 metal3 4 + contact m3contact metal3 metal2 5 + contact m2contact metal2 metal1 6 + contact pcontact metal1 poly 7 + notactive poly pcontact + +style garouter + layer m2 32 64 256 1 + layer m1 64 32 256 1 + contact m2contact metal1 metal2 1024 + +end + +drc + width nwell 12 \ + "N-well width < 12 (Mosis #1.1)" + + width rnw 12 \ + "rnwell (for resistor L/W extraction) width < 12 (Mosis #1.1)" + + width nwr 12 \ + "nwr (for Fig1b resistor L/W extraction) width < 12 (Mosis #Fig1bX)" + + width pwell 12 \ + "P-well width < 12 (Mosis #1.1)" + + width diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 \ + "Diffusion width < 3 (Mosis #2.1)" + + edge4way nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a pdiff,apres,rpd,pdc/a,pdm12c/a 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active pdiff,apres,rpd,pdc/a,pdm12c/a 3 \ + "P-Diffusion width in N-Ohmic < 3 (Mosis #2.1)" active + + edge4way psd,psc/a,psm12c/a ndiff,anres,rnd,ndc/a,ndm12c/a 3 ~(psd,psc/a,psm12c/a)/active ndiff,anres,rnd,ndc/a,ndm12c/a 3 \ + "N-Diffusion width in P-Ohmic < 3 (Mosis #2.1)" active + + edge4way pdiff,apres,rpd,pdc/a,pdm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 ~(pdiff,apres,rpd,pdc/a,pdm12c/a)/active nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 \ + "N-Ohmic width in P-Diffusion < 3 (Mosis #2.1)" active + + edge4way ndiff,anres,rnd,ndc/a,ndm12c/a psd,psc/a,psm12c/a 3 ~(ndiff,anres,rnd,ndc/a,ndm12c/a)/active psd,psc/a,psm12c/a 3 \ + "P-Ohmic width in N-Diffusion < 3 (Mosis #2.1)" active + + width poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet,fet 2 \ + "Poly width < 2 (Mosis #3.1)" + + width nselect 3 \ + "N-Select width < 3 (Mosis #4.4)" + + width pselect 3 \ + "P-Select width < 3 (Mosis #4.4)" + + width ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a 3 \ + "N-Diffusion,N-Ohmic width < 3 (Mosis #4.4)" + + width pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a 3 \ + "P-Diffusion,P-Ohmic width < 3 (Mosis #4.4)" + + width pc/m1 4 \ + "Poly contact width < 4 (Mosis #5.1)" + + width pm12c/m1 4 \ + "Poly contact width < 4 (Mosis #5.1)" + + width gc 2 \ + "GC contact width < 2 (Mosis #6.1)" + + width ndc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width ndm12c/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width nsc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width nwsc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width nsm12c/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width nwsm12c/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width nwsc 6 \ + "nwr (for Fig1b resistor) active Contact width < 6 (Mosis #Fig1b)" + + width pdc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width pdm12c/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width psc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width psm12c/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 3 \ + "Metal1 width < 3 (Mosis #7.1)" + + width gv1 2 \ + "GV1 via width < 2 (Mosis #8.1)" + + width m2c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width pdm12c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width ndm12c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width psm12c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width nsm12c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width pm12c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width m123c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width nwsm12c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 3 \ + "Metal2 width < 3 (Mosis #9.1)" + + width gv2 2 \ + "GV2 via width < 2 (Mosis #14.1)" + + width m3c/m2 4 \ + "Metal3 contact width < 4 (Mosis #14.1)" + + width m123c/m2 4 \ + "Metal3 contact width < 4 (Mosis #14.1)" + + width m234c/m2 4 \ + "Metal3 contact width < 4 (Mosis #14.1)" + + width m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 3 \ + "Metal3 width < 3 (Mosis #15.1)" + + width sb,pres,anres,apres 4 \ + "Silicide-Block width < 4 (Mosis #20.1)" + + width pres 5 \ + "Silicide-Block polyR width < 5 (Mosis #20.6)" + + width anres,apres 6 \ + "Silicide-Block activeR width < 6 (Mosis #20.16)" + + width gv3 2 \ + "GV3 via width < 2 (Mosis #21.3)" + + width m4c/m3 4 \ + "Metal4 contact width < 4 (Mosis #21.3)" + + width m234c/m3 4 \ + "Metal4 contact width < 4 (Mosis #21.3)" + + width m4,fm4,rm4,m4c/m4,m234c/m4,pad 3 \ + "Metal4 width < 3 (Mosis #22.1)" + + width nfi,pfi 4 \ + "N/P_field-implant width < 4 (Mosis #29.1)" + + spacing nwell nwell 6 touching_ok \ + "N-well(at-same-potential) spacing < 6 (Mosis #1.3)" + + spacing pwell pwell 6 touching_ok \ + "P-well(at-same-potential) spacing < 6 (Mosis #1.3)" + + spacing rnw nwell 18 touching_illegal \ + "rnw (for resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" + + spacing nwr nwell 18 touching_illegal \ + "nwr (for Fig1b resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" + + edge4way ~(pwell)/well pwell 1 ~(rnw)/active 0 0 \ + "P-well cannot touch rnw (for resistor L/W extraction) (Mosis #1.4)" active + + edge4way ~(pwell)/well pwell 1 ~(nwr)/active 0 0 \ + "P-well cannot touch nwr (for Fig1b resistor L/W extraction) (Mosis #1.4)" active + + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 touching_ok \ + "Diffusion spacing < 3 (Mosis #2.2)" + + spacing nwell ndiff,anres,rnd,nfet,ndc/a,ndm12c/a 6 touching_illegal \ + "N-well spacing to N-Diffusion < 6 (Mosis #2.3)" + + spacing pwell pdiff,apres,rpd,pfet,pdc/a,pdm12c/a 6 touching_illegal \ + "P-well spacing to P-Diffusion < 6 (Mosis #2.3)" + + spacing ndiff,anres,rnd,nfet,ndc/a,ndm12c/a pdiff,apres,rpd,pfet,pdc/a,pdm12c/a 12 touching_illegal \ + "N-Diffusion spacing to P-Diffusion < 12 (Mosis #2.3+2.3)" + + edge4way ~(nwell)/well nwell 6 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active nwell 6 \ + "N-well overlap of P-Diffusion < 6 (Mosis #2.4)" active + + edge4way ~(pwell)/well pwell 6 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active pwell 6 \ + "P-well overlap of N-Diffusion < 6 (Mosis #2.4)" active + + edge4way ~(nwell)/well nwell 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active nwell 3 \ + "N-well overlap of N-Ohmic < 3 (Mosis #2.4)" active + + edge4way ~(pwell)/well pwell 3 ~(psd,psc/a,psm12c/a)/active pwell 3 \ + "P-well overlap of P-Ohmic < 3 (Mosis #2.4)" active + + spacing ndiff,anres,rnd,ndc/a,ndm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 9 touching_illegal \ + "N-Diffusion spacing to N-Ohmic < 9 (Mosis #2.3+2.4)" + + spacing pdiff,apres,rpd,pdc/a,pdm12c/a psd,psc/a,psm12c/a 9 touching_illegal \ + "P-Diffusion spacing to P-Ohmic < 9 (Mosis #2.3+2.4)" + + spacing nwell psd,psc/a,psm12c/a 3 touching_illegal \ + "N-well spacing to P-Ohmic < 3 (Mosis #2.4)" + + spacing pwell nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 touching_illegal \ + "P-well spacing to N-Ohmic < 3 (Mosis #2.4)" + + spacing psd,psc/a,psm12c/a rnw,prnw 3 touching_illegal \ + "P-Ohmic spacing to rnw,prnw < 3 (Mosis #2.4)" + + spacing psd,psc/a,psm12c/a nwr,pnwr 3 touching_illegal \ + "P-Ohmic spacing to nwr,pnwr (for Fig1b Resistor) < 3 (Mosis #2.4)" + + spacing nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a psd,psc/a,psm12c/a 6 touching_illegal \ + "N-Ohmic spacing to P-Ohmic < 6 (Mosis #2.4+2.4)" + + spacing ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nfet psd,psc/a,psm12c/a 4 touching_ok \ + "N-Diffusion spacing to P-Ohmic < 4 (Mosis #2.5)" + + spacing pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,pfet nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 4 touching_ok \ + "P-Diffusion spacing to N-Ohmic < 4 (Mosis #2.5)" + + spacing poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet 3 touching_ok \ + "Poly spacing < 3 (Mosis #3.2)" + + spacing poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ + "Poly spacing to fill layer (fp) < 3 (Mosis #3.2)" + + spacing fp fp 4 touching_ok \ + "Poly fill layer (fp) spacing < 4 (Mosis #0)" + + edge4way nfet,pfet,fet space/active,poly,fp,pres,rp,pc/a,pm12c/a 2 poly,fp,pres,rp,pc/a,pm12c/a 0 0 \ + "Poly overhang of Transistor < 2 (Mosis #3.3)" active + + edge4way nfet,pfet,fet space/active,ndiff,anres,rnd,ndc/a,ndm12c/a,pdiff,apres,rpd,pdc/a,pdm12c/a 3 ndiff,anres,rnd,ndc/a,ndm12c/a,pdiff,apres,rpd,pdc/a,pdm12c/a,nfet,pfet,fet 0 0 \ + "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active + + edge4way poly,fp,rp,pc/a,pm12c/a ~(poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet,fet,prp)/active 1 space space 1 \ + "Poly spacing to Diffusion < 1 (Mosis #3.5)" + + edge4way nfet ~(nfet)/active 2 ~(pselect)/select ~(nfet)/active 2 \ + "N-Transistor space to P-Select < 2 (Mosis #4.1)" select + + edge4way pfet ~(pfet)/active 2 ~(nselect)/select ~(pfet)/active 2 \ + "P-Transistor space to N-Select < 2 (Mosis #4.1)" select + + edge4way nfet ~(nfet)/active 3 ~(psd,psc/a,psm12c/a)/active ~(nfet)/active 2 \ + "N-Transistor space to P-Ohmic < 3 (Mosis #4.1)" active + + edge4way pfet ~(pfet)/active 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active ~(pfet)/active 2 \ + "P-Transistor space to N-Ohmic < 3 (Mosis #4.1)" active + +#PEZ edge4way psd,psc/a,psm12c/a space ~(nfet)/active space \ +#PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active + +#PEZ edge4way nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a space ~(pfet)/active space \ +#PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active + + edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active nselect,pselect 2 \ + "N-Select,P-Select overlap of Diffusion < 2 (Mosis #4.2_)" active + + edge4way space nselect,pselect 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active nselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2a)" active + + edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active nselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2b)" active + + edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active space,nselect,pselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2c)" active + + edge4way space nselect,pselect 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2aa)" active + + edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2bb)" active + + edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active space,nselect,pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2cc)" active + + area nsd,nwsd,psd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,psc/a,psm12c/a 16 3 \ + "Ohmic-Diffusion area < 16 (Mosis #+++)" + + edge4way diff space 2 nselect space 2 \ + "N-Select must overlap Diffusion by 2 (Mosis #4.2)" select + + edge4way diff space 2 pselect space 2 \ + "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select + + edge4way ndiff,anres,rnd,nfet,ndc/a,ndm12c/a space 2 ~(pselect)/select space 2 \ + "P-Select space to N-Diffusion < 2 (Mosis #4.2e)" select + + edge4way pdiff,apres,rpd,pfet,pdc/a,pdm12c/a space 2 ~(nselect)/select space 2 \ + "N-Select space to P-Diffusion < 2 (Mosis #4.2e)" select + + edge4way ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,psd,psc/a,psm12c/a)/active pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,psd,psc/a,psm12c/a 1 ~(nselect)/select 0 0 \ + "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select + + edge4way ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 ~(pselect)/select 0 0 \ + "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select + + spacing nselect nselect 3 touching_ok \ + "N-Select spacing < 3 (Mosis #4.4)" + + spacing pselect pselect 3 touching_ok \ + "P-Select spacing < 3 (Mosis #4.4)" + + edge4way ndiff,anres,rnd,ndc/a,ndm12c/a psd,psc/a,psm12c/a 2 ~(ndiff,anres,rnd,ndc/a,ndm12c/a)/active 0 0 \ + "P-Ohmic(that touches N-Diffusion) width < 2 (Mosis #4.4)" + + edge4way pdiff,apres,rpd,pdc/a,pdm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 ~(pdiff,apres,rpd,pdc/a,pdm12c/a)/active 0 0 \ + "N-Ohmic(that touches P-Diffusion) width < 2 (Mosis #4.4)" + + edge4way gc ~(gc)/contact 1 poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a ~(gc)/contact 1 \ + "Poly,Diffusion overlap of GC contact < 1 (Mosis #5.2)" active + + edge4way ~(nwsd)/active nwsd 2 ~(gc)/contact nwsd 2 \ + "nwr (for Fig1b resistor) active overlap of GC contact < 2 (Mosis #Fig1b)" contact + + spacing nwr gc 5 touching_illegal \ + "nwr (for Fig1b resistor) spacing to GC contact < 5 (Mosis #Fig1b)" + + spacing nwr ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 touching_illegal \ + "nwr (for Fig1b resistor) spacing to Diffusion contact < 3 (Mosis #Fig1b)" + + edge4way gc space 1 poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a space 1 \ + "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active + + edge4way ~(poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 1 ~(gc)/contact 0 0 \ + "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact + + spacing gc gc 3 touching_ok \ + "Generic contact spacing < 3 (Mosis #5.3)" + + edge4way ~(gc)/contact gc 1 ~(ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1)/metal1 0 0 \ + "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 + + spacing gv1 m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2 2 touching_illegal \ + "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" + +#PSC spacing poly,fp,pres,rp,pc/a,pm12c/a pc/a,pm12c/a 4 touching_ok \ +#PSC "Poly spacing to Poly contact < 4 (Mosis #5.5.b)" + + edge4way gc ~(gc)/contact 1 diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,poly,fp,pres,rp,pc/a,pm12c/a ~(gc)/contact 1 \ + "Diffusion,Poly overlap of GC contact < 1 (Mosis #6.2)" active + + spacing gc pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 touching_illegal \ + "Generic contact spacing to Poly contact,Diffusion contact < 2 (Mosis #5.3)" + + spacing nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1 pdc/m1,pdm12c/m1 1 touching_illegal \ + "nsc spacing to pdc < 1 (Mosis #6.3)" + + spacing psc/m1,psm12c/m1 ndc/m1,ndm12c/m1 1 touching_illegal \ + "psc spacing to ndc < 1 (Mosis #6.3)" + + spacing pdm12c/m1 pdc/m1,m2c/m1,nsm12c/m1 1 touching_illegal \ + "pdm12c spacing to pdc or m2c or nsm12c < 1 (Mosis #6.3)" + + spacing psm12c/m1 psc/m1,m2c/m1 1 touching_illegal \ + "psm12c spacing to psc or m2c < 1 (Mosis #6.3)" + + spacing ndm12c/m1 ndc/m1,m2c/m1,nsm12c/m1 1 touching_illegal \ + "ndm12c spacing to ndc or m2c or nsm12c < 1 (Mosis #6.3)" + + spacing nsm12c/m1 nsc/m1,m2c/m1 1 touching_illegal \ + "nsm12c spacing to nsc or m2c < 1 (Mosis #6.3)" + + spacing pm12c/m1 pc/m1,m2c/m1 1 touching_illegal \ + "pm12c spacing to pc or m2c < 1 (Mosis #6.3)" + + spacing m123c/m2 pdm12c/m2,psm12c/m2,ndm12c/m2,nsm12c/m2,pm12c/m2,m2c/m2,m3c/m2 1 touching_illegal \ + "m123c spacing to *m12c or m2c or m3c < 1 (Mosis #6.3)" + + spacing m234c/m3 m3c/m3,m4c/m3,m123c/m3 1 touching_illegal \ + "m234c spacing to m3c or m4c or m123c < 1 (Mosis #6.3)" + + spacing nfet,pfet ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 touching_illegal \ + "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" + + spacing nfet,pfet gc 2 touching_illegal \ + "N-Transistor,P-Transistor spacing to Generic contact < 2 (Mosis #6.4)" + + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a pc/a,pm12c/a 1 touching_illegal \ + "Diffusion spacing to Poly contact < 1 (Mosis #6.5.b)" + + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nfet,pfet ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 4 touching_ok \ + "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" + + spacing pc/a,pm12c/a ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 touching_illegal \ + "pc/a,pm12c/a spacing to ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a < 2 (Mosis #6.7)" + + spacing m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 3 touching_ok \ + "Metal1 spacing < 3 (Mosis #7.2)" + + spacing m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 fm1,fapm 3 touching_illegal \ + "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" + + spacing fm1 fm1 4 touching_ok \ + "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" + + edge4way gc space 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 space 1 \ + "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1)/metal1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 1 ~(gc)/contact 0 0 \ + "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact + + spacing gv1 gv1 3 touching_ok \ + "GV1 via spacing < 3 (Mosis #8.2)" + + edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 ~(gv1)/via1 1 \ + "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 + + edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 space 1 \ + "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1)/metal1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 1 ~(gv1)/via1 0 0 \ + "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 + + spacing m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 3 touching_ok \ + "Metal2 spacing < 3 (Mosis #9.2)" + + spacing m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 fm2,fapm 3 touching_illegal \ + "Metal2 spacing to fill layer (fm2) < 3 (Mosis #9.2)" + + spacing fm2 fm2 4 touching_ok \ + "Metal2 fill layer (fm2) spacing < 4 (Mosis #0)" + + edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 space 1 \ + "Metal2 must overlap GV1 via by 1 (Mosis #9.3)" metal2 + + edge4way ~(m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2)/metal2 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 1 ~(gv1)/via1 0 0 \ + "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 + + width glass 10 \ + "COG width < 10 (Mosis #10.2)" + + edge4way ~(pad)/metal4 pad 30 ~(glass)/oxide pad 30 \ + "pad overlap of COG < 30 (Mosis #10.3)" oxide + + spacing gv2 gv2 3 touching_ok \ + "GV2 via spacing < 3 (Mosis #14.2)" + + spacing gv2 m3c/m2,m123c/m2,m234c/m2 2 touching_illegal \ + "GV2 via spacing to Metal3 contact < 2 (Mosis #14.2)" + + edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 space 1 \ + "Metal2 must overlap GV2 via by 1 (Mosis #14.3)" metal2 + + edge4way ~(m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2)/metal2 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 1 ~(gv2)/via2 0 0 \ + "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 + + spacing m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 3 touching_ok \ + "Metal3 spacing < 3 (Mosis #15.2)" + + spacing m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 fm3,fapm 3 touching_illegal \ + "Metal3 spacing to fill layer (fm3) < 3 (Mosis #15.2)" + + spacing fm3 fm3 4 touching_ok \ + "Metal3 fill layer (fm3) spacing < 4 (Mosis #0)" + + edge4way gv2 space 1 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 space 1 \ + "Metal3 must overlap GV2 via by 1 (Mosis #15.3)" metal3 + + edge4way ~(m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 1 ~(gv2)/via2 0 0 \ + "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 + + spacing sb,pres,anres,apres sb,pres,anres,apres 4 touching_ok \ + "Silicide-Block spacing < 4 (Mosis #20.2)" + + spacing sb,pres,anres,apres,pres,anres,apres pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 touching_illegal \ + "Silicide-Block spacing to Diffusion contact,Poly contact < 1 (Mosis #20.3)" + + spacing sb,pres,anres,apres,pres,anres,apres gc 2 touching_illegal \ + "Silicide-Block spacing to GC contact < 2 (Mosis #20.3)" + + edge4way sb,pres,anres,apres space 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active 0 2 \ + "Silicide-Block space to Diffusion < 2 (Mosis #20.4)" active + + spacing sb,pres,anres,apres,pres poly,fp,pres,rp,pc/a,pm12c/a 2 touching_ok \ + "Silicide-Block spacing to other Poly < 2 (Mosis #20.5)" + + edge4way sb,pres,anres,apres space 2 ~(poly,fp,pres,rp,pc/a,pm12c/a)/contact sb,pres,anres,apres 2 \ + "Silicide-Block space to Poly < 2 (Mosis #20.5x)" contact + + spacing sb,pres,anres,apres,pres nfet,pfet,fet 2 touching_ok \ + "Silicide-Block spacing to other Transistor < 2 (Mosis #20.5)" + + edge4way sb,pres,anres,apres space 2 ~(nfet,pfet,fet)/contact sb,pres,anres,apres 2 \ + "Silicide-Block space to Transistor < 2 (Mosis #20.5x)" contact + + spacing pres pres 7 touching_ok \ + "Silicide-Block polyR spacing < 7 (Mosis #20.13)" + + edge4way pres,anres,apres space/active,sb 2 sb sb 2 \ + "Silicide-Block overlap of Silicide-Block polyR/activeR < 2 (Mosis #20.15)" + + edge4way sb,pres,anres,apres diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 0 0 \ + "Diffusion overhang of Silicide-Block < 3 (Mosis #20.17) + + spacing gv3 gv3 3 touching_ok \ + "GV3 via spacing < 3 (Mosis #21.2)" + + spacing gv3 m4c/m3,m234c/m3 2 touching_illegal \ + "GV3 via spacing to Metal4 contact < 2 (Mosis #21.2)" + + edge4way gv3 space 1 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 space 1 \ + "Metal3 must overlap GV3 via by 1 (Mosis #21.3)" metal3 + + edge4way ~(m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 1 ~(gv3)/via3 0 0 \ + "Metal3(edge) cannot touch GV3 via (Mosis #21.3)" via3 + + spacing m4,rm4,m4c/m4,m234c/m4,pad m4,rm4,m4c/m4,m234c/m4,pad 3 touching_ok \ + "Metal4 spacing < 3 (Mosis #22.2)" + + spacing m4,rm4,m4c/m4,m234c/m4,pad fm4,fapm 3 touching_illegal \ + "Metal4 spacing to fill layer (fm4) < 3 (Mosis #22.2)" + + spacing fm4 fm4 4 touching_ok \ + "Metal4 fill layer (fm4) spacing < 4 (Mosis #0)" + + edge4way gv3 space 1 m4,fm4,rm4,m4c/m4,m234c/m4,pad space 1 \ + "Metal4 must overlap GV3 via by 1 (Mosis #22.3)" metal4 + + edge4way ~(m4,fm4,rm4,m4c/m4,m234c/m4,pad)/metal4 m4,fm4,rm4,m4c/m4,m234c/m4,pad 1 ~(gv3)/via3 0 0 \ + "Metal4(edge) cannot touch GV3 via (Mosis #22.3)" via3 + + spacing nfi nfi 4 touching_ok \ + "N_field-implant spacing < 4 (Mosis #35.2)" + + spacing pfi pfi 4 touching_ok \ + "P_field-implant spacing < 4 (Mosis #35.2)" + + spacing nfi pfi 4 touching_illegal \ + "N_field-implant spacing to P_field-implant < 4 (Mosis #35.2)" + + spacing nwell,pdiff,apres,rpd,pfet,pdc/a,pdm12c/a pfi 4 touching_illegal \ + "N-well,P-Diffusion spacing to P_field-implant < 4 (Mosis #2.1)" + + spacing pwell,ndiff,anres,rnd,nfet,ndc/a,ndm12c/a nfi 4 touching_illegal \ + "P-well,N-Diffusion spacing to N_field-implant < 4 (Mosis #2.1)" + + edge4way ~(nwell)/well nwell 4 ~(nfi)/implant nwell 4 \ + "N-well overlap of N_field-implant < 4 (Mosis #21.2)" implant + + edge4way ~(pwell)/well pwell 4 ~(pfi)/implant pwell 4 \ + "P-well overlap of P_field-implant < 4 (Mosis #21.2)" implant + + spacing fa fapm 4 touching_illegal \ + "fill layer fa spacing to fill layer fapm < 4 (Mosis #0)" + + width fa 10 \ + "filla width < 10 (Mosis #0)" + + width fapm 10 \ + "fillapm width < 10 (Mosis #0)" + + width fp 10 \ + "fillp width < 10 (Mosis #0)" + + width fm1 10 \ + "fillm1 width < 10 (Mosis #0)" + + width fm2 10 \ + "fillm2 width < 10 (Mosis #0)" + + width fm3 10 \ + "fillm3 width < 10 (Mosis #0)" + + width fm4 10 \ + "fillm4 width < 10 (Mosis #0)" + + edge4way fa ~(fa)/fill 1 ~(fa)/fill (~(fa),fa)/fill 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fb ~(fb)/fill 1 ~(fb)/fill (~(fb),fb)/fill 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fapm ~(fapm)/active 1 ~(fapm)/active (~(fapm),fapm)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fp ~(fp)/active 1 ~(fp)/active (~(fp),fp)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm1 ~(fm1)/metal1 1 ~(fm1)/metal1 (~(fm1),fm1)/metal1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm2 ~(fm2)/metal2 1 ~(fm2)/metal2 (~(fm2),fm2)/metal2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm3 ~(fm3)/metal3 1 ~(fm3)/metal3 (~(fm3),fm3)/metal3 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm4 ~(fm4)/metal4 1 ~(fm4)/metal4 (~(fm4),fm4)/metal4 1 \ + "Contact not rectangular (Magic rule)" + + edge4way rp space/active 1 prp 0 0 \ + "prp overhang of rpoly (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rnw space/active 1 prnw 0 0 \ + "prnw overhang of rnwell (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way nwr space/active 1 pnwr 0 0 \ + "pnwr overhang of nwr (for Fig1b resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rpd space/active 1 prpd 0 0 \ + "prpd overhang of rpdiff (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rnd space/active 1 prnd 0 0 \ + "prnd overhang of rndiff (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rm1 space/metal1 1 prm1 0 0 \ + "prm1 overhang of rmetal1 (for resistor L/W extraction) < 1 (Mosis #0)" metal1 + + edge4way rm2 space/metal2 1 prm2 0 0 \ + "prm2 overhang of rmetal2 (for resistor L/W extraction) < 1 (Mosis #0)" metal2 + + edge4way rm3 space/metal3 1 prm3 0 0 \ + "prm3 overhang of rmetal3 (for resistor L/W extraction) < 1 (Mosis #0)" metal3 + + edge4way rm4 space/metal4 1 prm4 0 0 \ + "prm4 overhang of rmetal4 (for resistor L/W extraction) < 1 (Mosis #0)" metal4 + + edge4way ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a ~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active 1 ~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active (~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a),ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way pdc/a,pdm12c/a,psc/a,psm12c/a ~(pdc/a,pdm12c/a,psc/a,psm12c/a)/active 1 ~(pdc/a,pdm12c/a,psc/a,psm12c/a)/active (~(pdc/a,pdm12c/a,psc/a,psm12c/a),pdc/a,pdm12c/a,psc/a,psm12c/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way pc/a,pm12c/a ~(pc/a,pm12c/a)/active 1 ~(pc/a,pm12c/a)/active (~(pc/a,pm12c/a),pc/a,pm12c/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 ~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 1 ~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 (~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1),m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m3c/m2,m123c/m2,m234c/m2 ~(m3c/m2,m123c/m2,m234c/m2)/metal2 1 ~(m3c/m2,m123c/m2,m234c/m2)/metal2 (~(m3c/m2,m123c/m2,m234c/m2),m3c/m2,m123c/m2,m234c/m2)/metal2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv3 ~(gv3)/via3 1 ~(gv3)/via3 (~(gv3),gv3)/via3 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m4c/m3,m234c/m3 ~(m4c/m3,m234c/m3)/metal3 1 ~(m4c/m3,m234c/m3)/metal3 (~(m4c/m3,m234c/m3),m4c/m3,m234c/m3)/metal3 1 \ + "Contact not rectangular (Magic rule)" + + exact_overlap gc,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,pc/a,pm12c/a,gc + + edge4way pad ~(pad)/m4 1 ~(pad)/m4 (~(pad),pad)/m4 1 \ + "Contact not rectangular (Magic rule)" + + exact_overlap ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1 + + exact_overlap m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2 + + exact_overlap m3c/m3,m123c/m3,m234c/m3 + + exact_overlap m4c/m4,m234c/m4 + + exact_overlap gv1 + + exact_overlap gv2 + + exact_overlap gv3 + + edge4way nfet,pfet,fet ~(nfet,pfet,fet)/active 1 ~(nfet,pfet,fet)/active nfet,pfet,fet 1 \ + "Transistor cannot bend in this process (Mosis #?.?)" + + width m1p 4 \ + "Metal1 PIN width < 4 (do_pins)" + + spacing m1p m1p 4 touching_ok \ + "Metal1 PIN spacing < 4 (do_pins)" + + width m2p 4 \ + "Metal2 PIN width < 4 (do_pins)" + + spacing m2p m2p 4 touching_ok \ + "Metal2 PIN spacing < 4 (do_pins)" + + width m3p 4 \ + "Metal3 PIN width < 4 (do_pins)" + + spacing m3p m3p 4 touching_ok \ + "Metal3 PIN spacing < 4 (do_pins)" + + width m4p 4 \ + "Metal4 PIN width < 4 (do_pins)" + + spacing m4p m4p 4 touching_ok \ + "Metal4 PIN spacing < 4 (do_pins)" + +#CC cifstyle lambda=0.20(p) +#CC cifwidth CWN 240 \ +#CC "generated CIF layer CWN width will be < 12 (';cif see CWN')" +#CC cifspacing CWN CWN 120 touching_ok \ +#CC "generated CIF layer CWN spacing will be < 6 (';cif see CWN')" +#CC cifwidth CWP 240 \ +#CC "generated CIF layer CWP width will be < 12 (';cif see CWP')" +#CC cifspacing CWP CWP 120 touching_ok \ +#CC "generated CIF layer CWP spacing will be < 6 (';cif see CWP')" +#CC cifwidth CSN 60 \ +#CC "generated CIF layer CSN width will be < 3 (';cif see CSN')" +#CC cifspacing CSN CSN 60 touching_ok \ +#CC "generated CIF layer CSN spacing will be < 3 (';cif see CSN')" +#CC cifwidth CSP 60 \ +#CC "generated CIF layer CSP width will be < 3 (';cif see CSP')" +#CC cifspacing CSP CSP 60 touching_ok \ +#CC "generated CIF layer CSP spacing will be < 3 (';cif see CSP')" + + stepsize 400 + +end + +#--------------------------------------------------- +# LEF format definitions +#--------------------------------------------------- + +lef + + ignore PC + ignore CA + + routing m1 M1 m1 met1 + routing m2 M2 m2 met2 + routing m3 M3 m3 met3 + routing m4 M4 m4 met4 + + contact m2c via1 V1 v1 + contact m3c via2 V2 v2 + contact m4c via3 V3 v3 + +end + +#--------------------------------------------------- + +extract + style TSMC0.35um(tsmc35)from:t11c + cscale 1 + lambda 20 + step 100 + sidehalo 8 + planeorder well 0 + planeorder implant 1 + planeorder select 2 + planeorder active 3 + planeorder metal1 4 + planeorder metal2 5 + planeorder metal3 6 + planeorder metal4 7 + planeorder oxide 8 + planeorder xp 9 + planeorder comment 10 + planeorder contact 11 + planeorder via1 12 + planeorder via2 13 + planeorder via3 14 + planeorder fill 15 + + resist (ndiff,anres,rnd,ndc,ndm12c,nsd,nwsd,nsc,nwsc,nsm12c,nwsm12c)/active 3700 + resist (pdiff,apres,rpd,pdc,pdm12c,psd,psc,psm12c)/active 2800 + resist (nwell)/well 1018000 + resist (rnw,nwr)/active 1018000 + resist (pwell)/well 1 + resist (poly,fp,rp,pc,pm12c,pc,pm12c,nfet,pfet,fet)/active 6000 + resist (pres)/active 6000 + resist (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c)/metal1 80 + resist (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c,m3c,m123c,m234c)/metal2 70 + resist (m3,fm3,rm3,m3c,m123c,m234c,m4c,m4c,m234c)/metal3 80 + resist (m4,fm4,rm4,m4c,m234c,pad)/metal4 40 + + contact ndc 4 4100 + contact pdc 4 3400 + contact pc 4 4600 + contact m2c 4 1300 + contact m3c 4 1170 + contact m4c 4 1110 + + +#nwell,cwell,pwell + areacap (nwell)/well 2.360 + +#rnw + areacap (rnw,nwr)/active 2.360 + +#ndiff +# MODEL HANDLES THIS: areacap (ndiff,ndc,ndm12c)/active 43.160 +# MODEL HANDLES THIS: overlap (ndiff,ndc,ndm12c)/active ~space/w 43.160 +# MODEL HANDLES THIS: perimc (ndiff,ndc,ndm12c)/active ~(ndiff,ndc,ndm12c,nfet,pfet,fet)/active 64.200 +# MODEL HANDLES THIS: sideoverlap (ndiff,ndc,ndm12c)/active ~(ndiff,ndc,ndm12c,nfet,pfet,fet)/active ~space/w 64.200 + + areacap (rnd,anres)/active 43.160 + overlap (rnd,anres)/active ~space/w 43.160 + perimc (rnd,anres)/active ~(rnd,anres)/active 64.200 + sideoverlap (rnd,anres)/active ~(rnd,anres)/active ~space/w 64.200 + +#pdiff +# MODEL HANDLES THIS: areacap (pdiff,pdc,pdm12c)/active 55.880 +# MODEL HANDLES THIS: overlap (pdiff,pdc,pdm12c)/active ~space/w 55.880 +# MODEL HANDLES THIS: perimc (pdiff,pdc,pdm12c)/active ~(pdiff,pdc,pdm12c,nfet,pfet,fet)/active 81.800 +# MODEL HANDLES THIS: sideoverlap (pdiff,pdc,pdm12c)/active ~(pdiff,pdc,pdm12c,nfet,pfet,fet)/active ~space/w 81.800 + + areacap (rpd,apres)/active 55.880 + overlap (rpd,apres)/active ~space/w 55.880 + perimc (rpd,apres)/active ~(rpd,apres)/active 81.800 + sideoverlap (rpd,apres)/active ~(rpd,apres)/active ~space/w 81.800 + +#rnw + +#poly +# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,anres,rnd,ndc,ndm12c)/active 181.800 +# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,anres,rnd,ndc,ndm12c)/active 55.400 +# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,apres,rpd,pdc,pdm12c)/active 181.160 +# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,apres,rpd,pdc,pdm12c)/active 52.200 + + sidewall (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active (poly,fp,pres,rp,pc,pm12c)/active 11.331 + areacap (poly,fp,pres,rp,pc,pm12c)/active 4.074 + overlap (poly,fp,pres,rp,pc,pm12c)/active ~space/w 4.074 + perimc (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active 4.622 + sideoverlap (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active ~space/w 4.622 + +#poly2 + +#rnw + +#metal1 + sidewall (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 20.619 + areacap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 1.666 + +#metal1-sub blocked by ~space/a + overlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~space/w 1.666 ~space/a + perimc (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 2.226 + sideoverlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~space/w 2.226 ~space/a + +#rnw + overlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 rnw,nwr/active 1.666 + sideoverlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 rnw,nwr/active 2.226 + +#metal1-diff blocked by + overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (ndiff,anres,rnd,ndc,ndm12c)/active 1.640 + sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (ndiff,anres,rnd,ndc,ndm12c)/active 2.226 + overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (pdiff,apres,rpd,pdc,pdm12c)/active 1.640 + sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (pdiff,apres,rpd,pdc,pdm12c)/active 2.226 + +#metal1-poly blocked by + overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 1.687 + sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 2.250 + sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 2.250 + +#metal2 + sidewall (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 23.532 + areacap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 0.581 + +#metal2-sub blocked by + overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 ~space/w 0.581 ~space/a,~space/m1 + perimc (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.836 + sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~space/w 0.836 ~space/a,~space/m1 + overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 rnw,nwr/active 0.581 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 rnw,nwr/active 0.836 ~space/m1 + +#metal2-*diff blocked by ~space/m1 + overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (ndiff,anres,rnd,ndc,ndm12c)/active 0.720 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (ndiff,anres,rnd,ndc,ndm12c)/active 0.836 ~space/m1 + overlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (pdiff,apres,rpd,pdc,pdm12c)/active 0.720 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (pdiff,apres,rpd,pdc,pdm12c)/active 0.836 ~space/m1 + +#metal2-poly blocked by ~space/m1 + overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.583 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.840 ~space/m1 + sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.840 ~space/m1 + +#M2->M1 + overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 1.844 + sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 2.432 + sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 2.432 + +#metal3 + sidewall (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 24.216 + areacap (m3,fm3,rm3,m4c,m234c)/metal3 0.352 + +#metal3-sub blocked by ~space/a,~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c,m234c)/metal3 ~space/w 0.352 ~space/a,~space/m1,~space/m2 + perimc (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.514 + sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~space/w 0.514 ~space/a,~space/m1,~space/m2 + +#rnw + overlap (m3,fm3,rm3,m4c,m234c)/metal3 rnw,nwr/active 0.352 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 rnw,nwr/active 0.514 ~space/m1,~space/m2 + +#metal3-*diff blocked by ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c,m234c)/metal3 (ndiff,anres,rnd,ndc,ndm12c)/active 0.520 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (ndiff,anres,rnd,ndc,ndm12c)/active 0.514 ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c,m234c)/metal3 (pdiff,apres,rpd,pdc,pdm12c)/active 0.520 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (pdiff,apres,rpd,pdc,pdm12c)/active 0.514 ~space/m1,~space/m2 + +#metal3-poly blocked by ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c,m234c)/metal3 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.352 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.516 ~space/m1,~space/m2 + sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.516 ~space/m1,~space/m2 + +#M3->M1 + +#metal3-metal1 blocked by ~space/m2 + overlap (m3,fm3,rm3,m4c,m234c)/metal3 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.601 ~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.864 ~space/m2 + sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.864 ~space/m2 + +#M3->M2 + overlap (m3,fm3,rm3,m4c,m234c)/metal3 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 1.844 + sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 2.430 + sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 2.430 + +#metal4 + sidewall (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m4,fm4,rm4,m4c,m234c,pad)/metal4 64.860 + areacap (m4,fm4,rm4,pad)/metal4 0.235 + +#metal4-sub blocked by ~space/a,~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 ~space/w 0.235 ~space/a,~space/m1,~space/m2,~space/m3 + perimc (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 0.802 + sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 ~space/w 0.802 ~space/a,~space/m1,~space/m2,~space/m3 + +#rnw + overlap (m4,fm4,rm4,pad)/metal4 rnw,nwr/active 0.235 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 rnw,nwr/active 0.802 ~space/m1,~space/m2,~space/m3 + +#metal4-*diff blocked by ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (ndiff,anres,rnd,ndc,ndm12c)/active 0.400 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (ndiff,anres,rnd,ndc,ndm12c)/active 0.802 ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (pdiff,apres,rpd,pdc,pdm12c)/active 0.400 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (pdiff,apres,rpd,pdc,pdm12c)/active 0.802 ~space/m1,~space/m2,~space/m3 + +#metal4-poly blocked by ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.271 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.666 ~space/m1,~space/m2,~space/m3 + sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m4,fm4,rm4,m4c,m234c,pad)/metal4 0.666 ~space/m1,~space/m2,~space/m3 + +#M4->M1 + +#metal4-metal1 blocked by ~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.359 ~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 1.038 ~space/m2,~space/m3 + sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m4,fm4,rm4,m4c,m234c,pad)/metal4 1.038 ~space/m2,~space/m3 + +#M4->M2 + +#metal4-metal2 blocked by ~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.601 ~space/m3 + sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 1.698 ~space/m3 + sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m4,fm4,rm4,m4c,m234c,pad)/metal4 1.698 ~space/m3 + +#M4->M3 + overlap (m4,fm4,rm4,pad)/metal4 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 1.844 + sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 4.604 + sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m4,fm4,rm4,m4c,m234c,pad)/metal4 4.604 + +#metal5 + +#metal6 + +#metal7 + +#metali + +#fets + +# fet pfet pdiff,pdc 2 pfet Vdd! nwell 52 181 +# fet pfet pdiff,pdc 1 pfet Vdd! nwell 52 181 + + device mosfet pfet pfet pdiff,pdc nwell $VDD 52 181 + +# fet nfet ndiff,ndc 2 nfet Gnd! pwell 55 182 +# fet nfet ndiff,ndc 1 nfet Gnd! pwell 55 182 + + device mosfet nfet nfet ndiff,ndc pwell $GND 55 182 + + fetresis pfet linear 12182 + fetresis pfet saturation 12182 + fetresis nfet linear 3961 + fetresis nfet saturation 3961 + +# fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 +# fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 +# fet nwr nwsd 2 nwellFig1bResistor Gnd! nwell,pwell 0 0 +# fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 +# fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 + + device resistor None rnwell nsd,nsc + device resistor None rpoly poly,pc + device resistor None nwr nwsd + device resistor None rndiff ndiff,ndc + device resistor None rpdiff pdiff,pdc + +# fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 +# fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 +# fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 +# fet rmetal4 metal4 2 metal4Resistor Gnd! nwell,pwell 0 0 + + device resistor None rmetal1 *metal1 + device resistor None rmetal2 *metal2 + device resistor None rmetal3 *metal3 + device resistor None rmetal4 *metal4 + +# fet pres poly,pc 2 presResistor Gnd! nwell,pwell 0 0 +# fet anres ndiff,ndc 2 anresResistor Gnd! nwell,pwell 0 0 +# fet apres pdiff,pdc 2 apresResistor Gnd! nwell,pwell 0 0 + + device resistor None pres poly,pc + device resistor None anres ndiff,ndc + device resistor None apres pdiff,pdc + +end + +wiring + contact pdcontact 4 metal1 0 pdiff 0 + contact ndcontact 4 metal1 0 ndiff 0 + contact pcontact 4 metal1 0 poly 0 + contact m2contact 4 metal1 0 metal2 0 + contact m3contact 5 metal2 0 metal3 1 + contact m4contact 4 metal3 0 metal4 0 + +end + +router + layer2 metal2 3 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 4 poly,fp,pres,rp,ndiff,anres,rnd,nsd,nwsd,pdiff,apres,rpd,psd,m1,fm1,rm1 1 + layer1 metal1 3 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 3 + contacts m2contact 4 + gridspacing 8 + +end + +plowing + fixed nfet,pfet,glass,pad + covered nfet,pfet + drag nfet,pfet + +end + +plot +style colorversatec + ndiff,anres,rnd,ndc/a,ndm12c/a yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + ndiff,anres,rnd,ndc/a,ndm12c/a cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + pdiff,apres,rpd,pdc/a,pdm12c/a yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + pdiff,apres,rpd,pdc/a,pdm12c/a cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + pdiff,apres,rpd,pdc/a,pdm12c/a magenta \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + psd,psc/a,psm12c/a yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + psd,psc/a,psm12c/a cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + psd,psc/a,psm12c/a magenta \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 + poly,fp,pres,rp,pc/a,pm12c/a magenta \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + nfet yellow \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 + nfet cyan \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 + nfet magenta \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A + pfet yellow \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 + pfet cyan \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 + pfet magenta \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 + m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 cyan \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 cyan \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 + m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 magenta \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 + m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1,gv1 black \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 + pad,glass black \ + 0300 0700 0E00 1C00 \ + 3800 7000 E000 C000 \ + 00C0 00E0 0070 0038 \ + 001C 000E 0007 0003 + nwell yellow \ + 0800 1000 2000 4000 \ + 8000 0001 0002 0004 \ + 0008 0010 0020 0040 \ + 0080 0010 0200 0400 + nwell cyan \ + 1000 2000 4000 8000 \ + 0001 0002 0004 0008 \ + 0010 0020 0040 0080 \ + 0100 0200 0400 0800 + pwell yellow \ + 1000 0400 0400 0100 \ + 0100 0040 0040 0010 \ + 0010 0004 0004 0001 \ + 0001 4000 4000 1000 + pwell cyan \ + 0000 0800 0000 0200 \ + 0000 0080 0000 0020 \ + 0000 0008 0000 0002 \ + 0000 8000 0000 2000 + pwell magenta \ + 0800 0000 0200 0000 \ + 0080 0000 0020 0000 \ + 0008 0000 0002 0000 \ + 8000 0000 2000 0000 + m3c/m2,m123c/m2,m234c/m2,gv2 black \ + 0100 0000 0000 0000 \ + 1010 0000 0000 0000 \ + 0001 0000 0000 0000 \ + 1010 0000 0000 0000 + m3c/m2,m123c/m2,m234c/m2,gv2 cyan \ + 0280 0000 0820 0000 \ + 2008 0000 8002 0000 \ + 8002 0000 2008 0000 \ + 0820 0000 0280 0000 + m3c/m2,m123c/m2,m234c/m2,gv2 magenta \ + 0100 06C0 0440 1830 \ + 1010 600C 4004 8003 \ + 0001 C006 4004 3018 \ + 1010 0C60 0440 0380 + m3c/m2,m123c/m2,m234c/m2,gv2 black \ + 0820 0820 0820 0FE0 \ + E00F 2008 2008 2008 \ + 2008 2008 2008 E00F \ + 0000 0FE0 0820 0820 + error_p,error_s,error_ps black \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 + magnet yellow \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 + fence magenta \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 + rotate cyan \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 + pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc X + +style versatec + pfet \ + 07c0 0f80 1f00 3e00 \ + 7c00 f800 f001 e003 \ + c007 800f 001f 003e \ + 00c7 00f8 01f0 03e0 + nfet \ + 1f00 0f80 07c0 03e0 \ + 01f0 00f8 007c 003e \ + 001f 800f c007 e003 \ + f001 f800 7c00 3e00 + gv1 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 + pwell \ + 2020 2020 2020 2020 \ + 2020 2020 2020 2020 \ + 0000 0000 0000 0000 \ + 0000 0000 0000 0000 + nwell \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 + poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet \ + 0808 0400 0202 0101 \ + 8080 4000 2020 1010 \ + 0808 0004 0202 0101 \ + 8080 0040 2020 1010 + m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 + pad,glass \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 + nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 + m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 + pdiff,apres,rpd,pdc/a,pdm12c/a,pfet \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 + psd,psc/a,psm12c/a \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 + ndiff,anres,rnd,ndc/a,ndm12c/a,nfet \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 + pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc X + +style gremlin + pfet 9 + nfet 10 + gv1 11 + pwell 15 + nwell 16 + poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet 19 + pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc 22 + pad,glass 23 + nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 24 + gv1 28 + pdiff,apres,rpd,pdc/a,pdm12c/a,pfet 29 + psd,psc/a,psm12c/a 30 + ndiff,anres,rnd,ndc/a,ndm12c/a,nfet 31 + pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc,gv1 X + +end + diff --git a/technology/scn4me_subm/tech/__init__.py b/technology/scn4me_subm/tech/__init__.py new file mode 100755 index 00000000..6b2d03b3 --- /dev/null +++ b/technology/scn4me_subm/tech/__init__.py @@ -0,0 +1,6 @@ +""" +Import tech specific modules. +""" + +from tech import * + diff --git a/technology/scn4me_subm/tech/tech.py b/technology/scn4me_subm/tech/tech.py new file mode 100755 index 00000000..565d73bc --- /dev/null +++ b/technology/scn4me_subm/tech/tech.py @@ -0,0 +1,295 @@ +import os + +""" +File containing the process technology parameters for SCMOS 3me, subm, 180nm. +""" + +info={} +info["name"]="scn3me_subm" +info["body_tie_down"] = 0 +info["has_pwell"] = True +info["has_nwell"] = True + +#GDS file info +GDS={} +# gds units +GDS["unit"]=(0.001,1e-6) +# default label zoom +GDS["zoom"] = 0.5 + + +################################################### +##GDS Layer Map +################################################### + +# create the GDS layer map +layer={} +layer["vtg"] = -1 +layer["vth"] = -1 +layer["contact"] = 47 +layer["pwell"] = 41 +layer["nwell"] = 42 +layer["active"] = 43 +layer["pimplant"] = 44 +layer["nimplant"] = 45 +layer["poly"] = 46 +layer["active_contact"] = 48 +layer["metal1"] = 49 +layer["via1"] = 50 +layer["metal2"] = 51 +layer["via2"] = 61 +layer["metal3"] = 62 +layer["via3"] = 30 +layer["metal4"] = 31 +layer["text"] = 63 +layer["boundary"] = 63 +layer["blockage"] = 83 + +################################################### +##END GDS Layer Map +################################################### + +################################################### +##DRC/LVS Rules Setup +################################################### +_lambda_ = 0.2 + +#technology parameter +parameter={} +parameter["min_tx_size"] = 4*_lambda_ +parameter["beta"] = 2 + +drclvs_home=os.environ.get("DRCLVS_HOME") + +drc={} +#grid size is 1/2 a lambda +drc["grid"]=0.5*_lambda_ +#DRC/LVS test set_up +drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul" +drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul" +drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" + + +# minwidth_tx with contact (no dog bone transistors) +drc["minwidth_tx"] = 4*_lambda_ +drc["minlength_channel"] = 2*_lambda_ + +# 1.3 Minimum spacing between wells of same type (if both are drawn) +drc["well_to_well"] = 6*_lambda_ +# 1.4 Minimum spacing between wells of different type (if both are drawn) +drc["pwell_to_nwell"] = 0 +# 1.1 Minimum width +drc["minwidth_well"] = 12*_lambda_ + +# 3.1 Minimum width +drc["minwidth_poly"] = 2*_lambda_ +# 3.2 Minimum spacing over active +drc["poly_to_poly"] = 3*_lambda_ +# 3.3 Minimum gate extension of active +drc["poly_extend_active"] = 2*_lambda_ +# 5.5.b Minimum spacing between poly contact and other poly (alternative rules) +drc["poly_to_polycontact"] = 4*_lambda_ +# ?? +drc["active_enclosure_gate"] = 0.0 +# 3.5 Minimum field poly to active +drc["poly_to_active"] = _lambda_ +# 3.2.a Minimum spacing over field poly +drc["poly_to_field_poly"] = 3*_lambda_ +# Not a rule +drc["minarea_poly"] = 0.0 + +# ?? +drc["active_to_body_active"] = 4*_lambda_ # Fix me +# 2.1 Minimum width +drc["minwidth_active"] = 3*_lambda_ +# 2.2 Minimum spacing +drc["active_to_active"] = 3*_lambda_ +# 2.3 Source/drain active to well edge +drc["well_enclosure_active"] = 6*_lambda_ +# Reserved for asymmetric enclosures +drc["well_extend_active"] = 6*_lambda_ +# Not a rule +drc["minarea_active"] = 0.0 + +# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width +drc["implant_to_channel"] = 3*_lambda_ +# 4.2 Minimum select overlap of active +drc["implant_enclosure_active"] = 2*_lambda_ +# 4.3 Minimum select overlap of contact +drc["implant_enclosure_contact"] = _lambda_ +# Not a rule +drc["implant_to_contact"] = 0 +# Not a rule +drc["implant_to_implant"] = 0 +# Not a rule +drc["minwidth_implant"] = 0 + +# 6.1 Exact contact size +drc["minwidth_contact"] = 2*_lambda_ +# 5.3 Minimum contact spacing +drc["contact_to_contact"] = 3*_lambda_ +# 6.2.b Minimum active overlap +drc["active_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosure +drc["active_extend_contact"] = _lambda_ +# 5.2.b Minimum poly overlap +drc["poly_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosures +drc["poly_extend_contact"] = _lambda_ +# Reserved for other technologies +drc["contact_to_gate"] = 2*_lambda_ +# 5.4 Minimum spacing to gate of transistor +drc["contact_to_poly"] = 2*_lambda_ + +# 7.1 Minimum width +drc["minwidth_metal1"] = 3*_lambda_ +# 7.2 Minimum spacing +drc["metal1_to_metal1"] = 3*_lambda_ +# 7.3 Minimum overlap of any contact +drc["metal1_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosure +drc["metal1_extend_contact"] = _lambda_ +# 8.3 Minimum overlap by metal1 +drc["metal1_enclosure_via1"] = _lambda_ +# Reserve for asymmetric enclosures +drc["metal1_extend_via1"] = _lambda_ +# Not a rule +drc["minarea_metal1"] = 0 + +# 8.1 Exact size +drc["minwidth_via1"] = 2*_lambda_ +# 8.2 Minimum via1 spacing +drc["via1_to_via1"] = 2*_lambda_ + +# 9.1 Minimum width +drc["minwidth_metal2"] = 3*_lambda_ +# 9.2 Minimum spacing +drc["metal2_to_metal2"] = 3*_lambda_ +# 9.3 Minimum overlap of via1 +drc["metal2_extend_via1"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal2_enclosure_via1"] = _lambda_ +# 14.3 Minimum overlap by metal2 +drc["metal2_extend_via2"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal2_enclosure_via2"] = _lambda_ +# Not a rule +drc["minarea_metal2"] = 0 + +# 14.2 Exact size +drc["minwidth_via2"] = 2*_lambda_ +# 14.2 Minimum spacing +drc["via2_to_via2"] = 3*_lambda_ + +# 15.1 Minimum width +drc["minwidth_metal3"] = 3*_lambda_ +# 15.2 Minimum spacing to metal3 +drc["metal3_to_metal3"] = 3*_lamda_ +# 15.3 Minimum overlap of via 2 +drc["metal3_extend_via2"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal3_enclosure_via2"] = 2*_lambda_ +# Reserved for asymmetric enclosures +drc["metal2_enclosure_via1"] = _lambda_ +# 21.3 Minimum overlap by metal3 +drc["metal3_extend_via2"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal3_enclosure_via2"] = _lambda_ +# Not a rule +drc["minarea_metal3"] = 0 + +# 21.1 Exact size +drc["minwidth_via3"] = 2*_lambda_ +# 21.2 Minimum spacing +drc["via3_to_via3"] = 3*_lambda_ + +# 22.1 Minimum width +drc["minwidth_metal3"] = 6*_lambda_ +# 22.2 Minimum spacing to metal3 +drc["metal3_to_metal3"] = 6*_lamda_ +# 22.3 Minimum overlap of via 2 +drc["metal3_extend_via2"] = 2_lambda_ +# Reserved for asymmetric enclosures +drc["metal3_enclosure_via2"] = 2*_lambda_ +# Not a rule +drc["minarea_metal3"] = 0 + +################################################### +##END DRC/LVS Rules +################################################### + +################################################### +##Spice Simulation Parameters +################################################### + +# spice model info +spice={} +spice["nmos"]="n" +spice["pmos"]="p" +# This is a map of corners to model files +SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR") +# FIXME: Uncomment when we have the new spice models +#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] } +spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"], + "FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], + "FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], + "SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], + "SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"] } + + +#spice stimulus related variables +spice["feasible_period"] = 5 # estimated feasible period in ns +spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts] +spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts] +spice["rise_time"] = 0.05 # rise time in [Nano-seconds] +spice["fall_time"] = 0.05 # fall time in [Nano-seconds] +spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius) +spice["nom_temperature"] = 25 # Nominal temperature (celcius) + +#sram signal names +#FIXME: We don't use these everywhere... +spice["vdd_name"] = "vdd" +spice["gnd_name"] = "gnd" +spice["control_signals"] = ["CSB", "WEB"] +spice["data_name"] = "DATA" +spice["addr_name"] = "ADDR" +spice["minwidth_tx"] = drc["minwidth_tx"] +spice["channel"] = drc["minlength_channel"] +spice["clk"] = "clk" + +# analytical delay parameters +# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45. +spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square +spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2 +spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms +spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff +spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff +spice["msflop_setup"] = 9 # DFF setup time in ps +spice["msflop_hold"] = 1 # DFF hold time in ps +spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps +spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load +spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] +spice["dff_setup"] = 9 # DFF setup time in ps +spice["dff_hold"] = 1 # DFF hold time in ps +spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps +spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load +spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] + +# analytical power parameters, many values are temporary +spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW +spice["inv_leakage"] = 1 # Leakage power of inverter in nW +spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW +spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW +spice["msflop_leakage"] = 1 # Leakage power of flop in nW +spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF + +spice["default_event_rate"] = 100 # Default event activity of every gate. MHz +spice["flop_transition_prob"] = .5 # Transition probability of inverter. +spice["inv_transition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. +################################################### +##END Spice Simulation Parameters +################################################### diff --git a/technology/scn4me_subm/tf/LICENSE b/technology/scn4me_subm/tf/LICENSE new file mode 100644 index 00000000..8d22c4be --- /dev/null +++ b/technology/scn4me_subm/tf/LICENSE @@ -0,0 +1,4 @@ +The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004, +2006. Users are free to use or modify the NCSU CDK as appropriate as long +as this notice appears in the modified package. The NCSU CDK is +provided with NO WARRANTY. diff --git a/technology/scn4me_subm/tf/README b/technology/scn4me_subm/tf/README new file mode 100644 index 00000000..d2531fe1 --- /dev/null +++ b/technology/scn4me_subm/tf/README @@ -0,0 +1,21 @@ +;; NCSU CDK v. 1.6.0.beta +;; Last Modified: 2007-07-12 + +The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004, +2006, 2007. Users are free to use or modify the NCSU CDK as appropriate as long +as this notice appears in the modified package. The NCSU CDK is +provided with NO WARRANTY. + +As of version 1.5.1, all documentation for the NCSU CDK is provided +by the NCSU EDA Wiki which can be found at: + + http://www.eda.ncsu.edu/ + +This beta release of the kit is to be used in migrating to Cadence Virtuoso 6.1 +for OpenAccess. Details of the conversion of the CDK from the CDB version can +be found in the file cdb2oa/OA_Conversion.txt. + +This kit is not yet fully supported. Please post problems and solutions at +http://www.chiptalk.org -> Forums -> NCSU CDK -> NCSU CDK 1.6.0.beta for Virtuoso 6.1 + +Modified 2018 by MRG to contain SCN4ME Via3/Metal4 layers. \ No newline at end of file diff --git a/technology/scn4me_subm/tf/display.drf b/technology/scn4me_subm/tf/display.drf new file mode 100644 index 00000000..aeeefe2c --- /dev/null +++ b/technology/scn4me_subm/tf/display.drf @@ -0,0 +1,717 @@ +drDefineDisplay( +;( DisplayName ) + ( display ) +) +drDefineColor( +;( DisplayName ColorsName Red Green Blue ) + ( display white 255 255 255 ) + ( display yellow 255 255 0 ) + ( display silver 217 230 255 ) + ( display cream 255 255 204 ) + ( display pink 255 191 242 ) + ( display magenta 255 0 255 ) + ( display lime 0 255 0 ) + ( display tan 255 230 191 ) + ( display cyan 0 255 255 ) + ( display cadetBlue 57 191 255 ) + ( display orange 255 128 0 ) + ( display red 255 51 51 ) + ( display purple 153 0 230 ) + ( display green 0 204 102 ) + ( display brown 191 64 38 ) + ( display blue 51 77 255 ) + ( display slate 140 140 166 ) + ( display gold 217 204 0 ) + ( display maroon 230 31 13 ) + ( display violet 94 0 230 ) + ( display forest 38 140 107 ) + ( display chocolate 128 38 38 ) + ( display navy 51 51 153 ) + ( display black 0 0 0 ) + ( display gray 204 204 217 ) + ( display winColor1 166 166 166 ) + ( display winColor2 115 115 115 ) + ( display winColor3 189 204 204 ) + ( display winColor4 204 204 204 ) + ( display winColor5 199 199 199 ) + ( display blinkRed 255 0 0 t ) + ( display blinkYellow 255 255 0 t ) + ( display blinkWhite 255 255 255 t ) + ( display winBack 224 224 224 ) + ( display winFore 128 0 0 ) + ( display winText 51 51 51 ) +) +drDefineStipple( +;( DisplayName StippleName Bitmap ) + ( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) + ( display vLine ( ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) ) + ( display cross ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) ) + ( display grid ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) + ( display slash ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) + ( display backSlash ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) ) + ( display hZigZag ( ( 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 ) + 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stipple1 lineStyle0 silver silver outlineStipple) + ( display CapWellNet brick solid slate slate outlineStipple) + ( display Unrouted7 stipple0 lineStyle1 purple purple solid ) + ( display CannotoccupyBnd blank solid red red outline ) + ( display winTopShadow solid solid white white solid ) + ( display designFlow4 stipple1 lineStyle0 black black outlineStipple) + ( display softFence stipple0 solid yellow yellow solid ) + ( display ResistorNet dots4 solid cyan cyan outlineStipple) + ( display winError solid solid winColor5 winColor5 solid ) + ( display changedLayerTl1 stipple0 solid yellow yellow solid ) + ( display prBoundaryLbl stipple0 solid purple purple solid ) + ( display ActXNet x solid yellow yellow outlineStipple) + ( display Pbase stipple10 lineStyle0 yellow yellow outlineStipple) + ( display Active dots2 lineStyle0 yellow yellow outlineStipple) + ( display changedLayerTl0 stipple0 solid red red solid ) + ( display spike stipple0 solid purple purple solid ) + ( display Metal3 grid solid navy violet outlineStipple) + ( display Metal4 grid solid tan tan outlineStipple) + ( display text blank solid white white outline ) + ( display Poly1Pin stipple0 lineStyle0 red red solid ) + ( display Row blank solid cyan cyan outline ) + ( display Pwell stipple9 lineStyle0 slate slate outlineStipple) + ( display Metal2 stipple5 lineStyle0 magenta magenta outlineStipple) + ( display wire solid lineStyle0 cyan cyan solid ) + ( display ActX solid solid yellow yellow solid ) + ( display Metal1 stipple6 lineStyle0 cadetBlue cadetBlue outlineStipple) + ( display Cannotoccupy blank solid red red outline ) + ( display GroupLbl stipple0 solid green green solid ) + ( display axis stipple0 solid slate slate solid ) + ( display SiBlockNet x dashed tan tan outlineStipple) + ( display edgeLayer stipple0 solid gray gray solid ) + ( display annotate2 stipple0 solid lime lime solid ) + ( display Metal1Pin stipple0 lineStyle0 blue blue solid ) + ( display Diode stipple7 lineStyle0 cream cream outlineStipple) + ( display Glass X lineStyle0 white white X ) + ( display ViaXNet x solid magenta magenta outlineStipple) + ( display annotate3 stipple0 solid cyan cyan solid ) + ( display Poly2 dots1 lineStyle0 orange orange outlineStipple) + ( display deviceAnt stipple0 solid yellow yellow solid ) + ( display winBottomShadow solid solid winColor1 winColor1 solid ) + ( display PselectNet dots4 solid brown brown outlineStipple) + ( display comment stipple0 lineStyle0 winBack winBack outline ) + ( display Poly1 dots lineStyle0 red red outlineStipple) + ( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid ) + ( display stretch stipple0 solid yellow yellow solid ) + ( display XP blank lineStyle0 winBack gold outline ) + ( display annotate1 stipple0 solid pink pink solid ) + ( display Group stipple2 solid green green outlineStipple) + ( display deviceLbl stipple0 solid green green solid ) + ( display annotate6 stipple0 solid silver silver solid ) + ( display GlassNet blank solid yellow yellow outline ) + ( display Canplace blank solid cyan cyan outline ) + ( display annotate7 stipple0 solid red red solid ) + ( display Via2 solid solid navy navy solid ) + ( display Metal2Pin stipple0 lineStyle0 magenta magenta solid ) + ( display annotate4 stipple0 solid yellow yellow solid ) + ( display device1 stipple1 lineStyle0 green green outlineStipple) + ( display "90" blank solid white white outline ) + ( display markerWarn x solid yellow yellow outlineStipple) + ( display text2 stipple1 lineStyle0 white white outlineStipple) + ( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple) + ( display designFlow stipple1 lineStyle0 green green outlineStipple) + ( display hilite1 stipple0 solid silver silver solid ) + ( display device blank solid green green outline ) + ( display prBoundary stipple0 solid purple purple solid ) + ( display annotate5 stipple0 solid white white solid ) + ( display text1 stipple0 dashed white white solid ) + ( display Via solid solid magenta magenta solid ) + ( display Capacitor stipple7 lineStyle0 tan tan outlineStipple) + ( display markerErr x solid white white outlineStipple) + ( display unknown stipple0 solid yellow yellow solid ) + ( display annotate stipple0 solid orange orange solid ) + ( display P1ConNet x solid red red outlineStipple) + ( display hilite3 stipple0 solid cyan cyan solid ) + ( display winActiveBanner solid solid winColor3 winColor3 solid ) + ( display pinLbl stipple0 solid red red solid ) + ( display device2 stipple0 lineStyle1 green green solid ) + ( display grid stipple0 solid slate slate solid ) + ( display winBackground solid solid winBack winBack solid ) + ( display Metal1Net dots4 lineStyle0 blue blue outlineStipple) + ( display hilite2 stipple0 solid tan tan solid ) + ( display annotate8 stipple0 solid tan tan solid ) + ( display hilite5 stipple0 solid lime lime solid ) + ( display annotate9 stipple0 solid green green solid ) + ( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple) + ( display Metal3Pin stipple0 solid navy navy solid ) + ( display Metal4Pin stipple0 solid tan tan solid ) + ( display hilite4 stipple0 solid gray gray solid ) + ( display y0 stipple0 solid gray gray solid ) + ( display supply stipple0 solid lime lime solid ) + ( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple) + ( display hilite7 stipple0 solid cream cream solid ) + ( display y1 stipple0 solid brown brown solid ) + ( display defaultPacket x solid chocolate winColor2 outlineStipple) + ( display Via2Net cross solid navy navy outlineStipple) + ( display NselectNet dots4 solid green green outlineStipple) + ( display Unrouted8 stipple0 lineStyle1 gold gold solid ) + ( display hilite6 stipple0 solid orange orange solid ) + ( display y2 stipple0 solid red red solid ) + ( display winBorder solid solid winColor2 winColor2 solid ) + ( display Nwell dats5 thickLine slate slate outlineStipple) + ( display Unrouted9 stipple0 lineStyle1 silver silver solid ) + ( display hilite9 stipple0 solid pink pink solid ) + ( display SiBlock blank dashed tan tan outline ) + ( display y3 stipple0 solid orange orange solid ) + ( display prBoundaryBnd stipple0 solid cyan cyan solid ) + ( display winForeground solid solid winFore winFore solid ) + ( display hilite8 stipple0 solid magenta magenta solid ) + ( display y4 stipple0 solid yellow yellow solid ) + ( display Pselect dots1 solid brown brown outlineStipple) + ( display winInactiveBanner solid solid winColor4 winColor4 solid ) + ( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple) + ( display winButton solid solid winFore winFore solid ) + ( display y5 stipple0 solid green green solid ) + ( display hiz stipple0 solid orange orange solid ) + ( display drive stipple0 solid blue blue solid ) + ( display wireFlt stipple0 dashed red red solid ) + ( display instanceLbl stipple0 solid gold gold solid ) + ( display P2ConNet x lineStyle0 orange orange outlineStipple) + ( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple) + ( display y6 stipple0 solid blue blue solid ) + ( display PwellNet dots4 lineStyle0 slate slate outlineStipple) + ( display P1Con solid solid red red solid ) + ( display CapWell dagger solid slate slate outlineStipple) + ( display y7 stipple0 solid purple purple solid ) + ( display ViaX solid solid magenta magenta solid ) + ( display HR x solid chocolate winColor2 outlineStipple) + ( display HRnet x solid chocolate winColor2 outlineStipple) +) diff --git a/technology/scn4me_subm/tf/glade_scn4me_subm.py b/technology/scn4me_subm/tf/glade_scn4me_subm.py new file mode 100644 index 00000000..d2f9aa7e --- /dev/null +++ b/technology/scn4me_subm/tf/glade_scn4me_subm.py @@ -0,0 +1,7 @@ +import os +CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf" +ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map") + + + + diff --git a/technology/scn4me_subm/tf/layers.map b/technology/scn4me_subm/tf/layers.map new file mode 100644 index 00000000..80b659d9 --- /dev/null +++ b/technology/scn4me_subm/tf/layers.map @@ -0,0 +1,18 @@ +Pwell drawing 41 0 +Nwell drawing 42 0 +Active drawing 43 0 +Poly1 drawing 46 0 +Pselect drawing 45 0 +Nselect drawing 44 0 +contact drawing 25 0 +P1Con drawing 47 0 +ActX drawing 48 0 +Metal1 drawing 49 0 +Via drawing 50 0 +Metal2 drawing 51 0 +Via2 drawing 61 0 +Metal3 drawing 62 0 +Via3 drawing 30 0 +Metal4 drawing 31 0 +Glass drawing 52 0 +comment drawing 63 0 diff --git a/technology/scn4me_subm/tf/mosis.tf b/technology/scn4me_subm/tf/mosis.tf new file mode 100644 index 00000000..e48d76a0 --- /dev/null +++ b/technology/scn4me_subm/tf/mosis.tf @@ -0,0 +1,850 @@ +; Generated on Sep 28 16:05:23 1998 +; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $ +; +; Matt Clapp fixed: October 10, 2002 +; added via devices, deleted useless app-specific crap, +; added lxExtractRules so undo in layout editor doesn't +; complain. + + +;******************************** +; LAYER DEFINITION +;******************************** + +layerDefinitions( + techLayers( + ;( LayerName Layer# Abbreviation ) + ;( --------- ------ ------------ ) + ;User-Defined Layers: + ( P2Con 3 P2Con ) + ( Poly2 7 Poly2 ) + ( Pbase 10 Pbase ) + ( Resistor 16 Resisto ) + ( Capacitor 17 Capacit ) + ( Diode 18 Diode ) + ( SiBlock 29 SiBlock ) + ( HR 34 HR ) + ( Pwell 41 Pwell ) + ( Nwell 42 Nwell ) + ( Active 43 Active ) + ( Pselect 44 Pselect ) + ( Nselect 45 Nselect ) + ( Poly1 46 Poly1 ) + ( P1Con 47 P1Con ) + ( ActX 48 ActX ) + ( Metal1 49 Metal1 ) + ( Via 50 Via ) + ( Metal2 51 Metal2 ) + ( Glass 52 Glass ) + ( CapWell 59 CapWell ) + ( XP 60 XP ) + ( Via2 61 Via2 ) + ( Metal3 62 Metal3 ) + ( Via3 30 Via3 ) + ( Metal4 31 Metal4 ) + ( A1 80 A1 ) + ( A2 81 A2 ) + ( comment 117 comment ) + ;System-Reserved Layers: + ( Unrouted 200 Unroute ) + ( Row 201 Row ) + ( Group 202 Group ) + ( Cannotoccupy 203 Cannoto ) + ( Canplace 204 Canplac ) + ( hardFence 205 hardFen ) + ( softFence 206 softFen ) + ( y0 207 y0 ) + ( y1 208 y1 ) + ( y2 209 y2 ) + ( y3 210 y3 ) + ( y4 211 y4 ) + ( y5 212 y5 ) + ( y6 213 y6 ) + ( y7 214 y7 ) + ( y8 215 y8 ) + ( y9 216 y9 ) + ( designFlow 217 designF ) + ( stretch 218 stretch ) + ( edgeLayer 219 edgeLay ) + ( changedLayer 220 changed ) + ( unset 221 unset ) + ( unknown 222 unknown ) + ( spike 223 spike ) + ( hiz 224 hiz ) + ( resist 225 resist ) + ( drive 226 drive ) + ( supply 227 supply ) + ( wire 228 wire ) + ( pin 229 pin ) + ( text 230 text ) + ( device 231 device ) + ( border 232 border ) + ( snap 233 snap ) + ( align 234 align ) + ( prBoundary 235 prBound ) + ( instance 236 instanc ) + ( annotate 237 annotat ) + ( marker 238 marker ) + ( select 239 select ) + ( grid 251 grid ) + ( axis 252 axis ) + ( hilite 253 hilite ) + ( background 254 backgro ) + ) ;techLayers + + techPurposes( + ;( PurposeName Purpose# Abbreviation ) + ;( ----------- -------- ------------ ) + ;User-Defined Purposes: + ;System-Reserved Purposes: + ( warning 234 wng ) + ( tool1 235 tl1 ) + ( tool0 236 tl0 ) + ( label 237 lbl ) + ( flight 238 flt ) + ( error 239 err ) + ( annotate 240 ant ) + ( drawing1 241 dr1 ) + ( drawing2 242 dr2 ) + ( drawing3 243 dr3 ) + ( drawing4 244 dr4 ) + ( drawing5 245 dr5 ) + ( drawing6 246 dr6 ) + ( drawing7 247 dr7 ) + ( drawing8 248 dr8 ) + ( drawing9 249 dr9 ) + ( boundary 250 bnd ) + ( pin 251 pin ) + ( drawing 252 drw ) + ( net 253 net ) + ( cell 254 cel ) + ( all 255 all ) + ) ;techPurposes + + techLayerPurposePriorities( + ;layers are ordered from lowest to highest priority + ; (higher priority is drawn on top of lower priority) + ;( LayerName Purpose ) + ;( --------- ------- ) + ( background drawing ) + ( grid drawing ) + ( grid drawing1 ) + ( Nwell drawing ) + ( Pwell drawing ) + ( CapWell drawing ) + ( Pselect drawing ) + ( Nselect drawing ) + ( Active drawing ) + ( ActX drawing ) + ( SiBlock drawing ) + ( HR drawing ) + ( Poly1 drawing ) + ( P1Con drawing ) + ( Poly2 drawing ) + ( P2Con drawing ) + ( Metal1 drawing ) + ( Via drawing ) + ( Metal2 drawing ) + ( Via2 drawing ) + ( Metal3 drawing ) + ( annotate drawing ) + ( annotate drawing1 ) + ( annotate drawing2 ) + ( annotate drawing3 ) + ( annotate drawing4 ) + ( annotate drawing5 ) + ( annotate drawing6 ) + ( annotate drawing7 ) + ( annotate drawing8 ) + ( annotate drawing9 ) + ( Poly1 pin ) + ( Metal1 pin ) + ( Metal2 pin ) + ( Metal3 pin ) + ( Glass drawing ) + ( XP drawing ) + ( prBoundary drawing ) + ( prBoundary boundary ) + ( instance drawing ) + ( prBoundary label ) + ( instance label ) + ( Row drawing ) + ( Nwell net ) + ( align drawing ) + ( Pwell net ) + ( CapWell net ) + ( hardFence drawing ) + ( Active net ) + ( softFence drawing ) + ( Row label ) + ( Group drawing ) + ( Group label ) + ( Cannotoccupy drawing ) + ( Cannotoccupy boundary ) + ( Canplace drawing ) + ( ActX net ) + ( A2 drawing ) + ( A1 drawing ) + ( comment drawing ) + ( border drawing ) + ( Pselect net ) + ( Nselect net ) + ( SiBlock net ) + ( HR net ) + ( wire drawing ) + ( Poly1 net ) + ( wire label ) + ( P1Con net ) + ( wire flight ) + ( Metal1 net ) + ( device annotate ) + ( Metal2 net ) + ( device label ) + ( Via net ) + ( Metal3 net ) + ( Via2 net ) + ( pin label ) + ( text drawing ) + ( pin drawing ) + ( text drawing1 ) + ( pin annotate ) + ( device drawing ) + ( axis drawing ) + ( edgeLayer drawing ) + ( edgeLayer pin ) + ( snap drawing ) + ( stretch drawing ) + ( y0 drawing ) + ( y1 drawing ) + ( y2 drawing ) + ( y3 drawing ) + ( y4 drawing ) + ( y5 drawing ) + ( y6 drawing ) + ( y7 drawing ) + ( y8 drawing ) + ( y9 drawing ) + ( hilite drawing ) + ( hilite drawing1 ) + ( hilite drawing2 ) + ( hilite drawing3 ) + ( hilite drawing4 ) + ( hilite drawing5 ) + ( hilite drawing6 ) + ( hilite drawing7 ) + ( hilite drawing8 ) + ( hilite drawing9 ) + ( select drawing ) + ( drive drawing ) + ( hiz drawing ) + ( resist drawing ) + ( spike drawing ) + ( supply drawing ) + ( unknown drawing ) + ( unset drawing ) + ( designFlow drawing ) + ( designFlow drawing1 ) + ( designFlow drawing2 ) + ( designFlow drawing3 ) + ( designFlow drawing4 ) + ( designFlow drawing5 ) + ( designFlow drawing6 ) + ( designFlow drawing7 ) + ( designFlow drawing8 ) + ( designFlow drawing9 ) + ( changedLayer tool0 ) + ( changedLayer tool1 ) + ( marker warning ) + ( marker error ) + ( device drawing1 ) + ( Pbase drawing ) + ( Pbase net ) + ( Resistor net ) + ( Resistor drawing ) + ( Capacitor net ) + ( Capacitor drawing ) + ( Diode net ) + ( Diode drawing ) + ( Poly2 net ) + ( P2Con net ) + ( device drawing2 ) + ( Unrouted drawing ) + ( text drawing2 ) + ( Unrouted drawing1 ) + ( Unrouted drawing2 ) + ( Unrouted drawing3 ) + ( Unrouted drawing4 ) + ( Unrouted drawing5 ) + ( Unrouted drawing6 ) + ( Unrouted drawing7 ) + ( Unrouted drawing8 ) + ( Unrouted drawing9 ) + ) ;techLayerPurposePriorities + + techDisplays( + ;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid ) + ;( --------- ------- ------ --- --- --------- ------- ----- ) + ( background drawing background t nil nil nil nil ) + ( grid drawing grid t nil nil nil nil ) + ( grid drawing1 grid1 t nil nil nil nil ) + ( Nwell drawing Nwell t t t t t ) + ( Pwell drawing Pwell t t t t nil ) + ( Active drawing Active t t t t t ) + ( ActX drawing ActX t t t t t ) + ( Pselect drawing Pselect t t t t t ) + ( Nselect drawing Nselect t t t t t ) + ( SiBlock drawing SiBlock t t t t t ) + ( HR drawing HR t t t t t ) + ( CapWell drawing CapWell t t t t t ) + ( Poly1 drawing Poly1 t t t t t ) + ( P1Con drawing P1Con t t t t t ) + ( Metal1 drawing Metal1 t t t t t ) + ( Via drawing Via t t t t t ) + ( Metal2 drawing Metal2 t t t t t ) + ( annotate drawing annotate t t nil t nil ) + ( annotate drawing1 annotate1 t t nil t nil ) + ( annotate drawing2 annotate2 t t nil t nil ) + ( annotate drawing3 annotate3 t t nil t nil ) + ( annotate drawing4 annotate4 t t nil t nil ) + ( annotate drawing5 annotate5 t t nil t nil ) + ( annotate drawing6 annotate6 t t nil t nil ) + ( annotate drawing7 annotate7 t t nil t nil ) + ( annotate drawing8 annotate8 t t nil t nil ) + ( annotate drawing9 annotate9 t t nil t nil ) + ( Via2 drawing Via2 t t t t t ) + ( Metal3 drawing Metal3 t t t t t ) + ( Glass drawing Glass t t t nil t ) + ( XP drawing XP t t t nil t ) + ( Metal1 pin Metal1Pin t t t nil t ) + ( Metal2 pin Metal2Pin t t t nil t ) + ( Metal3 pin Metal3Pin t t t nil t ) + ( Poly1 pin Poly1Pin t t t nil t ) + ( prBoundary drawing prBoundary t t nil t nil ) + ( prBoundary boundary prBoundaryBnd t t nil t nil ) + ( instance drawing instance t t nil t t ) + ( prBoundary label prBoundaryLbl t t t t nil ) + ( instance label instanceLbl t t t t nil ) + ( Row drawing Row t t t t nil ) + ( Nwell net NwellNet t t t nil nil ) + ( align drawing align t t nil t nil ) + ( Pwell net PwellNet t t t nil nil ) + ( CapWell net CapWellNet t t t nil nil ) + ( SiBlock net SiBlockNet t t t nil nil ) + ( HR net HRnet t t t nil nil ) + ( hardFence drawing hardFence t t t t nil ) + ( Active net ActiveNet t t t nil nil ) + ( softFence drawing softFence t t t t nil ) + ( Row label RowLbl t t t t nil ) + ( Group drawing Group t t t t nil ) + ( Group label GroupLbl t t t t nil ) + ( Cannotoccupy drawing Cannotoccupy t t t t nil ) + ( Cannotoccupy boundary CannotoccupyBnd t t t t nil ) + ( Canplace drawing Canplace t t t t nil ) + ( ActX net ActXNet t t t nil nil ) + ( A2 drawing A2 t t t t nil ) + ( A1 drawing A1 t t t t nil ) + ( comment drawing comment t t t t nil ) + ( border drawing border t t t t nil ) + ( Pselect net PselectNet t t t nil nil ) + ( Nselect net NselectNet t t t nil nil ) + ( wire drawing wire t t t t nil ) + ( Poly1 net Poly1Net t t t nil nil ) + ( wire label wireLbl t t t t nil ) + ( P1Con net P1ConNet t t t nil nil ) + ( wire flight wireFlt t t t t nil ) + ( Metal1 net Metal1Net t t t nil nil ) + ( device annotate deviceAnt t t t t nil ) + ( Metal2 net Metal2Net t t t nil nil ) + ( Metal3 net Metal3Net t t t nil nil ) + ( device label deviceLbl t t t t nil ) + ( Via net ViaNet t t t nil nil ) + ( Via2 net Via2Net t t t nil nil ) + ( pin label pinLbl t t t t nil ) + ( text drawing text t t t t t ) + ( pin drawing pin t t t t nil ) + ( text drawing1 text1 t t t t nil ) + ( pin annotate pinAnt t t t t nil ) + ( device drawing device t t t t nil ) + ( axis drawing axis t t t t nil ) + ( edgeLayer drawing edgeLayer t t nil t nil ) + ( edgeLayer pin edgeLayerPin t t nil t nil ) + ( snap drawing snap t t nil t nil ) + ( stretch drawing stretch t t nil t nil ) + ( y0 drawing y0 t t nil t nil ) + ( y1 drawing y1 t t nil t nil ) + ( y2 drawing y2 t t nil t nil ) + ( y3 drawing y3 t t nil t nil ) + ( y4 drawing y4 t t nil t nil ) + ( y5 drawing y5 t t nil t nil ) + ( y6 drawing y6 t t nil t nil ) + ( y7 drawing y7 t t nil t nil ) + ( y8 drawing y8 t t nil t nil ) + ( y9 drawing y9 t t nil t nil ) + ( hilite drawing hilite t t nil t nil ) + ( hilite drawing1 hilite1 t t t t nil ) + ( hilite drawing2 hilite2 t t nil t nil ) + ( hilite drawing3 hilite3 t t t t nil ) + ( hilite drawing4 hilite4 t t t t nil ) + ( hilite drawing5 hilite5 t t t t nil ) + ( hilite drawing6 hilite6 t t t t nil ) + ( hilite drawing7 hilite7 t t t t nil ) + ( hilite drawing8 hilite8 t t t t nil ) + ( hilite drawing9 hilite9 t t t t nil ) + ( select drawing select t t nil t nil ) + ( drive drawing drive t t t t nil ) + ( hiz drawing hiz t t t t nil ) + ( resist drawing resist t t t t nil ) + ( spike drawing spike t t t t nil ) + ( supply drawing supply t t t t nil ) + ( unknown drawing unknown t t t t nil ) + ( unset drawing unset t t t t nil ) + ( designFlow drawing designFlow t t t nil nil ) + ( designFlow drawing1 designFlow1 t t t nil nil ) + ( designFlow drawing2 designFlow2 t t t nil nil ) + ( designFlow drawing3 designFlow3 t t t nil nil ) + ( designFlow drawing4 designFlow4 t t t nil nil ) + ( designFlow drawing5 designFlow5 t t t nil nil ) + ( designFlow drawing6 designFlow6 t t t nil nil ) + ( designFlow drawing7 designFlow7 t t t nil nil ) + ( designFlow drawing8 designFlow8 t t t nil nil ) + ( designFlow drawing9 designFlow9 t t t nil nil ) + ( changedLayer tool0 changedLayerTl0 nil nil nil nil nil ) + ( changedLayer tool1 changedLayerTl1 nil nil t nil nil ) + ( marker warning markerWarn t t t t nil ) + ( marker error markerErr t t t t nil ) + ( device drawing1 device1 t t t t nil ) + ( Poly2 net Poly2Net t t t nil nil ) + ( Poly2 drawing Poly2 t t t t t ) + ( P2Con net P2ConNet t t t nil nil ) + ( P2Con drawing P2Con t t t t t ) + ( Pbase net PbaseNet t t t nil nil ) + ( Pbase drawing Pbase t t t t t ) + ( Resistor net ResistorNet t t t nil nil ) + ( Resistor drawing Resistor t t t t t ) + ( Capacitor net CapacitorNet t t t nil nil ) + ( Capacitor drawing Capacitor t t t t t ) + ( Diode net DiodeNet t t t nil nil ) + ( Diode drawing Diode t t t t t ) + ( device drawing2 device2 t t t t nil ) + ( Unrouted drawing Unrouted t t t t nil ) + ( text drawing2 text2 t t t t nil ) + ( Unrouted drawing1 Unrouted1 t t t t nil ) + ( Unrouted drawing2 Unrouted2 t t t t nil ) + ( Unrouted drawing3 Unrouted3 t t t t nil ) + ( Unrouted drawing4 Unrouted4 t t t t nil ) + ( Unrouted drawing5 Unrouted5 t t t t nil ) + ( Unrouted drawing6 Unrouted6 t t t t nil ) + ( Unrouted drawing7 Unrouted7 t t t t nil ) + ( Unrouted drawing8 Unrouted8 t t t t nil ) + ( Unrouted drawing9 Unrouted9 t t t t nil ) + ) ;techDisplays + +; I don't think the following is necessary (or used!) +techLayerProperties( +;( PropName Layer1 [ Layer2 ] PropValue ) + ( contactLimit P2Con 10000 ) + ( eqPinLimit P2Con 10000 ) + ( horizontalJogLength P2Con 2147483648.000000 ) + ( routingGrid P2Con 1.000000 ) + ( verticalJogLength P2Con 2147483648.000000 ) + ( routingGrid Poly2 1.000000 ) + ( contactLimit Active 10000 ) + ( eqPinLimit Active 10000 ) + ( horizontalJogLength Active 2147483648.000000 ) + ( routingGrid Active 1.000000 ) + ( verticalJogLength Active 2147483648.000000 ) + ( routingGrid Poly1 1.000000 ) + ( contactLimit P1Con 10000 ) + ( eqPinLimit P1Con 10000 ) + ( horizontalJogLength P1Con 2147483648.000000 ) + ( routingGrid P1Con 1.000000 ) + ( verticalJogLength P1Con 2147483648.000000 ) + ( contactLimit ActX 10000 ) + ( eqPinLimit ActX 10000 ) + ( horizontalJogLength ActX 2147483648.000000 ) + ( routingGrid ActX 1.000000 ) + ( verticalJogLength ActX 2147483648.000000 ) + ( routingGrid Metal1 1.000000 ) + ( contactLimit Via 10000 ) + ( eqPinLimit Via 10000 ) + ( horizontalJogLength Via 2147483648.000000 ) + ( routingGrid Via 1.000000 ) + ( verticalJogLength Via 2147483648.000000 ) + ( routingGrid Metal2 1.000000 ) +) + +) ;layerDefinitions + + +;******************************** +; DEVICE RULES +;******************************** + +devices( + tcCreateCDSDeviceClass() + + symContactDevice( + ;( deviceName viaLayer viaPurpose + ( VIA Via drawing + + ; layer1 purpose1 [implant1] + Metal1 drawing + + ; layer2 purpose2 [implant2] + Metal2 drawing + + ; width length [( row column xPitch yPitch xBias yBias )] + ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) + 2 2 + + ; encLayer1 encLayer2 legalRegion ) + 1 1 _NA_) + ) ;symContactDevice + + symContactDevice( + ;( deviceName viaLayer viaPurpose + ( VIA2 Via2 drawing + + ; layer1 purpose1 [implant1] + Metal2 drawing + + ; layer2 purpose2 [implant2] + Metal3 drawing + + ; width length [( row column xPitch yPitch xBias yBias )] + ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) + 2 2 + + ; encLayer1 encLayer2 legalRegion ) + 1 2 _NA_) + ) ;symContactDevice + +) ;devices + + +;******************************** +; LAYER RULES +;******************************** + +layerRules( + streamLayers( + ;( layer streamNumber dataType translate ) + ;( ----- ------------ -------- --------- ) + ( ("background" "drawing") 0 0 nil ) + ( ("grid" "drawing") 0 0 nil ) + ( ("grid" "drawing1") 0 0 nil ) + ( ("Nwell" "drawing") 42 0 t ) + ( ("Pwell" "drawing") 41 0 t ) + ( ("Active" "drawing") 43 0 t ) + ( ("ActX" "drawing") 48 0 t ) + ( ("Pselect" "drawing") 44 0 t ) + ( ("Nselect" "drawing") 45 0 t ) + ( ("Poly1" "drawing") 46 0 t ) + ( ("P1Con" "drawing") 47 0 t ) + ( ("Metal1" "drawing") 49 0 t ) + ( ("Metal2" "drawing") 51 0 t ) + ( ("annotate" "drawing") 0 0 nil ) + ( ("annotate" "drawing1") 0 0 nil ) + ( ("annotate" "drawing2") 0 0 nil ) + ( ("annotate" "drawing3") 0 0 nil ) + ( ("annotate" "drawing4") 0 0 nil ) + ( ("annotate" "drawing5") 0 0 nil ) + ( ("annotate" "drawing6") 0 0 nil ) + ( ("annotate" "drawing7") 0 0 nil ) + ( ("annotate" "drawing8") 0 0 nil ) + ( ("annotate" "drawing9") 0 0 nil ) + ( ("Via" "drawing") 50 0 t ) + ( ("Glass" "drawing") 52 0 t ) + ( ("XP" "drawing") 60 0 t ) + ( ("Metal2" "pin") 0 0 nil ) + ( ("Poly1" "pin") 0 0 nil ) + ( ("prBoundary" "drawing") 0 0 nil ) + ( ("Metal1" "pin") 0 0 nil ) + ( ("prBoundary" "boundary") 0 0 nil ) + ( ("instance" "drawing") 246 0 nil ) + ( ("instance" "label") 0 0 nil ) + ( ("Nwell" "net") 0 0 nil ) + ( ("align" "drawing") 0 0 nil ) + ( ("Pwell" "net") 0 0 nil ) + ( ("hardFence" "drawing") 0 0 nil ) + ( ("Active" "net") 0 0 nil ) + ( ("softFence" "drawing") 0 0 nil ) + ( ("ActX" "net") 0 0 nil ) + ( ("A2" "drawing") 5 0 nil ) + ( ("A1" "drawing") 2 0 nil ) + ( ("comment" "drawing") 0 0 nil ) + ( ("border" "drawing") 0 0 nil ) + ( ("Pselect" "net") 0 0 nil ) + ( ("Nselect" "net") 0 0 nil ) + ( ("wire" "drawing") 0 0 nil ) + ( ("Poly1" "net") 0 0 nil ) + ( ("P1Con" "net") 0 0 nil ) + ( ("Metal1" "net") 0 0 nil ) + ( ("Metal2" "net") 0 0 nil ) + ( ("device" "label") 0 0 nil ) + ( ("Via" "net") 0 0 nil ) + ( ("pin" "label") 0 0 nil ) + ( ("text" "drawing") 63 0 t ) + ( ("pin" "drawing") 0 0 nil ) + ( ("device" "drawing") 0 0 nil ) + ( ("axis" "drawing") 0 0 nil ) + ( ("edgeLayer" "drawing") 0 0 nil ) + ( ("edgeLayer" "pin") 0 0 nil ) + ( ("snap" "drawing") 0 0 nil ) + ( ("stretch" "drawing") 0 0 nil ) + ( ("y0" "drawing") 0 0 nil ) + ( ("y1" "drawing") 0 0 nil ) + ( ("y2" "drawing") 0 0 nil ) + ( ("y3" "drawing") 0 0 nil ) + ( ("y4" "drawing") 0 0 nil ) + ( ("y5" "drawing") 0 0 nil ) + ( ("y6" "drawing") 0 0 nil ) + ( ("y7" "drawing") 0 0 nil ) + ( ("y8" "drawing") 0 0 nil ) + ( ("y9" "drawing") 0 0 nil ) + ( ("hilite" "drawing") 0 0 nil ) + ( ("hilite" "drawing2") 0 0 nil ) + ( ("select" "drawing") 0 0 nil ) + ( ("drive" "drawing") 0 0 nil ) + ( ("hiz" "drawing") 0 0 nil ) + ( ("resist" "drawing") 0 0 nil ) + ( ("spike" "drawing") 0 0 nil ) + ( ("supply" "drawing") 0 0 nil ) + ( ("unknown" "drawing") 0 0 nil ) + ( ("unset" "drawing") 0 0 nil ) + ( ("changedLayer" "tool0") 0 0 nil ) + ( ("Resistor" "net") 0 0 nil ) + ( ("Resistor" "drawing") 0 0 nil ) + ( ("Capacitor" "net") 0 0 nil ) + ( ("Capacitor" "drawing") 0 0 nil ) + ( ("Diode" "net") 0 0 nil ) + ( ("Diode" "drawing") 0 0 nil ) + ( ("Poly2" "net") 0 0 nil ) + ( ("Poly2" "drawing") 0 0 nil ) + ( ("P2Con" "net") 0 0 nil ) + ( ("P2Con" "drawing") 0 0 nil ) + ( ("Pbase" "drawing") 0 0 nil ) + ( ("Pbase" "net") 0 0 nil ) + ( P2Con 0 0 nil ) + ( Poly2 0 0 nil ) + ( Pwell 0 0 nil ) + ( Nwell 0 0 nil ) + ( Active 0 0 nil ) + ( Pselect 0 0 nil ) + ( Nselect 0 0 nil ) + ( Poly1 0 0 nil ) + ( P1Con 0 0 nil ) + ( ActX 0 0 nil ) + ( Metal1 0 0 nil ) + ( Via 0 0 nil ) + ( Metal2 0 0 nil ) + ( Glass 0 0 nil ) + ( XP 0 0 nil ) + ( ("Via2" "drawing") 50 0 t ) + ( ("Via2" "net") 0 0 nil ) + ( ("Metal3" "drawing") 50 0 t ) + ( ("Metal3" "net") 0 0 nil ) + ( ("Metal3" "pin") 0 0 nil ) + ( ("CapWell" "drawing") 0 0 nil ) + ( ("CapWell" "net") 0 0 nil ) + ( ("SiBlock" "drawing") 0 0 nil ) + ( ("SiBlock" "net") 0 0 nil ) + ( ("HR" "drawing") 0 0 nil ) + ( ("HR" "net") 0 0 nil ) + ) ;streamLayers + + viaLayers( + ;( layer1 viaLayer layer2 ) + ;( ------ -------- ------ ) + ( Metal2 Via2 Metal3 ) + ( Metal1 Via Metal2 ) + ( Active ActX Poly1 ) + ( Poly1 P1Con Metal1 ) + ( Poly2 P2Con Metal1 ) + ) ;viaLayers + +) ;layerRules + + +;******************************** +; PHYSICAL RULES +;******************************** + +physicalRules( + orderedSpacingRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( minEnclosure "prBoundary" "Metal1" 0.0 ) + ( minEnclosure "Metal2" "Via" 1.0 ) + ( minEnclosure "Metal1" "Via" 1.0 ) + ( minEnclosure "Metal1" "P1Con" 1.0 ) + ( minEnclosure "Metal1" "ActX" 1.0 ) + ( minEnclosure "Nselect" "Active" 2.0 ) + ( minEnclosure "Pselect" "Active" 2.0 ) + ( minEnclosure "Active" "ActX" 1.0 ) + ( minEnclosure "Pwell" "Active" 5.0 ) + ( minEnclosure "Nwell" "Active" 5.0 ) + ) ;orderedSpacingRules + + spacingRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( minSpacing "P2Con" 2.0 ) + ( minSpacing "Poly2" 3.0 ) + ( minSpacing "Pwell" 9.0 ) + ( minSpacing "Nwell" 9.0 ) + ( minSpacing "Active" 3.0 ) + ( minSpacing "Pselect" 2.0 ) + ( minSpacing "Nselect" 2.0 ) + ( minSpacing "Poly1" 2.0 ) + ( minSpacing "P1Con" 2.0 ) + ( minSpacing "ActX" 2.0 ) + ( minSpacing "Metal1" 3.0 ) + ( minSpacing "Via" 3.0 ) + ( minSpacing "Via2" 3.0 ) + ( minSpacing "Metal2" 3.0 ) + ( minSpacing "Metal3" 4.0 ) + ( minSpacing "Glass" 75.0 ) + ( minSpacing "XP" 100.0 ) + ( minSpacing "Metal2" 4.0 ) + ( minSpacing "P1Con" "Via" 2.0 ) + ( minSpacing "ActX" "Via" 2.0 ) + ( minSpacing "ActX" "P2Con" 2.0 ) + ( minSpacing "Poly2" "P2Con" 4.0 ) + ( minSpacing "Poly1" "P1Con" 4.0 ) + ( minSpacing "ActX" "P1Con" 2.0 ) + ( minSpacing "Active" "P1Con" 2.0 ) + ( minSpacing "Active" "Poly2" 2.0 ) + ( minSpacing "Poly1" "Poly2" 2.0 ) + ( minSpacing "Active" "Poly1" 2.0 ) + ( minSpacing "ActX" "Poly1" 2.0 ) + ( minSpacing "Pselect" "Nselect" 0.0 ) + ( minSpacing "Nwell" "Pwell" 9.0 ) + ( minWidth "P2Con" 2.0 ) + ( minWidth "Poly2" 3.0 ) + ( minWidth "Pwell" 10.0 ) + ( minWidth "Nwell" 10.0 ) + ( minWidth "Active" 3.0 ) + ( minWidth "Pselect" 2.0 ) + ( minWidth "Nselect" 2.0 ) + ( minWidth "Poly1" 2.0 ) + ( minWidth "P1Con" 2.0 ) + ( minWidth "ActX" 2.0 ) + ( minWidth "Metal1" 4.0 ) + ( minWidth "Via" 2.0 ) + ( minWidth "Metal2" 4.0 ) + ( minWidth "Glass" 75.0 ) + ( minWidth "XP" 100.0 ) + ( minWidth "Metal3" 6.0 ) + ) ;spacingRules + + mfgGridResolution( + ( 1.000000 ) + ) ;mfgGridResolution + +) ;physicalRules + + +;******************************** +; ELECTRICAL RULES +;******************************** + +electricalRules( + characterizationRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( areaCap "P2Con" 0.0 ) + ( areaCap "Poly2" 0.0 ) + ( areaCap "Active" 0.0 ) + ( areaCap "Poly1" 6e-05 ) + ( areaCap "P1Con" 0.0 ) + ( areaCap "ActX" 0.0 ) + ( areaCap "Metal1" 2.6e-05 ) + ( areaCap "Via" 0.0 ) + ( areaCap "Metal2" 1.6e-05 ) + ( edgeCapacitance "P2Con" 0.0 ) + ( edgeCapacitance "Poly2" 0.0 ) + ( edgeCapacitance "Active" 0.0 ) + ( edgeCapacitance "Poly1" 0.0 ) + ( edgeCapacitance "P1Con" 0.0 ) + ( edgeCapacitance "ActX" 0.0 ) + ( edgeCapacitance "Metal1" 0.0 ) + ( edgeCapacitance "Via" 0.0 ) + ( edgeCapacitance "Metal2" 0.0 ) + ( sheetRes "P2Con" 0.0 ) + ( sheetRes "Poly2" 0.0 ) + ( sheetRes "Active" 0.0 ) + ( sheetRes "Poly1" 23.0 ) + ( sheetRes "P1Con" 0.0 ) + ( sheetRes "ActX" 0.0 ) + ( sheetRes "Metal1" 0.04 ) + ( sheetRes "Via" 0.0 ) + ( sheetRes "Metal2" 0.07 ) + ( currentDensity "P2Con" 1.0 ) + ( currentDensity "Poly2" 1.0 ) + ( currentDensity "Active" 1.0 ) + ( currentDensity "Poly1" 1.0 ) + ( currentDensity "P1Con" 1.0 ) + ( currentDensity "ActX" 1.0 ) + ( currentDensity "Metal1" 1.0 ) + ( currentDensity "Via" 1.0 ) + ( currentDensity "Metal2" 1.0 ) + ) ;characterizationRules + +) ;electricalRules + + +;******************************** +; LAYOUT EDITOR RULES +;******************************** +; specifies the ordering of the layers in the LSW + +leRules( + leLswLayers( + ;( layer purpose ) + ; ----- ------- ) + ( Nwell drawing ) + ( Pselect drawing ) + ( Nselect drawing ) + ( Active drawing ) + ( ActX drawing ) + ( Poly1 drawing ) + ( P1Con drawing ) + ( Metal1 drawing ) + ( Via drawing ) + ( Metal2 drawing ) + ( Via2 drawing ) + ( Metal3 drawing ) + ( Poly1 pin ) + ( Metal1 pin ) + ( Metal2 pin ) + ( Metal3 pin ) + ( Poly2 drawing ) + ( P2Con drawing ) + ( instance drawing ) + ( text drawing ) + ( CapWell drawing ) + ( SiBlock drawing ) + ( HR drawing ) + ( Pbase drawing ) + ( Resistor drawing ) + ( Capacitor drawing ) + ( Diode drawing ) + ( Glass drawing ) + ( XP drawing ) + + ) ;leLswLayers +) ;leRules + + +;******************************** +; VIRTUOSO XL RULES +;******************************** +; specifies the ordering of the layers in the LSW + +lxRules( + lxExtractLayers( + (Metal1 Metal2 Metal3) + ) ;lxExtractLayers +) ;lxRules + From 66cbe0966c8bad036b655109df37b9a8de22ce15 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 11:15:33 -0700 Subject: [PATCH 04/14] Removed old ms_flop unit test --- compiler/tests/11_ms_flop_array_test.py | 35 ------------------------- 1 file changed, 35 deletions(-) delete mode 100755 compiler/tests/11_ms_flop_array_test.py diff --git a/compiler/tests/11_ms_flop_array_test.py b/compiler/tests/11_ms_flop_array_test.py deleted file mode 100755 index d6472a15..00000000 --- a/compiler/tests/11_ms_flop_array_test.py +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env python3 -""" -Run a regression test on a dff_array. -""" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -from globals import OPTS -import debug - -class dff_array_test(openram_test): - - def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import ms_flop_array - - debug.info(2, "Testing ms_flop_array for columns=8, word_size=8") - a = ms_flop_array.ms_flop_array(columns=8, word_size=8) - self.local_check(a) - - debug.info(2, "Testing ms_flop_array for columns=16, word_size=8") - a = ms_flop_array.ms_flop_array(columns=16, word_size=8) - self.local_check(a) - - globals.end_openram() - -# instantiate a copdsay of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() From 3539887ee484479a0ef54abae202400d6fde560a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 11:40:24 -0700 Subject: [PATCH 05/14] Updating ms_flop removal. Updated characterizer for dff. Added new setup/hold results for dff instead of ms_flop. Removed ms_flop references in sram-base. Fixed syntax errors in SCN3ME tech file. --- compiler/characterizer/setup_hold.py | 2 +- compiler/modules/bank.py | 2 +- compiler/modules/multibank.py | 2 +- compiler/options.py | 3 +-- compiler/sram_base.py | 4 ---- compiler/tests/04_precharge_test.py | 0 .../tests/04_single_level_column_mux_test.py | 0 .../07_single_level_column_mux_array_test.py | 0 compiler/tests/08_precharge_array_test.py | 0 compiler/tests/08_wordline_driver_test.py | 0 compiler/tests/09_sense_amp_array_test.py | 0 compiler/tests/10_write_driver_array_test.py | 0 compiler/tests/19_psingle_bank_test.py | 0 compiler/tests/20_psram_1bank_test.py | 0 compiler/tests/21_hspice_setuphold_test.py | 16 ++++++++-------- compiler/tests/21_ngspice_setuphold_test.py | 16 ++++++++-------- technology/scn4me_subm/tech/tech.py | 6 +++--- 17 files changed, 23 insertions(+), 28 deletions(-) mode change 100644 => 100755 compiler/tests/04_precharge_test.py mode change 100644 => 100755 compiler/tests/04_single_level_column_mux_test.py mode change 100644 => 100755 compiler/tests/07_single_level_column_mux_array_test.py mode change 100644 => 100755 compiler/tests/08_precharge_array_test.py mode change 100644 => 100755 compiler/tests/08_wordline_driver_test.py mode change 100644 => 100755 compiler/tests/09_sense_amp_array_test.py mode change 100644 => 100755 compiler/tests/10_write_driver_array_test.py mode change 100644 => 100755 compiler/tests/19_psingle_bank_test.py mode change 100644 => 100755 compiler/tests/20_psram_1bank_test.py diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index eaef6bac..8a515776 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -15,7 +15,7 @@ class setup_hold(): def __init__(self, corner): # This must match the spice model order - self.pins = ["data", "dout", "dout_bar", "clk", "vdd", "gnd"] + self.pins = ["data", "dout", "clk", "vdd", "gnd"] self.model_name = "dff" self.model_location = OPTS.openram_tech + "sp_lib/dff.sp" self.period = tech.spice["feasible_period"] diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index c930d62a..d6c884a4 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -206,7 +206,7 @@ class bank(design.design): def add_modules(self): """ Create all the modules using the class loader """ - mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver", + mod_list = ["bitcell", "decoder", "wordline_driver", "bitcell_array", "sense_amp_array", "precharge_array", "column_mux_array", "write_driver_array", "dff", "bank_select"] diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index 3a63c890..e23fa6aa 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -23,7 +23,7 @@ class multibank(design.design): def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""): - mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver", + mod_list = ["tri_gate", "bitcell", "decoder", "wordline_driver", "bitcell_array", "sense_amp_array", "precharge_array", "column_mux_array", "write_driver_array", "tri_gate_array", "dff", "bank_select"] diff --git a/compiler/options.py b/compiler/options.py index 4d522465..58d97ea0 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -71,8 +71,7 @@ class options(optparse.Values): # These are the default modules that can be over-riden decoder = "hierarchical_decoder" - ms_flop = "ms_flop" - ms_flop_array = "ms_flop_array" + dff_array = "dff_array" dff = "dff" control_logic = "control_logic" bitcell_array = "bitcell_array" diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 67789b78..9a511bd4 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -227,10 +227,6 @@ class sram_base(design): c = reload(__import__(OPTS.control_logic)) self.mod_control_logic = getattr(c, OPTS.control_logic) - c = reload(__import__(OPTS.ms_flop)) - self.mod_ms_flop = getattr(c, OPTS.ms_flop) - self.ms_flop = self.mod_ms_flop() - from control_logic import control_logic # Create the control logic module diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/20_psram_1bank_test.py b/compiler/tests/20_psram_1bank_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index b123ed57..80568196 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -35,15 +35,15 @@ class timing_setup_test(openram_test): data = sh.analyze(slews,slews) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'setup_times_LH': [0.014648399999999999], - 'hold_times_LH': [0.0024414], - 'hold_times_HL': [-0.0036620999999999997], - 'setup_times_HL': [0.0085449]} + golden_data = {'hold_times_HL': [-0.01586914], + 'hold_times_LH': [-0.01586914], + 'setup_times_HL': [0.02685547], + 'setup_times_LH': [0.03295898]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'setup_times_LH': [0.08178709999999999], - 'hold_times_LH': [0.0024414], - 'hold_times_HL': [-0.0646973], - 'setup_times_HL': [0.0390625]} + golden_data = {'hold_times_HL': [-0.15625], + 'hold_times_LH': [-0.1257324], + 'setup_times_HL': [0.2038574], + 'setup_times_LH': [0.2893066]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 849a23f0..df8c60de 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -35,15 +35,15 @@ class timing_setup_test(openram_test): data = sh.analyze(slews,slews) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'setup_times_LH': [0.01464844], - 'hold_times_LH': [0.0024414059999999997], - 'hold_times_HL': [-0.003662109], - 'setup_times_HL': [0.008544922]} + golden_data = {'hold_times_HL': [-0.01586914], + 'hold_times_LH': [-0.01586914], + 'setup_times_HL': [0.02685547], + 'setup_times_LH': [0.03295898]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'setup_times_LH': [0.07568359], - 'hold_times_LH': [0.008544922], - 'hold_times_HL': [-0.05859374999999999], - 'setup_times_HL': [0.03295898]} + golden_data = {'hold_times_HL': [-0.15625], + 'hold_times_LH': [-0.1257324], + 'setup_times_HL': [0.2038574], + 'setup_times_LH': [0.2893066]} else: self.assertTrue(False) # other techs fail diff --git a/technology/scn4me_subm/tech/tech.py b/technology/scn4me_subm/tech/tech.py index 565d73bc..85285f84 100755 --- a/technology/scn4me_subm/tech/tech.py +++ b/technology/scn4me_subm/tech/tech.py @@ -184,7 +184,7 @@ drc["via2_to_via2"] = 3*_lambda_ # 15.1 Minimum width drc["minwidth_metal3"] = 3*_lambda_ # 15.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 3*_lamda_ +drc["metal3_to_metal3"] = 3*_lambda_ # 15.3 Minimum overlap of via 2 drc["metal3_extend_via2"] = _lambda_ # Reserved for asymmetric enclosures @@ -206,9 +206,9 @@ drc["via3_to_via3"] = 3*_lambda_ # 22.1 Minimum width drc["minwidth_metal3"] = 6*_lambda_ # 22.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 6*_lamda_ +drc["metal3_to_metal3"] = 6*_lambda_ # 22.3 Minimum overlap of via 2 -drc["metal3_extend_via2"] = 2_lambda_ +drc["metal3_extend_via2"] = 2*_lambda_ # Reserved for asymmetric enclosures drc["metal3_enclosure_via2"] = 2*_lambda_ # Not a rule From 63d0523228b5c302432243152feedc93b295a0c5 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 12:53:35 -0700 Subject: [PATCH 06/14] Added scn4m_subm. Added scn4m_subm files (instead of scn4me_subm). Fixed missing cifoutput/cifinput in magic tech file and gds files. Fixed incorrect M3/via3/M4 design rules. --- compiler/tests/config_20_scn4m_subm.py | 9 + technology/scn3me_subm/tech/tech.py | 2 +- .../gds_lib/cell_6t.gds | Bin 5660 -> 5724 bytes .../gds_lib/dff.gds | Bin 16558 -> 16622 bytes .../gds_lib/replica_cell_6t.gds | Bin 5804 -> 5868 bytes .../gds_lib/sense_amp.gds | Bin 8248 -> 8312 bytes .../gds_lib/tri_gate.gds | Bin 4512 -> 4576 bytes .../gds_lib/write_driver.gds | Bin 11740 -> 11804 bytes technology/scn4m_subm/mag_lib/.magicrc | 5 + .../mag_lib/cell_6t.mag | 0 technology/scn4m_subm/mag_lib/convertall.sh | 14 + .../mag_lib/dff.mag | 0 .../mag_lib/replica_cell_6t.mag | 0 .../mag_lib/sense_amp.mag | 0 .../mag_lib/tri_gate.mag | 0 .../mag_lib/write_driver.mag | 0 .../models/ff/nmos.sp | 0 .../models/ff/pmos.sp | 0 .../models/nom/nmos.sp | 0 .../models/nom/pmos.sp | 0 .../models/ss/nmos.sp | 0 .../models/ss/pmos.sp | 0 .../sp_lib/cell_6t.sp | 0 .../{scn4me_subm => scn4m_subm}/sp_lib/dff.sp | 2 +- .../sp_lib/replica_cell_6t.sp | 0 .../sp_lib/sense_amp.sp | 0 .../sp_lib/tri_gate.sp | 0 .../sp_lib/write_driver.sp | 0 .../sue_lib/cell_6t.sue | 0 .../sue_lib/ms_flop.sue | 0 .../sue_lib/replica_cell_6t.sue | 0 .../sue_lib/sense_amp.sue | 0 .../sue_lib/tri_gate.sue | 0 .../sue_lib/write_driver.sue | 0 .../tech/LICENSE.txt | 0 .../tech/SCN4M_SUBM.20.tech | 3725 +++-------------- .../tech/__init__.py | 0 .../{scn4me_subm => scn4m_subm}/tech/tech.py | 22 +- .../{scn4me_subm => scn4m_subm}/tf/LICENSE | 0 .../{scn4me_subm => scn4m_subm}/tf/README | 0 .../tf/display.drf | 0 .../tf/glade_scn4me_subm.py | 0 .../{scn4me_subm => scn4m_subm}/tf/layers.map | 0 .../{scn4me_subm => scn4m_subm}/tf/mosis.tf | 0 technology/scn4me_subm/mag_lib/.magicrc | 5 - .../setup_scripts/setup_openram_scn4m_subm.py | 41 + 46 files changed, 649 insertions(+), 3176 deletions(-) create mode 100644 compiler/tests/config_20_scn4m_subm.py rename technology/{scn4me_subm => scn4m_subm}/gds_lib/cell_6t.gds (96%) rename technology/{scn4me_subm => scn4m_subm}/gds_lib/dff.gds (98%) rename technology/{scn4me_subm => scn4m_subm}/gds_lib/replica_cell_6t.gds (96%) rename technology/{scn4me_subm => scn4m_subm}/gds_lib/sense_amp.gds (97%) rename technology/{scn4me_subm => scn4m_subm}/gds_lib/tri_gate.gds (94%) rename technology/{scn4me_subm => scn4m_subm}/gds_lib/write_driver.gds (98%) create mode 100644 technology/scn4m_subm/mag_lib/.magicrc rename technology/{scn4me_subm => scn4m_subm}/mag_lib/cell_6t.mag (100%) create mode 100755 technology/scn4m_subm/mag_lib/convertall.sh rename technology/{scn4me_subm => scn4m_subm}/mag_lib/dff.mag (100%) rename technology/{scn4me_subm => scn4m_subm}/mag_lib/replica_cell_6t.mag (100%) rename technology/{scn4me_subm => scn4m_subm}/mag_lib/sense_amp.mag (100%) rename technology/{scn4me_subm => scn4m_subm}/mag_lib/tri_gate.mag (100%) rename technology/{scn4me_subm => scn4m_subm}/mag_lib/write_driver.mag (100%) rename technology/{scn4me_subm => scn4m_subm}/models/ff/nmos.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/models/ff/pmos.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/models/nom/nmos.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/models/nom/pmos.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/models/ss/nmos.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/models/ss/pmos.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/sp_lib/cell_6t.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/sp_lib/dff.sp (96%) rename technology/{scn4me_subm => scn4m_subm}/sp_lib/replica_cell_6t.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/sp_lib/sense_amp.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/sp_lib/tri_gate.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/sp_lib/write_driver.sp (100%) rename technology/{scn4me_subm => scn4m_subm}/sue_lib/cell_6t.sue (100%) rename technology/{scn4me_subm => scn4m_subm}/sue_lib/ms_flop.sue (100%) rename technology/{scn4me_subm => scn4m_subm}/sue_lib/replica_cell_6t.sue (100%) rename technology/{scn4me_subm => scn4m_subm}/sue_lib/sense_amp.sue (100%) rename technology/{scn4me_subm => scn4m_subm}/sue_lib/tri_gate.sue (100%) rename technology/{scn4me_subm => scn4m_subm}/sue_lib/write_driver.sue (100%) rename technology/{scn4me_subm => scn4m_subm}/tech/LICENSE.txt (100%) rename technology/{scn4me_subm => scn4m_subm}/tech/SCN4M_SUBM.20.tech (57%) rename technology/{scn4me_subm => scn4m_subm}/tech/__init__.py (100%) rename technology/{scn4me_subm => scn4m_subm}/tech/tech.py (96%) rename technology/{scn4me_subm => scn4m_subm}/tf/LICENSE (100%) rename technology/{scn4me_subm => scn4m_subm}/tf/README (100%) rename technology/{scn4me_subm => scn4m_subm}/tf/display.drf (100%) rename technology/{scn4me_subm => scn4m_subm}/tf/glade_scn4me_subm.py (100%) rename technology/{scn4me_subm => scn4m_subm}/tf/layers.map (100%) rename technology/{scn4me_subm => scn4m_subm}/tf/mosis.tf (100%) delete mode 100644 technology/scn4me_subm/mag_lib/.magicrc create mode 100644 technology/setup_scripts/setup_openram_scn4m_subm.py diff --git a/compiler/tests/config_20_scn4m_subm.py b/compiler/tests/config_20_scn4m_subm.py new file mode 100644 index 00000000..ca112a97 --- /dev/null +++ b/compiler/tests/config_20_scn4m_subm.py @@ -0,0 +1,9 @@ +word_size = 1 +num_words = 16 +num_banks = 1 + +tech_name = "scn4m_subm" +process_corners = ["TT"] +supply_voltages = [5.0] +temperatures = [25] + diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 52c602cf..c09e109b 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -157,7 +157,7 @@ drc["minarea_metal1"] = 0 # 8.1 Exact size drc["minwidth_via1"] = 2*_lambda_ # 8.2 Minimum via1 spacing -drc["via1_to_via1"] = 2*_lambda_ +drc["via1_to_via1"] = 3*_lambda_ # 9.1 Minimum width drc["minwidth_metal2"] = 3*_lambda_ diff --git a/technology/scn4me_subm/gds_lib/cell_6t.gds b/technology/scn4m_subm/gds_lib/cell_6t.gds similarity index 96% rename from technology/scn4me_subm/gds_lib/cell_6t.gds rename to technology/scn4m_subm/gds_lib/cell_6t.gds index e44a111806248b29d516fd0d0b79a5b2a0d26eba..df64404849cfca64d73c49d74d3ea497d6f33fcf 100644 GIT binary patch delta 100 zcmbQEb4O=_EGrL#27|>!CG!98FEGs9227};4C368VgMo*QEjcwOC*G`N4}%7S#Y81zA25S~gN-dEEscSJg@b{CjhBhRo`H>ziGhJZM}Qef ZLP4kogaM-c6d-IE4dk&1ZcOxb005gT3g7?$ delta 34 mcmaFY$hfYNae^!>CxZrq!bBxw9x#J}gN-dEEp6jMUk3n_2M7uP diff --git a/technology/scn4me_subm/gds_lib/replica_cell_6t.gds b/technology/scn4m_subm/gds_lib/replica_cell_6t.gds similarity index 96% rename from technology/scn4me_subm/gds_lib/replica_cell_6t.gds rename to technology/scn4m_subm/gds_lib/replica_cell_6t.gds index 0a3226dcea5402be81254e1fe89f4b417c7fc9db..6a6b32adb52b8061b43e681556d321176f8dda04 100644 GIT binary patch delta 108 zcmZ3Z`$l(yEGrL#27|>!CHn|4gF%Fittho1Co?%QJ~=ffC*G`tfq{jCfq{*eiNT(M jjgN_efk8)r8Aw8b)C33vL@R%QuwgWi$0E3~(pU@tFuV|k delta 44 wcmaE(yGD0{EGs9227~EDC3^`lgF%Fittho1Co?%QJ~=ffC*G`N<4$8S0QaH{HUIzs diff --git a/technology/scn4me_subm/gds_lib/sense_amp.gds b/technology/scn4m_subm/gds_lib/sense_amp.gds similarity index 97% rename from technology/scn4me_subm/gds_lib/sense_amp.gds rename to technology/scn4m_subm/gds_lib/sense_amp.gds index 7212992021da885b7223e5147e01ee08ce59e94f..cf5fa5872f978d8b62c59084ec4deea7bb926cbd 100644 GIT binary patch delta 83 zcmdnt@WWw(EGrL#27|>!B}*tHLEOxqfsK!efq_9sfEh?afz$*D14P$HK-e%E$YT-Q In0s0t03?SCod5s; delta 28 ecmez2u)|@3EGs92CIjn4B}*tHL44!(gYp1vVF!`` diff --git a/technology/scn4me_subm/gds_lib/tri_gate.gds b/technology/scn4m_subm/gds_lib/tri_gate.gds similarity index 94% rename from technology/scn4me_subm/gds_lib/tri_gate.gds rename to technology/scn4m_subm/gds_lib/tri_gate.gds index 78d40b8bfc85fce5cd2febcf0c330ffcce9fa40c..ad83f4c63d59f757b95862a8a5886dcc92f58eb2 100644 GIT binary patch delta 101 zcmZ3W{6KkvEGrL#27|>!CG$WqgMo*Qt)wV3K0UD{m4StWfq{*eiNT(MjgN_efk8)r d8Aw8b)C33vL|XzCf&h#LGFb!}HfEU#0ssYT3-tg1 delta 37 pcmaE$yg+$^EGs92CWF94C38VAgMo*Qt)wV3K0UD{b>k{CK>(d_2>}2A diff --git a/technology/scn4me_subm/gds_lib/write_driver.gds b/technology/scn4m_subm/gds_lib/write_driver.gds similarity index 98% rename from technology/scn4me_subm/gds_lib/write_driver.gds rename to technology/scn4m_subm/gds_lib/write_driver.gds index 11ad9c15076becdf44b4126ca25b79a30e438952..44dabaf15053ee00c0423e6f735b73240698d467 100644 GIT binary patch delta 104 zcmcZ;Jtt;@EGrL#27|>!CF?*igF%3et-L6+BsD&zD6=fJh=GNJfq{*eiNT(MjgN_e hfk8)r8Aw8b)C33vM9;kdVZ&$!hKcLsHuePQ0s#Cj5+wit delta 41 tcmbOeb0>O&EGs92CWFjGC2LVIgF%3et-L6+BsD&zD6=fJXyc|VT>#pK3#|YE diff --git a/technology/scn4m_subm/mag_lib/.magicrc b/technology/scn4m_subm/mag_lib/.magicrc new file mode 100644 index 00000000..0dfe42ef --- /dev/null +++ b/technology/scn4m_subm/mag_lib/.magicrc @@ -0,0 +1,5 @@ +path sys +$::env(OPENRAM_TECH)/scn4m_subm/tech +tech load SCN4M_SUBM.20 -noprompt +scalegrid 1 4 +set GND gnd +set VDD vdd diff --git a/technology/scn4me_subm/mag_lib/cell_6t.mag b/technology/scn4m_subm/mag_lib/cell_6t.mag similarity index 100% rename from technology/scn4me_subm/mag_lib/cell_6t.mag rename to technology/scn4m_subm/mag_lib/cell_6t.mag diff --git a/technology/scn4m_subm/mag_lib/convertall.sh b/technology/scn4m_subm/mag_lib/convertall.sh new file mode 100755 index 00000000..f5e2482c --- /dev/null +++ b/technology/scn4m_subm/mag_lib/convertall.sh @@ -0,0 +1,14 @@ +magic -dnull -noconsole << EOF +load dff +gds write dff.gds +load cell_6t +gds write cell_6t.gds +load replica_cell_6t +gds write replica_cell_6t.gds +load sense_amp +gds write sense_amp.gds +load tri_gate +gds write tri_gate.gds +load write_driver +gds write write_driver.gds +EOF diff --git a/technology/scn4me_subm/mag_lib/dff.mag b/technology/scn4m_subm/mag_lib/dff.mag similarity index 100% rename from technology/scn4me_subm/mag_lib/dff.mag rename to technology/scn4m_subm/mag_lib/dff.mag diff --git a/technology/scn4me_subm/mag_lib/replica_cell_6t.mag b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag similarity index 100% rename from technology/scn4me_subm/mag_lib/replica_cell_6t.mag rename to technology/scn4m_subm/mag_lib/replica_cell_6t.mag diff --git a/technology/scn4me_subm/mag_lib/sense_amp.mag b/technology/scn4m_subm/mag_lib/sense_amp.mag similarity index 100% rename from technology/scn4me_subm/mag_lib/sense_amp.mag rename to technology/scn4m_subm/mag_lib/sense_amp.mag diff --git a/technology/scn4me_subm/mag_lib/tri_gate.mag b/technology/scn4m_subm/mag_lib/tri_gate.mag similarity index 100% rename from technology/scn4me_subm/mag_lib/tri_gate.mag rename to technology/scn4m_subm/mag_lib/tri_gate.mag diff --git a/technology/scn4me_subm/mag_lib/write_driver.mag b/technology/scn4m_subm/mag_lib/write_driver.mag similarity index 100% rename from technology/scn4me_subm/mag_lib/write_driver.mag rename to technology/scn4m_subm/mag_lib/write_driver.mag diff --git a/technology/scn4me_subm/models/ff/nmos.sp b/technology/scn4m_subm/models/ff/nmos.sp similarity index 100% rename from technology/scn4me_subm/models/ff/nmos.sp rename to technology/scn4m_subm/models/ff/nmos.sp diff --git a/technology/scn4me_subm/models/ff/pmos.sp b/technology/scn4m_subm/models/ff/pmos.sp similarity index 100% rename from technology/scn4me_subm/models/ff/pmos.sp rename to technology/scn4m_subm/models/ff/pmos.sp diff --git a/technology/scn4me_subm/models/nom/nmos.sp b/technology/scn4m_subm/models/nom/nmos.sp similarity index 100% rename from technology/scn4me_subm/models/nom/nmos.sp rename to technology/scn4m_subm/models/nom/nmos.sp diff --git a/technology/scn4me_subm/models/nom/pmos.sp b/technology/scn4m_subm/models/nom/pmos.sp similarity index 100% rename from technology/scn4me_subm/models/nom/pmos.sp rename to technology/scn4m_subm/models/nom/pmos.sp diff --git a/technology/scn4me_subm/models/ss/nmos.sp b/technology/scn4m_subm/models/ss/nmos.sp similarity index 100% rename from technology/scn4me_subm/models/ss/nmos.sp rename to technology/scn4m_subm/models/ss/nmos.sp diff --git a/technology/scn4me_subm/models/ss/pmos.sp b/technology/scn4m_subm/models/ss/pmos.sp similarity index 100% rename from technology/scn4me_subm/models/ss/pmos.sp rename to technology/scn4m_subm/models/ss/pmos.sp diff --git a/technology/scn4me_subm/sp_lib/cell_6t.sp b/technology/scn4m_subm/sp_lib/cell_6t.sp similarity index 100% rename from technology/scn4me_subm/sp_lib/cell_6t.sp rename to technology/scn4m_subm/sp_lib/cell_6t.sp diff --git a/technology/scn4me_subm/sp_lib/dff.sp b/technology/scn4m_subm/sp_lib/dff.sp similarity index 96% rename from technology/scn4me_subm/sp_lib/dff.sp rename to technology/scn4m_subm/sp_lib/dff.sp index d35d5123..3d8db9d8 100644 --- a/technology/scn4me_subm/sp_lib/dff.sp +++ b/technology/scn4m_subm/sp_lib/dff.sp @@ -14,7 +14,7 @@ M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u M1009 vdd Q a_320_336# vdd p w=2u l=0.4u -M1010 gnd clk a_24_24# gnd nfet w=4u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u M1011 Q a_280_24# vdd vdd p w=8u l=0.4u M1012 a_84_24# D gnd gnd n w=2u l=0.4u M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u diff --git a/technology/scn4me_subm/sp_lib/replica_cell_6t.sp b/technology/scn4m_subm/sp_lib/replica_cell_6t.sp similarity index 100% rename from technology/scn4me_subm/sp_lib/replica_cell_6t.sp rename to technology/scn4m_subm/sp_lib/replica_cell_6t.sp diff --git a/technology/scn4me_subm/sp_lib/sense_amp.sp b/technology/scn4m_subm/sp_lib/sense_amp.sp similarity index 100% rename from technology/scn4me_subm/sp_lib/sense_amp.sp rename to technology/scn4m_subm/sp_lib/sense_amp.sp diff --git a/technology/scn4me_subm/sp_lib/tri_gate.sp b/technology/scn4m_subm/sp_lib/tri_gate.sp similarity index 100% rename from technology/scn4me_subm/sp_lib/tri_gate.sp rename to technology/scn4m_subm/sp_lib/tri_gate.sp diff --git a/technology/scn4me_subm/sp_lib/write_driver.sp b/technology/scn4m_subm/sp_lib/write_driver.sp similarity index 100% rename from technology/scn4me_subm/sp_lib/write_driver.sp rename to technology/scn4m_subm/sp_lib/write_driver.sp diff --git a/technology/scn4me_subm/sue_lib/cell_6t.sue b/technology/scn4m_subm/sue_lib/cell_6t.sue similarity index 100% rename from technology/scn4me_subm/sue_lib/cell_6t.sue rename to technology/scn4m_subm/sue_lib/cell_6t.sue diff --git a/technology/scn4me_subm/sue_lib/ms_flop.sue b/technology/scn4m_subm/sue_lib/ms_flop.sue similarity index 100% rename from technology/scn4me_subm/sue_lib/ms_flop.sue rename to technology/scn4m_subm/sue_lib/ms_flop.sue diff --git a/technology/scn4me_subm/sue_lib/replica_cell_6t.sue b/technology/scn4m_subm/sue_lib/replica_cell_6t.sue similarity index 100% rename from technology/scn4me_subm/sue_lib/replica_cell_6t.sue rename to technology/scn4m_subm/sue_lib/replica_cell_6t.sue diff --git a/technology/scn4me_subm/sue_lib/sense_amp.sue b/technology/scn4m_subm/sue_lib/sense_amp.sue similarity index 100% rename from technology/scn4me_subm/sue_lib/sense_amp.sue rename to technology/scn4m_subm/sue_lib/sense_amp.sue diff --git a/technology/scn4me_subm/sue_lib/tri_gate.sue b/technology/scn4m_subm/sue_lib/tri_gate.sue similarity index 100% rename from technology/scn4me_subm/sue_lib/tri_gate.sue rename to technology/scn4m_subm/sue_lib/tri_gate.sue diff --git a/technology/scn4me_subm/sue_lib/write_driver.sue b/technology/scn4m_subm/sue_lib/write_driver.sue similarity index 100% rename from technology/scn4me_subm/sue_lib/write_driver.sue rename to technology/scn4m_subm/sue_lib/write_driver.sue diff --git a/technology/scn4me_subm/tech/LICENSE.txt b/technology/scn4m_subm/tech/LICENSE.txt similarity index 100% rename from technology/scn4me_subm/tech/LICENSE.txt rename to technology/scn4m_subm/tech/LICENSE.txt diff --git a/technology/scn4me_subm/tech/SCN4M_SUBM.20.tech b/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech similarity index 57% rename from technology/scn4me_subm/tech/SCN4M_SUBM.20.tech rename to technology/scn4m_subm/tech/SCN4M_SUBM.20.tech index 7400825c..bb2c2490 100644 --- a/technology/scn4me_subm/tech/SCN4M_SUBM.20.tech +++ b/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech @@ -1,5 +1,5 @@ tech - format 32 + format 29 scmos end @@ -28,127 +28,107 @@ planes end types - well nwell,nw - active nwr - well pwell,pw - implant n_field_implant,nfi - implant p_field_implant,pfi - select nselect,ns - select pselect,ps - active ntransistor,nfet - active ptransistor,pfet - active diffusion,diff - active transistor,fet - active ndiffusion,ndif,green - active pdiffusion,pdif,brown - active ndcontact,ndc - active pdcontact,pdc - active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd - active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd - active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc - active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc - active nwsd - active nwsc - active polysilicon,red,poly,p - active polycontact,pcontact,polycut,pc - contact genericcontact,gcontact,gc - metal1 metal1,m1,blue - metal1 pseudo_rmetal1,prm1 - metal1 rmetal1,rm1 - metal1 fillm1,fm1 - metal1 m2contact,m2cut,m2c,via1,v1,via - metal1 pm12contact,pm12c - metal1 pdm12contact,pdm12c - metal1 psm12contact,psm12c,pom12c,pwm12c - metal1 ndm12contact,ndm12c - metal1 nsm12contact,nsm12c,nom12c,nwm12c - metal1 nwsm12contact,nwsm12c - metal2 metal2,m2,purple - metal2 pseudo_rmetal2,prm2 - metal2 rmetal2,rm2 - metal2 fillm2,fm2 - via1 gv1 - metal2 m3contact,m3cut,m3c,via2,v2 - metal2 m123contact,m123c - metal3 metal3,m3,cyan - metal3 pseudo_rmetal3,prm3 - metal3 rmetal3,rm3 - metal3 fillm3,fm3 - via2 gv2 - metal3 m234contact,m234c - metal3 m4contact,m4cut,m4c,via3,v3 - metal4 metal4,m4,yellow - metal4 pseudo_rmetal4,prm4 - metal4 rmetal4,rm4 - metal4 fillm4,fm4 - via3 gv3 - metal4 pad - oxide glass - active silicide_block,sb - active poly_resist,pres - active pseudo_rpoly,prp - active rpoly,rp - active pseudo_rndiffusion,prnd - active rndiffusion,rndiff,rnd - active pseudo_rpdiffusion,prpd - active rpdiffusion,rpdiff,rpd - active pseudo_rnwell,prnwell,prnw - active rnwell,rnw - active pseudo_nwr,pnwr - implant filln,fn - fill filla,fa - fill fillb,fb - active fillp,fp - active fillapm,fapm - active activen_resist,anres - active activep_resist,apres - xp xp - xp m1p - xp m2p - xp m3p - xp m4p - comment comment - comment bb + well nwell,nw + active nwr + well pwell,pw + implant n_field_implant,nfi + implant p_field_implant,pfi + select nselect,ns + select pselect,ps + active ntransistor,nfet + active ptransistor,pfet + active diffusion,diff + active transistor,fet + active ndiffusion,ndif,green + active pdiffusion,pdif,brown + active ndcontact,ndc + active pdcontact,pdc + active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd + active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd + active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc + active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc + active nwsd + active nwsc + active polysilicon,red,poly,p + active polycontact,pcontact,polycut,pc + contact genericcontact,gcontact,gc + metal1 metal1,m1,blue + metal1 pseudo_rmetal1,prm1 + metal1 rmetal1,rm1 + metal1 fillm1,fm1 + metal1 m2contact,m2cut,m2c,via1,v1 + metal2 metal2,m2,purple + metal2 pseudo_rmetal2,prm2 + metal2 rmetal2,rm2 + metal2 fillm2,fm2 + via1 gv1 + metal2 m3contact,m3cut,m3c,via2,v2 + metal3 metal3,m3,cyan + metal3 pseudo_rmetal3,prm3 + metal3 rmetal3,rm3 + metal3 fillm3,fm3 + via2 gv2 + metal3 m4contact,m4cut,m4c,via3,v3 + metal4 metal4,m4,yellow + metal4 pseudo_rmetal4,prm4 + metal4 rmetal4,rm4 + metal4 fillm4,fm4 + via3 gv3 + metal4 pad + oxide glass + active silicide_block,sb + active poly_resist,pres + active pseudo_rpoly,prp + active rpoly,rp + active pseudo_rndiffusion,prnd + active rndiffusion,rndiff,rnd + active pseudo_rpdiffusion,prpd + active rpdiffusion,rpdiff,rpd + active pseudo_rnwell,prnwell,prnw + active rnwell,rnw + active pseudo_nwr,pnwr + implant filln,fn + fill filla,fa + fill fillb,fb + active fillp,fp + active fillapm,fapm + active activen_resist,anres + active activep_resist,apres + xp xp + xp m1p + xp m2p + xp m3p + xp m4p + comment comment + comment bb end contact - pc poly metal1 - ndc ndiff metal1 - pdc pdiff metal1 - nsc nsd metal1 - nwsc nwsd metal1 - psc psd metal1 - m2c metal1 metal2 - m3c metal2 metal3 - m4c metal3 metal4 - # pm12c poly metal1 metal2 - # pdm12c pdiff metal1 metal2 - # psm12c psd metal1 metal2 - # ndm12c ndiff metal1 metal2 - # nsm12c nsd metal1 metal2 - # nwsm12c nwsd metal1 metal2 - # m123c metal1 metal2 metal3 - # m234c metal2 metal3 metal4 - stackable pc m2c pm12c - stackable pdc m2c pdm12c - stackable psc m2c psm12c - stackable ndc m2c ndm12c - stackable nsc m2c nsm12c - stackable nwsc m2c nwsm12c - stackable m2c m3c m123c - stackable m3c m4c m234c + pc poly metal1 + ndc ndiff metal1 + pdc pdiff metal1 + nsc nsd metal1 + nwsc nwsd metal1 + psc psd metal1 + m2c metal1 metal2 + m3c metal2 metal3 + m4c metal3 metal4 + stackable pc m2c pm12contact,pm12c + stackable pdc m2c pdm12contact,pdm12c + stackable psc m2c psm12contact,psm12c,pom12c,pwm12c + stackable ndc m2c ndm12contact,ndm12c + stackable nsc m2c nsm12contact,nsm12c,nom12c,nwm12c + stackable nwsc m2c nwsm12contact,nwsm12c + stackable m2c m3c m123contact,m123c + stackable m3c m4c m234contact,m234c end styles styletype mos nwr 54 pnwr 53 - nwsd 3 - nwsd 54 - nwsc 3 - nwsc 20 - nwsc 32 - nwsc 54 + nwsd 3 54 + nwsc 3 20 32 54 nwell 12 pwell 13 nfi 53 @@ -156,154 +136,65 @@ styles nselect 43 pselect 44 diff 25 - tran 2 - tran 4 + tran 2 4 ndiff 2 pdiff 4 nsd 3 psd 5 - nfet 6 - nfet 7 - pfet 8 - pfet 9 - ndc 2 - ndc 20 - ndc 32 - pdc 4 - pdc 20 - pdc 32 - nsc 3 - nsc 20 - nsc 32 - psc 5 - psc 20 - psc 32 + nfet 6 7 + pfet 8 9 + ndc 2 20 32 + pdc 4 20 32 + nsc 3 20 32 + psc 5 20 32 poly 1 - pcontact 1 - pcontact 20 - pcontact 32 + pcontact 1 20 32 gc 32 metal1 20 - rm1 20 - rm1 48 + rm1 20 48 prm1 48 - m1p 20 - m1p 34 - fm1 20 - fm1 34 - fp 1 - fp 34 + m1p 20 34 + fm1 20 34 + fp 1 34 fa 32 - fb 45 - fb 34 - fn 45 - fn 34 - fapm 1 - fapm 20 - fapm 21 - fapm 34 + fb 45 34 + fn 45 34 + fapm 1 20 21 34 gv1 55 - m2contact 20 - m2contact 21 - m2contact 55 - pm12contact 1 - pm12contact 20 - pm12contact 21 - pm12contact 32 - pm12contact 55 - ndm12c 2 - ndm12c 20 - ndm12c 21 - ndm12c 32 - ndm12c 55 - nsm12c 3 - nsm12c 20 - nsm12c 21 - nsm12c 32 - nsm12c 55 - nwsm12c 3 - nwsm12c 20 - nwsm12c 21 - nwsm12c 32 - nwsm12c 55 - nwsm12c 54 - pdm12c 4 - pdm12c 20 - pdm12c 21 - pdm12c 32 - pdm12c 55 - psm12c 5 - psm12c 20 - psm12c 21 - psm12c 32 - psm12c 55 + m2contact 20 21 55 metal2 21 - rm2 21 - rm2 48 + rm2 21 48 prm2 48 - m2p 21 - m2p 34 - fm2 21 - fm2 34 + m2p 21 34 + fm2 21 34 gv2 56 - m3contact 21 - m3contact 22 - m3contact 56 - m123c 20 - m123c 21 - m123c 22 - m123c 55 - m123c 56 + m3contact 21 22 56 metal3 22 - rm3 22 - rm3 48 + rm3 22 48 prm3 48 - m3p 22 - m3p 34 - fm3 22 - fm3 34 + m3p 22 34 + fm3 22 34 gv3 57 - m4contact 22 - m4contact 23 - m4contact 57 - m234contact 21 - m234contact 22 - m234contact 23 - m234contact 56 - m234contact 57 + m4contact 22 23 57 metal4 23 - rm4 23 - rm4 48 + rm4 23 48 prm4 48 - m4p 23 - m4p 34 - fm4 23 - fm4 34 - pad 22 - pad 23 - pad 34 - pad 38 + m4p 23 34 + fm4 23 34 + pad 22 23 34 38 glass 34 - xp 25 - xp 34 + xp 25 34 sb 10 - pres 47 - pres 48 - rp 47 - rp 48 + pres 47 48 + rp 47 48 prp 48 - anres 2 - anres 48 - rnd 2 - rnd 48 + anres 2 48 + rnd 2 48 prnd 48 - apres 4 - apres 53 - rpd 4 - rpd 53 + apres 4 53 + rpd 4 53 prpd 53 - rnw 12 - rnw 53 + rnw 12 53 prnw 54 comment 45 bb 32 @@ -377,18 +268,18 @@ compose end connect - nwell,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nsd,nwsd nwell,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nsd,nwsd - pwell,psc/a,psm12c/a,psd pwell,psc/a,psm12c/a,psd - m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 - m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 - m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 - m4,fm4,fapm,m4c/m4,m234c/m4 m4,fm4,fapm,m4c/m4,m234c/m4 - ndiff,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdiff,psd,pdc/a,pdm12c/a,psc/a,psm12c/a ndiff,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdiff,psd,pdc/a,pdm12c/a,psc/a,psm12c/a - poly,fp,nfet,pfet,fet,fapm,pc/a,pm12c/a poly,fp,nfet,pfet,fet,fapm,pc/a,pm12c/a - gc poly,fp,ndiff,pdiff,nsd,nwsd,psd,m1,fm1,fapm,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 - gv1 m1,fm1,fapm,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2,fm2,fapm,m3c/m2,m123c/m2,m234c/m2 - gv2 m2,fm2,fapm,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3,fm3,fapm,m4c/m3,m234c/m3 - gv3 m3,fm3,fapm,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4,fm4,fapm + nwell,nsc/a,nwsc/a,nsd,nwsd nwell,nsc/a,nwsc/a,nsd,nwsd + pwell,psc/a,psd pwell,psc/a,psd + m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 + m3,fm3,fapm,m3c/m3,m4c/m3,m4c/m3 m3,fm3,fapm,m3c/m3,m4c/m3,m4c/m3 + m4,fm4,fapm,m4c/m4 m4,fm4,fapm,m4c/m4 + ndiff,nsd,nwsd,ndc/a,nsc/a,nwsc/a,pdiff,psd,pdc/a,psc/a ndiff,nsd,nwsd,ndc/a,nsc/a,nwsc/a,pdiff,psd,pdc/a,psc/a + poly,fp,nfet,pfet,fet,fapm,pc/a poly,fp,nfet,pfet,fet,fapm,pc/a + gc poly,fp,ndiff,pdiff,nsd,nwsd,psd,m1,fm1,fapm,m2c/m1 + gv1 m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2,fm2,fapm,m3c/m2 + gv2 m2,fm2,fapm,m2c/m2,m3c/m2,m3,fm3,fapm,m4c/m3 + gv3 m3,fm3,fapm,m3c/m3,m4c/m3,m4,fm4,fapm pad m1,fm1,m2,fm2,m3,fm3,m4,fm4 rm1 prm1 rm2 prm2 @@ -408,10 +299,16 @@ cifoutput style lambda=0.20(p) scalefactor 20 10 + options calma-permissive-labels + + # This is a custom section to add bounding boxes in OpenRAM + layer BB bb + labels bb + calma 63 0 layer CWN nwell,rnw,nwr,nwsd,nwsc - bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 - bloat-or nsd,nsc/a,nsm12c/a * 60 + bloat-or pdiff,apres,rpd,pdc/a,pfet * 120 + bloat-or nsd,nsc/a * 60 bloat-or nfi * 80 grow 60 shrink 60 @@ -452,8 +349,8 @@ style lambda=0.20(p) calma 93 0 layer CWP pwell - bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a,nfet * 120 - bloat-or psd,psc/a,psm12c/a * 60 + bloat-or ndiff,anres,rnd,ndc/a,nfet * 120 + bloat-or psd,psc/a * 60 bloat-or pfi * 80 grow 60 shrink 60 @@ -475,17 +372,17 @@ style lambda=0.20(p) #diffusion auto-nselect (will have priority) templayer XDN - bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 + bloat-or ndiff,anres,rnd,ndc/a * 40 psd,psc/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP - bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 + bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0 or TPS #final pselect templayer FSP - bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN @@ -497,7 +394,7 @@ style lambda=0.20(p) #final nselect templayer FSN - bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 40 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 and-not nwr or XDN #never conflict with final pselect @@ -515,27 +412,27 @@ style lambda=0.20(p) layer CSP FSP calma 44 0 - layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet - labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 - layer CCA nwsc/m1,nwsm12c/m1 + layer CCA nwsc/m1 squares 40 40 60 calma 48 0 - layer CCA ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 + layer CCA ndc/m1,nsc/m1 squares 20 40 60 calma 48 0 - layer CCA pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 + layer CCA pdc/m1,psc/m1 squares 20 40 60 calma 48 0 - layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a - labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a + labels poly,pres,rp,nfet,pfet,fet,pc/a calma 46 0 - layer CCP pc/m1,pm12c/m1 + layer CCP pc/m1 squares 20 40 60 calma 47 0 @@ -543,7 +440,7 @@ style lambda=0.20(p) squares 0 40 60 calma 25 0 - layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + layer CV1 m2c/m1 squares 20 40 60 calma 50 0 @@ -551,7 +448,7 @@ style lambda=0.20(p) squares 0 40 60 calma 50 0 - layer CV2 m3c/m2,m123c/m2,m234c/m2 + layer CV2 m3c/m2 squares 20 40 60 calma 61 0 @@ -559,7 +456,7 @@ style lambda=0.20(p) squares 0 40 60 calma 61 0 - layer CV3 m4c/m3,m234c/m3 + layer CV3 m4c/m3 squares 20 40 60 calma 30 0 @@ -601,12 +498,12 @@ style lambda=0.20(p) layer CM1 pad calma 49 0 - layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 - labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 calma 49 0 - layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 - labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p @@ -676,16 +573,16 @@ style lambda=0.20(p) labels fm3 calma 62 0 - layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 - labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 + labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 - layer CM4 m4,rm4,m4c/m4,m234c/m4 - labels m4,rm4,m4c/m4,m234c/m4 + layer CM4 m4,rm4,m4c/m4 + labels m4,rm4,m4c/m4 calma 31 0 layer CMQP m4p @@ -781,7 +678,7 @@ style fapm-boxes # this output style creates fill boxes automatically (to meet minimum # density requirements for poly and metal layers) 5 microns outside of -# drawn layout IF: 1. you have a flattened version of your chip, +# drawn layout IF: 1. you have a flattened version of your chip # 2. over which you paint the special fill layer 'fa', preferably with # a size that is a multiple of 10 + n * (10 + 4), 3. set 'cif # ostype fapm-boxes' and cif out to a file (this actually creates the @@ -794,11 +691,11 @@ style fapm-boxes scalefactor 20 10 - templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a - or fm1,m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 - or fm2,m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 - or fm3,m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 - or fm4,m4,rm4,m4c/m4,m234c/m4 + templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a + or fm1,m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2 + or fm3,m3,rm3,m3c/m3,m4c/m3,m4c/m3 + or fm4,m4,rm4,m4c/m4 or glass,pad grow 500 and fa @@ -820,11 +717,11 @@ style fapm-stripes # and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box # to be a 1-lambda wide layer 'fb' box -- else you won't get strips! - templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a - or fm1,m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 - or fm2,m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 - or fm3,m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 - or fm4,m4,rm4,m4c/m4,m234c/m4 + templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a + or fm1,m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2 + or fm3,m3,rm3,m3c/m3,m4c/m3,m4c/m3 + or fm4,m4,rm4,m4c/m4 or glass,pad grow 500 and fa @@ -849,8 +746,8 @@ style lambda=0.20(cp) scalefactor 20 10 layer CWN nwell,rnw,nwr,nwsd,nwsc - bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 - bloat-or nsd,nsc/a,nsm12c/a * 60 + bloat-or pdiff,apres,rpd,pdc/a,pfet * 120 + bloat-or nsd,nsc/a * 60 bloat-or nfi * 80 grow 60 shrink 60 @@ -891,8 +788,8 @@ style lambda=0.20(cp) calma 93 0 layer CWP pwell - bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a,nfet * 120 - bloat-or psd,psc/a,psm12c/a * 60 + bloat-or ndiff,anres,rnd,ndc/a,nfet * 120 + bloat-or psd,psc/a * 60 bloat-or pfi * 80 grow 60 shrink 60 @@ -914,17 +811,17 @@ style lambda=0.20(cp) #diffusion auto-nselect (will have priority) templayer XDN - bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 + bloat-or ndiff,anres,rnd,ndc/a * 40 psd,psc/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP - bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 + bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0 or TPS #final pselect templayer FSP - bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN @@ -936,7 +833,7 @@ style lambda=0.20(cp) #final nselect templayer FSN - bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 40 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 and-not nwr or XDN #never conflict with final pselect @@ -954,27 +851,27 @@ style lambda=0.20(cp) layer CSP FSP calma 44 0 - layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet - labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 - layer CCC nwsc/m1,nwsm12c/m1 + layer CCC nwsc/m1 squares 40 40 60 calma 25 0 - layer CCC ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 + layer CCC ndc/m1,nsc/m1 squares 20 40 60 calma 25 0 - layer CCC pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 + layer CCC pdc/m1,psc/m1 squares 20 40 60 calma 25 0 - layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a - labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a + labels poly,pres,rp,nfet,pfet,fet,pc/a calma 46 0 - layer CCC pc/m1,pm12c/m1 + layer CCC pc/m1 squares 20 40 60 calma 25 0 @@ -982,7 +879,7 @@ style lambda=0.20(cp) squares 0 40 60 calma 25 0 - layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + layer CV1 m2c/m1 squares 20 40 60 calma 50 0 @@ -990,7 +887,7 @@ style lambda=0.20(cp) squares 0 40 60 calma 50 0 - layer CV2 m3c/m2,m123c/m2,m234c/m2 + layer CV2 m3c/m2 squares 20 40 60 calma 61 0 @@ -998,7 +895,7 @@ style lambda=0.20(cp) squares 0 40 60 calma 61 0 - layer CV3 m4c/m3,m234c/m3 + layer CV3 m4c/m3 squares 20 40 60 calma 30 0 @@ -1040,12 +937,12 @@ style lambda=0.20(cp) layer CM1 pad calma 49 0 - layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 - labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 calma 49 0 - layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 - labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p @@ -1115,16 +1012,16 @@ style lambda=0.20(cp) labels fm3 calma 62 0 - layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 - labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 + labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 - layer CM4 m4,rm4,m4c/m4,m234c/m4 - labels m4,rm4,m4c/m4,m234c/m4 + layer CM4 m4,rm4,m4c/m4 + labels m4,rm4,m4c/m4 calma 31 0 layer CMQP m4p @@ -1196,8 +1093,8 @@ style lambda=0.20(c) scalefactor 20 10 layer CWN nwell,rnw,nwr,nwsd,nwsc - bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 - bloat-or nsd,nsc/a,nsm12c/a * 60 + bloat-or pdiff,apres,rpd,pdc/a,pfet * 120 + bloat-or nsd,nsc/a * 60 bloat-or nfi * 80 grow 60 shrink 60 @@ -1251,17 +1148,17 @@ style lambda=0.20(c) #diffusion auto-nselect (will have priority) templayer XDN - bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 + bloat-or ndiff,anres,rnd,ndc/a * 40 psd,psc/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP - bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 + bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0 or TPS #final pselect templayer FSP - bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN @@ -1273,7 +1170,7 @@ style lambda=0.20(c) #final nselect templayer FSN - bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 40 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 and-not nwr or XDN #never conflict with final pselect @@ -1291,27 +1188,27 @@ style lambda=0.20(c) layer CSP FSP calma 44 0 - layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet - labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 - layer CCC nwsc/m1,nwsm12c/m1 + layer CCC nwsc/m1 squares 40 40 60 calma 25 0 - layer CCC ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 + layer CCC ndc/m1,nsc/m1 squares 20 40 60 calma 25 0 - layer CCC pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 + layer CCC pdc/m1,psc/m1 squares 20 40 60 calma 25 0 - layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a - labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a + labels poly,pres,rp,nfet,pfet,fet,pc/a calma 46 0 - layer CCC pc/m1,pm12c/m1 + layer CCC pc/m1 squares 20 40 60 calma 25 0 @@ -1319,7 +1216,7 @@ style lambda=0.20(c) squares 0 40 60 calma 25 0 - layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + layer CV1 m2c/m1 squares 20 40 60 calma 50 0 @@ -1327,7 +1224,7 @@ style lambda=0.20(c) squares 0 40 60 calma 50 0 - layer CV2 m3c/m2,m123c/m2,m234c/m2 + layer CV2 m3c/m2 squares 20 40 60 calma 61 0 @@ -1335,7 +1232,7 @@ style lambda=0.20(c) squares 0 40 60 calma 61 0 - layer CV3 m4c/m3,m234c/m3 + layer CV3 m4c/m3 squares 20 40 60 calma 30 0 @@ -1377,12 +1274,12 @@ style lambda=0.20(c) layer CM1 pad calma 49 0 - layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 - labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 calma 49 0 - layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 - labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p @@ -1452,16 +1349,16 @@ style lambda=0.20(c) labels fm3 calma 62 0 - layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 - labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 + labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 - layer CM4 m4,rm4,m4c/m4,m234c/m4 - labels m4,rm4,m4c/m4,m234c/m4 + layer CM4 m4,rm4,m4c/m4 + labels m4,rm4,m4c/m4 calma 31 0 layer CMQP m4p @@ -1533,8 +1430,8 @@ style lambda=0.20() scalefactor 20 10 layer CWN nwell,rnw,nwr,nwsd,nwsc - bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a,pfet * 120 - bloat-or nsd,nsc/a,nsm12c/a * 60 + bloat-or pdiff,apres,rpd,pdc/a,pfet * 120 + bloat-or nsd,nsc/a * 60 bloat-or nfi * 80 grow 60 shrink 60 @@ -1588,17 +1485,17 @@ style lambda=0.20() #diffusion auto-nselect (will have priority) templayer XDN - bloat-or ndiff,anres,rnd,ndc/a,ndm12c/a * 40 psd,psc/a,psm12c/a 0 + bloat-or ndiff,anres,rnd,ndc/a * 40 psd,psc/a 0 or TNS #diffusion auto-pselect (will have priority) templayer XDP - bloat-or pdiff,apres,rpd,pdc/a,pdm12c/a * 40 nsd,nsc/a,nsm12c/a 0 + bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0 or TPS #final pselect templayer FSP - bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet * 40 ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a,nfet 0 + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 or XDP #give diff nselect priority and-not XDN @@ -1610,7 +1507,7 @@ style lambda=0.20() #final nselect templayer FSN - bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,nfet * 40 pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a,pfet 0 + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 40 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 and-not nwr or XDN #never conflict with final pselect @@ -1628,27 +1525,27 @@ style lambda=0.20() layer CSP FSP calma 44 0 - layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet - labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,pfet,pfet,fet + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet calma 43 0 - layer CCA nwsc/m1,nwsm12c/m1 + layer CCA nwsc/m1 squares 40 40 60 calma 48 0 - layer CCA ndc/m1,ndm12c/m1,nsc/m1,nsm12c/m1 + layer CCA ndc/m1,nsc/m1 squares 20 40 60 calma 48 0 - layer CCA pdc/m1,pdm12c/m1,psc/m1,psm12c/m1 + layer CCA pdc/m1,psc/m1 squares 20 40 60 calma 48 0 - layer CPG poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a - labels poly,pres,rp,nfet,pfet,fet,pc/a,pm12c/a + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a + labels poly,pres,rp,nfet,pfet,fet,pc/a calma 46 0 - layer CCP pc/m1,pm12c/m1 + layer CCP pc/m1 squares 20 40 60 calma 47 0 @@ -1656,7 +1553,7 @@ style lambda=0.20() squares 0 40 60 calma 25 0 - layer CV1 m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + layer CV1 m2c/m1 squares 20 40 60 calma 50 0 @@ -1664,7 +1561,7 @@ style lambda=0.20() squares 0 40 60 calma 50 0 - layer CV2 m3c/m2,m123c/m2,m234c/m2 + layer CV2 m3c/m2 squares 20 40 60 calma 61 0 @@ -1672,7 +1569,7 @@ style lambda=0.20() squares 0 40 60 calma 61 0 - layer CV3 m4c/m3,m234c/m3 + layer CV3 m4c/m3 squares 20 40 60 calma 30 0 @@ -1714,12 +1611,12 @@ style lambda=0.20() layer CM1 pad calma 49 0 - layer CM1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 - labels m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 + layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 calma 49 0 - layer CM2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 - labels m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 calma 51 0 layer CMFP m1p @@ -1789,16 +1686,16 @@ style lambda=0.20() labels fm3 calma 62 0 - layer CM3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 - labels m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3,m234c/m3,m4c/m3,m234c/m3 + layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 + labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 calma 62 0 layer CMTP m3p labels m3p calma 83 0 - layer CM4 m4,rm4,m4c/m4,m234c/m4 - labels m4,rm4,m4c/m4,m234c/m4 + layer CM4 m4,rm4,m4c/m4 + labels m4,rm4,m4c/m4 calma 31 0 layer CMQP m4p @@ -1872,6 +1769,11 @@ cifinput style lambda=0.20(p) scalefactor 20 + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma 63 0 + layer nwell CWN and-not CWNR and-not CTA @@ -2096,10 +1998,9 @@ style lambda=0.20(p) layer ndc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA - + and-not CWN and CM1 grow 20 @@ -2110,10 +2011,9 @@ style lambda=0.20(p) layer ndc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA - + and-not CWN and CM1 grow 20 @@ -2124,10 +2024,9 @@ style lambda=0.20(p) layer nsc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA - + and CWN and CM1 grow 20 @@ -2138,10 +2037,9 @@ style lambda=0.20(p) layer nsc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA - + and CWN and CM1 grow 20 @@ -2151,12 +2049,11 @@ style lambda=0.20(p) layer nwsc CAA and CSN - and-not CV1 and CWNR shrink 100 and-not CTA and CCA - + and CWN and CM1 grow 40 @@ -2166,12 +2063,11 @@ style lambda=0.20(p) layer nwsc CAA and CSN - and-not CV1 and CWNR shrink 105 and-not CTA and CCC - + and CWN and CM1 grow 40 @@ -2182,9 +2078,8 @@ style lambda=0.20(p) layer pdc CAA and CSP and CCA - and-not CV1 and-not CTA - + and-not CPS and CWN and CM1 @@ -2196,9 +2091,8 @@ style lambda=0.20(p) layer pdc CAA and CSP and CCC - and-not CV1 and-not CTA - + and-not CPS and CWN and CM1 @@ -2210,9 +2104,8 @@ style lambda=0.20(p) layer psc CAA and CSP and CCA - and-not CV1 and-not CTA - + and-not CPS and-not CWN and CM1 @@ -2224,173 +2117,9 @@ style lambda=0.20(p) layer psc CAA and CSP and CCC - and-not CV1 and-not CWNR and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer nwsc CAA - and CSN - and CV1 - and CV2 - and-not CV3 - and CWNR - shrink 100 - and-not CTA - and CCA - - and CWN - and CM1 - grow 40 - grow 10 - shrink 10 - calma CCA 48 * - - layer nwsc CAA - and CSN - and CV1 - and CV2 - and-not CV3 - and CWNR - shrink 105 - and-not CTA - and CCC - - and CWN - and CM1 - grow 40 - grow 10 - shrink 10 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - and-not CPS and-not CWN and CM1 @@ -2418,7 +2147,6 @@ style lambda=0.20(p) calma CRG 67 * layer pc CCP - and-not CV1 and CPG and-not CPC and-not CEL @@ -2430,35 +2158,6 @@ style lambda=0.20(p) calma CCP 47 * layer pc CCC - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 20 - and CM1 - grow 10 - shrink 10 - calma CCC 25 * - - layer pc CCP - and CV1 - and CV2 - and-not CV3 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 20 - and CM1 - grow 10 - shrink 10 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and-not CV3 and CPG and-not CPC and-not CEL @@ -2543,10 +2242,6 @@ style lambda=0.20(p) calma CV3 30 * layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCP - and-not CCA and-not XP grow 20 and CM2 @@ -2555,65 +2250,7 @@ style lambda=0.20(p) shrink 10 calma CV1 50 * - layer m2c CV1 - and CV2 - and CV3 - and-not CCC - and-not CCP - and-not CCA - and-not XP - grow 20 - and CM2 - and CM1 - grow 10 - shrink 10 - calma CV1 50 * - layer pm12c CV1 - and-not CV2 - and CCP - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and-not CV2 - and CCC - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and CV2 - and CV3 - and CCP - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and CV2 - and CV3 - and CCC - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * layer m1 CM1 and-not CRM @@ -2661,325 +2298,25 @@ style lambda=0.20(p) labels CMSP calma CMSP 82 * - layer ndm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and-not CV2 - and CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and-not CV2 - and CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * layer fp 100 calma 100 100 * @@ -3006,8 +2343,6 @@ style lambda=0.20(p) calma 110 110 * layer m3c CV2 - and-not CV3 - and-not CV1 and-not XP grow 20 and CM3 @@ -3016,17 +2351,6 @@ style lambda=0.20(p) shrink 10 calma CV2 61 * - layer m123c CV2 - and-not CV3 - and CV1 - and-not XP - grow 20 - and CM3 - and CM2 - and CM1 - grow 10 - shrink 10 - calma CV2 61 * layer m3 CM3 and-not CRM @@ -3051,17 +2375,6 @@ style lambda=0.20(p) labels CMTP calma CMTP 83 * - layer m234c CV3 - - and CV2 - and-not XP - grow 20 - and CM4 - and CM3 - and CM2 - grow 20 - shrink 20 - calma CV3 30 * layer m4 CM4 and-not CRM @@ -3087,8 +2400,6 @@ style lambda=0.20(p) calma CMQP 84 * layer m4c CV3 - - and-not CV2 and-not XP grow 20 and CM4 @@ -3155,7 +2466,6 @@ style lambda=0.20(p) calma CTA 60 * -#CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * @@ -3395,10 +2705,9 @@ style lambda=0.20(s) layer ndc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA - + and-not CWN and CM1 grow 20 @@ -3409,10 +2718,9 @@ style lambda=0.20(s) layer ndc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA - + and-not CWN and CM1 grow 20 @@ -3423,10 +2731,9 @@ style lambda=0.20(s) layer nsc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA - + and CWN and CM1 grow 20 @@ -3437,10 +2744,9 @@ style lambda=0.20(s) layer nsc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA - + and CWN and CM1 grow 20 @@ -3450,12 +2756,11 @@ style lambda=0.20(s) layer nwsc CAA and CSN - and-not CV1 and CWNR shrink 100 and-not CTA and CCA - + and CWN and CM1 grow 40 @@ -3465,12 +2770,11 @@ style lambda=0.20(s) layer nwsc CAA and CSN - and-not CV1 and CWNR shrink 105 and-not CTA and CCC - + and CWN and CM1 grow 40 @@ -3481,9 +2785,8 @@ style lambda=0.20(s) layer pdc CAA and CSP and CCA - and-not CV1 and-not CTA - + and-not CPS and CWN and CM1 @@ -3495,9 +2798,8 @@ style lambda=0.20(s) layer pdc CAA and CSP and CCC - and-not CV1 and-not CTA - + and-not CPS and CWN and CM1 @@ -3509,9 +2811,8 @@ style lambda=0.20(s) layer psc CAA and CSP and CCA - and-not CV1 and-not CTA - + and-not CPS and-not CWN and CM1 @@ -3523,173 +2824,9 @@ style lambda=0.20(s) layer psc CAA and CSP and CCC - and-not CV1 and-not CWNR and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer nwsc CAA - and CSN - and CV1 - and CV2 - and-not CV3 - and CWNR - shrink 100 - and-not CTA - and CCA - - and CWN - and CM1 - grow 40 - grow 10 - shrink 10 - calma CCA 48 * - - layer nwsc CAA - and CSN - and CV1 - and CV2 - and-not CV3 - and CWNR - shrink 105 - and-not CTA - and CCC - - and CWN - and CM1 - grow 40 - grow 10 - shrink 10 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - and-not CPS and-not CWN and CM1 @@ -3717,7 +2854,6 @@ style lambda=0.20(s) calma CRG 67 * layer pc CCP - and-not CV1 and CPG and-not CPC and-not CEL @@ -3729,35 +2865,6 @@ style lambda=0.20(s) calma CCP 47 * layer pc CCC - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 20 - and CM1 - grow 10 - shrink 10 - calma CCC 25 * - - layer pc CCP - and CV1 - and CV2 - and-not CV3 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 20 - and CM1 - grow 10 - shrink 10 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and-not CV3 and CPG and-not CPC and-not CEL @@ -3842,10 +2949,6 @@ style lambda=0.20(s) calma CV3 30 * layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCP - and-not CCA and-not XP grow 20 and CM2 @@ -3854,65 +2957,8 @@ style lambda=0.20(s) shrink 10 calma CV1 50 * - layer m2c CV1 - and CV2 - and CV3 - and-not CCC - and-not CCP - and-not CCA - and-not XP - grow 20 - and CM2 - and CM1 - grow 10 - shrink 10 - calma CV1 50 * - layer pm12c CV1 - and-not CV2 - and CCP - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - layer pm12c CV1 - and-not CV2 - and CCC - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and CV2 - and CV3 - and CCP - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and CV2 - and CV3 - and CCC - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * layer m1 CM1 and-not CRM @@ -3960,325 +3006,25 @@ style lambda=0.20(s) labels CMSP calma CMSP 82 * - layer ndm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and-not CV2 - and CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and-not CV2 - and CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * layer fp 100 calma 100 100 * @@ -4305,8 +3051,6 @@ style lambda=0.20(s) calma 110 110 * layer m3c CV2 - and-not CV3 - and-not CV1 and-not XP grow 20 and CM3 @@ -4315,17 +3059,6 @@ style lambda=0.20(s) shrink 10 calma CV2 61 * - layer m123c CV2 - and-not CV3 - and CV1 - and-not XP - grow 20 - and CM3 - and CM2 - and CM1 - grow 10 - shrink 10 - calma CV2 61 * layer m3 CM3 and-not CRM @@ -4350,17 +3083,6 @@ style lambda=0.20(s) labels CMTP calma CMTP 83 * - layer m234c CV3 - - and CV2 - and-not XP - grow 20 - and CM4 - and CM3 - and CM2 - grow 20 - shrink 20 - calma CV3 30 * layer m4 CM4 and-not CRM @@ -4386,8 +3108,6 @@ style lambda=0.20(s) calma CMQP 84 * layer m4c CV3 - - and-not CV2 and-not XP grow 20 and CM4 @@ -4454,7 +3174,6 @@ style lambda=0.20(s) calma CTA 60 * -#CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * @@ -4695,10 +3414,9 @@ style lambda=0.20(ps) layer ndc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA - + and-not CWN and CM1 grow 20 @@ -4709,10 +3427,9 @@ style lambda=0.20(ps) layer ndc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA - + and-not CWN and CM1 grow 20 @@ -4723,10 +3440,9 @@ style lambda=0.20(ps) layer nsc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA - + and CWN and CM1 grow 20 @@ -4737,10 +3453,9 @@ style lambda=0.20(ps) layer nsc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA - + and CWN and CM1 grow 20 @@ -4750,12 +3465,11 @@ style lambda=0.20(ps) layer nwsc CAA and CSN - and-not CV1 and CWNR shrink 100 and-not CTA and CCA - + and CWN and CM1 grow 40 @@ -4765,12 +3479,11 @@ style lambda=0.20(ps) layer nwsc CAA and CSN - and-not CV1 and CWNR shrink 105 and-not CTA and CCC - + and CWN and CM1 grow 40 @@ -4781,9 +3494,8 @@ style lambda=0.20(ps) layer pdc CAA and CSP and CCA - and-not CV1 and-not CTA - + and-not CPS and CWN and CM1 @@ -4795,9 +3507,8 @@ style lambda=0.20(ps) layer pdc CAA and CSP and CCC - and-not CV1 and-not CTA - + and-not CPS and CWN and CM1 @@ -4809,9 +3520,8 @@ style lambda=0.20(ps) layer psc CAA and CSP and CCA - and-not CV1 and-not CTA - + and-not CPS and-not CWN and CM1 @@ -4823,173 +3533,9 @@ style lambda=0.20(ps) layer psc CAA and CSP and CCC - and-not CV1 and-not CWNR and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer nwsc CAA - and CSN - and CV1 - and CV2 - and-not CV3 - and CWNR - shrink 100 - and-not CTA - and CCA - - and CWN - and CM1 - grow 40 - grow 10 - shrink 10 - calma CCA 48 * - - layer nwsc CAA - and CSN - and CV1 - and CV2 - and-not CV3 - and CWNR - shrink 105 - and-not CTA - and CCC - - and CWN - and CM1 - grow 40 - grow 10 - shrink 10 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - and-not CPS and-not CWN and CM1 @@ -5017,7 +3563,6 @@ style lambda=0.20(ps) calma CRG 67 * layer pc CCP - and-not CV1 and CPG and-not CPC and-not CEL @@ -5029,35 +3574,6 @@ style lambda=0.20(ps) calma CCP 47 * layer pc CCC - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 20 - and CM1 - grow 10 - shrink 10 - calma CCC 25 * - - layer pc CCP - and CV1 - and CV2 - and-not CV3 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 20 - and CM1 - grow 10 - shrink 10 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and-not CV3 and CPG and-not CPC and-not CEL @@ -5142,10 +3658,6 @@ style lambda=0.20(ps) calma CV3 30 * layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCP - and-not CCA and-not XP grow 20 and CM2 @@ -5154,65 +3666,8 @@ style lambda=0.20(ps) shrink 10 calma CV1 50 * - layer m2c CV1 - and CV2 - and CV3 - and-not CCC - and-not CCP - and-not CCA - and-not XP - grow 20 - and CM2 - and CM1 - grow 10 - shrink 10 - calma CV1 50 * - layer pm12c CV1 - and-not CV2 - and CCP - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - layer pm12c CV1 - and-not CV2 - and CCC - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and CV2 - and CV3 - and CCP - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and CV2 - and CV3 - and CCC - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * layer m1 CM1 and-not CRM @@ -5260,325 +3715,25 @@ style lambda=0.20(ps) labels CMSP calma CMSP 82 * - layer ndm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and-not CV2 - and CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and-not CV2 - and CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * layer fp 100 calma 100 100 * @@ -5605,89 +3760,6 @@ style lambda=0.20(ps) calma 110 110 * layer m3c CV2 - and-not CV3 - and-not CV1 - and-not XP - grow 20 - and CM3 - and CM2 - grow 10 - shrink 10 - calma CV2 61 * - - layer m123c CV2 - and-not CV3 - and CV1 - and-not XP - grow 20 - and CM3 - and CM2 - and CM1 - grow 10 - shrink 10 - calma CV2 61 * - - layer m3 CM3 - and-not CRM - and-not CRT - and-not XP - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer m234c CV3 - - and CV2 - and-not XP - grow 20 - and CM4 - and CM3 - and CM2 - grow 20 - shrink 20 - calma CV3 30 * - - layer m4 CM4 - and-not CRM - and-not CRQ - and-not XP - labels CM4 - calma CM4 31 * - - layer rm4 CRM - and CM4 - calma CRM 70 * - - layer rm4 CRQ - and CM4 - calma CRQ 74 * - - layer pseudo_rmetal4 CRQ - and-not rm4 - calma CRQ 74 * - - layer m4p CMQP - labels CMQP - calma CMQP 84 * - - layer m4c CV3 - - and-not CV2 and-not XP grow 20 and CM4 @@ -5754,7 +3826,6 @@ style lambda=0.20(ps) calma CTA 60 * -#CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * @@ -5992,10 +4063,9 @@ style lambda=0.20() layer ndc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA - + and-not CWN and CM1 grow 20 @@ -6006,10 +4076,9 @@ style lambda=0.20() layer ndc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA - + and-not CWN and CM1 grow 20 @@ -6020,10 +4089,9 @@ style lambda=0.20() layer nsc CAA and CSN and CCA - and-not CV1 and-not CWNR and-not CTA - + and CWN and CM1 grow 20 @@ -6034,10 +4102,9 @@ style lambda=0.20() layer nsc CAA and CSN and CCC - and-not CV1 and-not CWNR and-not CTA - + and CWN and CM1 grow 20 @@ -6047,12 +4114,11 @@ style lambda=0.20() layer nwsc CAA and CSN - and-not CV1 and CWNR shrink 100 and-not CTA and CCA - + and CWN and CM1 grow 40 @@ -6062,12 +4128,11 @@ style lambda=0.20() layer nwsc CAA and CSN - and-not CV1 and CWNR shrink 105 and-not CTA and CCC - + and CWN and CM1 grow 40 @@ -6078,9 +4143,8 @@ style lambda=0.20() layer pdc CAA and CSP and CCA - and-not CV1 and-not CTA - + and-not CPS and CWN and CM1 @@ -6092,9 +4156,8 @@ style lambda=0.20() layer pdc CAA and CSP and CCC - and-not CV1 and-not CTA - + and-not CPS and CWN and CM1 @@ -6106,9 +4169,8 @@ style lambda=0.20() layer psc CAA and CSP and CCA - and-not CV1 and-not CTA - + and-not CPS and-not CWN and CM1 @@ -6120,173 +4182,9 @@ style lambda=0.20() layer psc CAA and CSP and CCC - and-not CV1 and-not CWNR and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer nwsc CAA - and CSN - and CV1 - and CV2 - and-not CV3 - and CWNR - shrink 100 - and-not CTA - and CCA - - and CWN - and CM1 - grow 40 - grow 10 - shrink 10 - calma CCA 48 * - - layer nwsc CAA - and CSN - and CV1 - and CV2 - and-not CV3 - and CWNR - shrink 105 - and-not CTA - and CCC - - and CWN - and CM1 - grow 40 - grow 10 - shrink 10 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CV3 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 20 - grow 10 - shrink 10 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CV3 - and-not CWNR - and-not CTA - and-not CPS and-not CWN and CM1 @@ -6314,7 +4212,6 @@ style lambda=0.20() calma CRG 67 * layer pc CCP - and-not CV1 and CPG and-not CPC and-not CEL @@ -6326,35 +4223,6 @@ style lambda=0.20() calma CCP 47 * layer pc CCC - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 20 - and CM1 - grow 10 - shrink 10 - calma CCC 25 * - - layer pc CCP - and CV1 - and CV2 - and-not CV3 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 20 - and CM1 - grow 10 - shrink 10 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and-not CV3 and CPG and-not CPC and-not CEL @@ -6439,10 +4307,6 @@ style lambda=0.20() calma CV3 30 * layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCP - and-not CCA and-not XP grow 20 and CM2 @@ -6451,65 +4315,8 @@ style lambda=0.20() shrink 10 calma CV1 50 * - layer m2c CV1 - and CV2 - and CV3 - and-not CCC - and-not CCP - and-not CCA - and-not XP - grow 20 - and CM2 - and CM1 - grow 10 - shrink 10 - calma CV1 50 * - layer pm12c CV1 - and-not CV2 - and CCP - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - layer pm12c CV1 - and-not CV2 - and CCC - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and CV2 - and CV3 - and CCP - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * - - layer pm12c CV1 - and CV2 - and CV3 - and CCC - grow 20 - and CM2 - and CM1 - and CPG - grow 10 - shrink 10 - calma CV1 50 * layer m1 CM1 and-not CRM @@ -6557,325 +4364,25 @@ style lambda=0.20() labels CMSP calma CMSP 82 * - layer ndm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and-not CV2 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and-not CV2 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and-not CV2 - and CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and-not CV2 - and CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer ndm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer pdm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and-not CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer psm12c CAA - and CSP - and CV1 - and CV2 - and CV3 - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and-not CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and CWNR - and-not CTA - and CCA - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * - layer nwsm12c CAA - and CSN - and CV1 - and CV2 - and CV3 - and CWNR - and-not CTA - and CCC - grow 20 - and CM1 - and CM2 - - and CWN - grow 10 - shrink 10 - calma CV1 50 * layer fp 100 calma 100 100 * @@ -6902,8 +4409,6 @@ style lambda=0.20() calma 110 110 * layer m3c CV2 - and-not CV3 - and-not CV1 and-not XP grow 20 and CM3 @@ -6912,17 +4417,6 @@ style lambda=0.20() shrink 10 calma CV2 61 * - layer m123c CV2 - and-not CV3 - and CV1 - and-not XP - grow 20 - and CM3 - and CM2 - and CM1 - grow 10 - shrink 10 - calma CV2 61 * layer m3 CM3 and-not CRM @@ -6947,17 +4441,6 @@ style lambda=0.20() labels CMTP calma CMTP 83 * - layer m234c CV3 - - and CV2 - and-not XP - grow 20 - and CM4 - and CM3 - and CM2 - grow 20 - shrink 20 - calma CV3 30 * layer m4 CM4 and-not CRM @@ -6983,8 +4466,6 @@ style lambda=0.20() calma CMQP 84 * layer m4c CV3 - - and-not CV2 and-not XP grow 20 and CM4 @@ -7051,7 +4532,6 @@ style lambda=0.20() calma CTA 60 * -#CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * @@ -7525,7 +5005,6 @@ style lambda=0.20(c) calma CTA 60 * -#CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * @@ -8001,7 +5480,6 @@ style lambda=0.20(cs) calma CTA 60 * -#CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * @@ -8478,7 +5956,6 @@ style lambda=0.20(cps) calma CTA 60 * -#CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * @@ -8953,7 +6430,6 @@ style lambda=0.20(cp) calma CTA 60 * -#CRE/CRM calma CRW 65 * calma CRG 67 * calma CRD 66 * @@ -9029,22 +6505,22 @@ drc width pwell 12 \ "P-well width < 12 (Mosis #1.1)" - width diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 \ + width diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 3 \ "Diffusion width < 3 (Mosis #2.1)" - edge4way nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a pdiff,apres,rpd,pdc/a,pdm12c/a 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active pdiff,apres,rpd,pdc/a,pdm12c/a 3 \ + edge4way nsd,nwsd,nsc/a,nwsc/a pdiff,apres,rpd,pdc/a 3 ~(nsd,nwsd,nsc/a,nwsc/a)/active pdiff,apres,rpd,pdc/a 3 \ "P-Diffusion width in N-Ohmic < 3 (Mosis #2.1)" active - edge4way psd,psc/a,psm12c/a ndiff,anres,rnd,ndc/a,ndm12c/a 3 ~(psd,psc/a,psm12c/a)/active ndiff,anres,rnd,ndc/a,ndm12c/a 3 \ + edge4way psd,psc/a ndiff,anres,rnd,ndc/a 3 ~(psd,psc/a)/active ndiff,anres,rnd,ndc/a 3 \ "N-Diffusion width in P-Ohmic < 3 (Mosis #2.1)" active - edge4way pdiff,apres,rpd,pdc/a,pdm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 ~(pdiff,apres,rpd,pdc/a,pdm12c/a)/active nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 \ + edge4way pdiff,apres,rpd,pdc/a nsd,nwsd,nsc/a,nwsc/a 3 ~(pdiff,apres,rpd,pdc/a)/active nsd,nwsd,nsc/a,nwsc/a 3 \ "N-Ohmic width in P-Diffusion < 3 (Mosis #2.1)" active - edge4way ndiff,anres,rnd,ndc/a,ndm12c/a psd,psc/a,psm12c/a 3 ~(ndiff,anres,rnd,ndc/a,ndm12c/a)/active psd,psc/a,psm12c/a 3 \ + edge4way ndiff,anres,rnd,ndc/a psd,psc/a 3 ~(ndiff,anres,rnd,ndc/a)/active psd,psc/a 3 \ "P-Ohmic width in N-Diffusion < 3 (Mosis #2.1)" active - width poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet,fet 2 \ + width poly,fp,pres,rp,pc/a,nfet,pfet,fet 2 \ "Poly width < 2 (Mosis #3.1)" width nselect 3 \ @@ -9053,17 +6529,15 @@ drc width pselect 3 \ "P-Select width < 3 (Mosis #4.4)" - width ndiff,anres,rnd,ndc/a,ndm12c/a,nsd,nsc/a,nsm12c/a 3 \ + width ndiff,anres,rnd,ndc/a,nsd,nsc/a 3 \ "N-Diffusion,N-Ohmic width < 3 (Mosis #4.4)" - width pdiff,apres,rpd,pdc/a,pdm12c/a,psd,psc/a,psm12c/a 3 \ + width pdiff,apres,rpd,pdc/a,psd,psc/a 3 \ "P-Diffusion,P-Ohmic width < 3 (Mosis #4.4)" width pc/m1 4 \ "Poly contact width < 4 (Mosis #5.1)" - width pm12c/m1 4 \ - "Poly contact width < 4 (Mosis #5.1)" width gc 2 \ "GC contact width < 2 (Mosis #6.1)" @@ -9071,8 +6545,6 @@ drc width ndc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" - width ndm12c/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" width nsc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" @@ -9080,11 +6552,7 @@ drc width nwsc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" - width nsm12c/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" - width nwsm12c/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" width nwsc 6 \ "nwr (for Fig1b resistor) active Contact width < 6 (Mosis #Fig1b)" @@ -9092,16 +6560,12 @@ drc width pdc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" - width pdm12c/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" width psc/m1 4 \ "Diffusion contact width < 4 (Mosis #6.1)" - width psm12c/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" - width m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 3 \ + width m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 \ "Metal1 width < 3 (Mosis #7.1)" width gv1 2 \ @@ -9110,28 +6574,14 @@ drc width m2c/m1 4 \ "Metal2 contact width < 4 (Mosis #8.1)" - width pdm12c/m1 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - width ndm12c/m1 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - width psm12c/m1 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - width nsm12c/m1 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - width pm12c/m1 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - width m123c/m1 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - width nwsm12c/m1 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - width m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 3 \ + width m2,fm2,rm2,m2c/m2,m3c/m2 3 \ "Metal2 width < 3 (Mosis #9.1)" width gv2 2 \ @@ -9140,13 +6590,9 @@ drc width m3c/m2 4 \ "Metal3 contact width < 4 (Mosis #14.1)" - width m123c/m2 4 \ - "Metal3 contact width < 4 (Mosis #14.1)" - width m234c/m2 4 \ - "Metal3 contact width < 4 (Mosis #14.1)" - width m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 3 \ + width m3,fm3,rm3,m3c/m3,m4c/m3 3 \ "Metal3 width < 3 (Mosis #15.1)" width sb,pres,anres,apres 4 \ @@ -9164,10 +6610,8 @@ drc width m4c/m3 4 \ "Metal4 contact width < 4 (Mosis #21.3)" - width m234c/m3 4 \ - "Metal4 contact width < 4 (Mosis #21.3)" - width m4,fm4,rm4,m4c/m4,m234c/m4,pad 3 \ + width m4,fm4,rm4,m4c/m4,pad 3 \ "Metal4 width < 3 (Mosis #22.1)" width nfi,pfi 4 \ @@ -9191,73 +6635,73 @@ drc edge4way ~(pwell)/well pwell 1 ~(nwr)/active 0 0 \ "P-well cannot touch nwr (for Fig1b resistor L/W extraction) (Mosis #1.4)" active - spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 touching_ok \ + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 3 touching_ok \ "Diffusion spacing < 3 (Mosis #2.2)" - spacing nwell ndiff,anres,rnd,nfet,ndc/a,ndm12c/a 6 touching_illegal \ + spacing nwell ndiff,anres,rnd,nfet,ndc/a 6 touching_illegal \ "N-well spacing to N-Diffusion < 6 (Mosis #2.3)" - spacing pwell pdiff,apres,rpd,pfet,pdc/a,pdm12c/a 6 touching_illegal \ + spacing pwell pdiff,apres,rpd,pfet,pdc/a 6 touching_illegal \ "P-well spacing to P-Diffusion < 6 (Mosis #2.3)" - spacing ndiff,anres,rnd,nfet,ndc/a,ndm12c/a pdiff,apres,rpd,pfet,pdc/a,pdm12c/a 12 touching_illegal \ + spacing ndiff,anres,rnd,nfet,ndc/a pdiff,apres,rpd,pfet,pdc/a 12 touching_illegal \ "N-Diffusion spacing to P-Diffusion < 12 (Mosis #2.3+2.3)" - edge4way ~(nwell)/well nwell 6 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active nwell 6 \ + edge4way ~(nwell)/well nwell 6 ~(pdiff,apres,rpd,pfet,pdc/a)/active nwell 6 \ "N-well overlap of P-Diffusion < 6 (Mosis #2.4)" active - edge4way ~(pwell)/well pwell 6 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active pwell 6 \ + edge4way ~(pwell)/well pwell 6 ~(ndiff,anres,rnd,nfet,ndc/a)/active pwell 6 \ "P-well overlap of N-Diffusion < 6 (Mosis #2.4)" active - edge4way ~(nwell)/well nwell 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active nwell 3 \ + edge4way ~(nwell)/well nwell 3 ~(nsd,nwsd,nsc/a,nwsc/a)/active nwell 3 \ "N-well overlap of N-Ohmic < 3 (Mosis #2.4)" active - edge4way ~(pwell)/well pwell 3 ~(psd,psc/a,psm12c/a)/active pwell 3 \ + edge4way ~(pwell)/well pwell 3 ~(psd,psc/a)/active pwell 3 \ "P-well overlap of P-Ohmic < 3 (Mosis #2.4)" active - spacing ndiff,anres,rnd,ndc/a,ndm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 9 touching_illegal \ + spacing ndiff,anres,rnd,ndc/a nsd,nwsd,nsc/a,nwsc/a 9 touching_illegal \ "N-Diffusion spacing to N-Ohmic < 9 (Mosis #2.3+2.4)" - spacing pdiff,apres,rpd,pdc/a,pdm12c/a psd,psc/a,psm12c/a 9 touching_illegal \ + spacing pdiff,apres,rpd,pdc/a psd,psc/a 9 touching_illegal \ "P-Diffusion spacing to P-Ohmic < 9 (Mosis #2.3+2.4)" - spacing nwell psd,psc/a,psm12c/a 3 touching_illegal \ + spacing nwell psd,psc/a 3 touching_illegal \ "N-well spacing to P-Ohmic < 3 (Mosis #2.4)" - spacing pwell nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 touching_illegal \ + spacing pwell nsd,nwsd,nsc/a,nwsc/a 3 touching_illegal \ "P-well spacing to N-Ohmic < 3 (Mosis #2.4)" - spacing psd,psc/a,psm12c/a rnw,prnw 3 touching_illegal \ + spacing psd,psc/a rnw,prnw 3 touching_illegal \ "P-Ohmic spacing to rnw,prnw < 3 (Mosis #2.4)" - spacing psd,psc/a,psm12c/a nwr,pnwr 3 touching_illegal \ + spacing psd,psc/a nwr,pnwr 3 touching_illegal \ "P-Ohmic spacing to nwr,pnwr (for Fig1b Resistor) < 3 (Mosis #2.4)" - spacing nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a psd,psc/a,psm12c/a 6 touching_illegal \ + spacing nsd,nwsd,nsc/a,nwsc/a psd,psc/a 6 touching_illegal \ "N-Ohmic spacing to P-Ohmic < 6 (Mosis #2.4+2.4)" - spacing ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nfet psd,psc/a,psm12c/a 4 touching_ok \ + spacing ndiff,anres,rnd,nfet,ndc/a,nfet psd,psc/a 4 touching_ok \ "N-Diffusion spacing to P-Ohmic < 4 (Mosis #2.5)" - spacing pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,pfet nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 4 touching_ok \ + spacing pdiff,apres,rpd,pfet,pdc/a,pfet nsd,nwsd,nsc/a,nwsc/a 4 touching_ok \ "P-Diffusion spacing to N-Ohmic < 4 (Mosis #2.5)" - spacing poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet 3 touching_ok \ + spacing poly,pres,rp,pc/a,nfet,pfet,fet poly,pres,rp,pc/a,nfet,pfet,fet 3 touching_ok \ "Poly spacing < 3 (Mosis #3.2)" - spacing poly,pres,rp,pc/a,pm12c/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ + spacing poly,pres,rp,pc/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ "Poly spacing to fill layer (fp) < 3 (Mosis #3.2)" spacing fp fp 4 touching_ok \ "Poly fill layer (fp) spacing < 4 (Mosis #0)" - edge4way nfet,pfet,fet space/active,poly,fp,pres,rp,pc/a,pm12c/a 2 poly,fp,pres,rp,pc/a,pm12c/a 0 0 \ + edge4way nfet,pfet,fet space/active,poly,fp,pres,rp,pc/a 2 poly,fp,pres,rp,pc/a 0 0 \ "Poly overhang of Transistor < 2 (Mosis #3.3)" active - edge4way nfet,pfet,fet space/active,ndiff,anres,rnd,ndc/a,ndm12c/a,pdiff,apres,rpd,pdc/a,pdm12c/a 3 ndiff,anres,rnd,ndc/a,ndm12c/a,pdiff,apres,rpd,pdc/a,pdm12c/a,nfet,pfet,fet 0 0 \ + edge4way nfet,pfet,fet space/active,ndiff,anres,rnd,ndc/a,pdiff,apres,rpd,pdc/a 3 ndiff,anres,rnd,ndc/a,pdiff,apres,rpd,pdc/a,nfet,pfet,fet 0 0 \ "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active - edge4way poly,fp,rp,pc/a,pm12c/a ~(poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet,fet,prp)/active 1 space space 1 \ + edge4way poly,fp,rp,pc/a ~(poly,fp,pres,rp,pc/a,nfet,pfet,fet,prp)/active 1 space space 1 \ "Poly spacing to Diffusion < 1 (Mosis #3.5)" edge4way nfet ~(nfet)/active 2 ~(pselect)/select ~(nfet)/active 2 \ @@ -9266,40 +6710,40 @@ drc edge4way pfet ~(pfet)/active 2 ~(nselect)/select ~(pfet)/active 2 \ "P-Transistor space to N-Select < 2 (Mosis #4.1)" select - edge4way nfet ~(nfet)/active 3 ~(psd,psc/a,psm12c/a)/active ~(nfet)/active 2 \ + edge4way nfet ~(nfet)/active 3 ~(psd,psc/a)/active ~(nfet)/active 2 \ "N-Transistor space to P-Ohmic < 3 (Mosis #4.1)" active - edge4way pfet ~(pfet)/active 3 ~(nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active ~(pfet)/active 2 \ + edge4way pfet ~(pfet)/active 3 ~(nsd,nwsd,nsc/a,nwsc/a)/active ~(pfet)/active 2 \ "P-Transistor space to N-Ohmic < 3 (Mosis #4.1)" active -#PEZ edge4way psd,psc/a,psm12c/a space ~(nfet)/active space \ +#PEZ edge4way psd,psc/a space ~(nfet)/active space \ #PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active -#PEZ edge4way nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a space ~(pfet)/active space \ +#PEZ edge4way nsd,nwsd,nsc/a,nwsc/a space ~(pfet)/active space \ #PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active - edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active nselect,pselect 2 \ + edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active nselect,pselect 2 \ "N-Select,P-Select overlap of Diffusion < 2 (Mosis #4.2_)" active - edge4way space nselect,pselect 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active nselect 2 \ + edge4way space nselect,pselect 2 ~(ndiff,anres,rnd,nfet,ndc/a)/active nselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2a)" active - edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active nselect 2 \ + edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a)/active nselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2b)" active - edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a)/active space,nselect,pselect 2 \ + edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a)/active space,nselect,pselect 2 \ "N-Select space to N-Diffusion < 2 (Mosis #4.2c)" active - edge4way space nselect,pselect 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active pselect 2 \ + edge4way space nselect,pselect 2 ~(pdiff,apres,rpd,pfet,pdc/a)/active pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2aa)" active - edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active pselect 2 \ + edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a)/active pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2bb)" active - edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a)/active space,nselect,pselect 2 \ + edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a)/active space,nselect,pselect 2 \ "P-Select space to P-Diffusion < 2 (Mosis #4.2cc)" active - area nsd,nwsd,psd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,psc/a,psm12c/a 16 3 \ + area nsd,nwsd,psd,nsc/a,nwsc/a,psc/a 16 3 \ "Ohmic-Diffusion area < 16 (Mosis #+++)" edge4way diff space 2 nselect space 2 \ @@ -9308,16 +6752,16 @@ drc edge4way diff space 2 pselect space 2 \ "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select - edge4way ndiff,anres,rnd,nfet,ndc/a,ndm12c/a space 2 ~(pselect)/select space 2 \ + edge4way ndiff,anres,rnd,nfet,ndc/a space 2 ~(pselect)/select space 2 \ "P-Select space to N-Diffusion < 2 (Mosis #4.2e)" select - edge4way pdiff,apres,rpd,pfet,pdc/a,pdm12c/a space 2 ~(nselect)/select space 2 \ + edge4way pdiff,apres,rpd,pfet,pdc/a space 2 ~(nselect)/select space 2 \ "N-Select space to P-Diffusion < 2 (Mosis #4.2e)" select - edge4way ~(pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,psd,psc/a,psm12c/a)/active pdiff,apres,rpd,pfet,pdc/a,pdm12c/a,psd,psc/a,psm12c/a 1 ~(nselect)/select 0 0 \ + edge4way ~(pdiff,apres,rpd,pfet,pdc/a,psd,psc/a)/active pdiff,apres,rpd,pfet,pdc/a,psd,psc/a 1 ~(nselect)/select 0 0 \ "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select - edge4way ~(ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active ndiff,anres,rnd,nfet,ndc/a,ndm12c/a,nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 ~(pselect)/select 0 0 \ + edge4way ~(ndiff,anres,rnd,nfet,ndc/a,nsd,nwsd,nsc/a,nwsc/a)/active ndiff,anres,rnd,nfet,ndc/a,nsd,nwsd,nsc/a,nwsc/a 1 ~(pselect)/select 0 0 \ "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select spacing nselect nselect 3 touching_ok \ @@ -9326,13 +6770,13 @@ drc spacing pselect pselect 3 touching_ok \ "P-Select spacing < 3 (Mosis #4.4)" - edge4way ndiff,anres,rnd,ndc/a,ndm12c/a psd,psc/a,psm12c/a 2 ~(ndiff,anres,rnd,ndc/a,ndm12c/a)/active 0 0 \ + edge4way ndiff,anres,rnd,ndc/a psd,psc/a 2 ~(ndiff,anres,rnd,ndc/a)/active 0 0 \ "P-Ohmic(that touches N-Diffusion) width < 2 (Mosis #4.4)" - edge4way pdiff,apres,rpd,pdc/a,pdm12c/a nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 ~(pdiff,apres,rpd,pdc/a,pdm12c/a)/active 0 0 \ + edge4way pdiff,apres,rpd,pdc/a nsd,nwsd,nsc/a,nwsc/a 2 ~(pdiff,apres,rpd,pdc/a)/active 0 0 \ "N-Ohmic(that touches P-Diffusion) width < 2 (Mosis #4.4)" - edge4way gc ~(gc)/contact 1 poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a ~(gc)/contact 1 \ + edge4way gc ~(gc)/contact 1 poly,fp,pres,rp,pc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a ~(gc)/contact 1 \ "Poly,Diffusion overlap of GC contact < 1 (Mosis #5.2)" active edge4way ~(nwsd)/active nwsd 2 ~(gc)/contact nwsd 2 \ @@ -9341,115 +6785,101 @@ drc spacing nwr gc 5 touching_illegal \ "nwr (for Fig1b resistor) spacing to GC contact < 5 (Mosis #Fig1b)" - spacing nwr ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 3 touching_illegal \ + spacing nwr ndc/a,nsc/a,nwsc/a 3 touching_illegal \ "nwr (for Fig1b resistor) spacing to Diffusion contact < 3 (Mosis #Fig1b)" - edge4way gc space 1 poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a space 1 \ + edge4way gc space 1 poly,fp,pres,rp,pc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a space 1 \ "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active - edge4way ~(poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active poly,fp,pres,rp,pc/a,pm12c/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 1 ~(gc)/contact 0 0 \ + edge4way ~(poly,fp,pres,rp,pc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active poly,fp,pres,rp,pc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 1 ~(gc)/contact 0 0 \ "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact spacing gc gc 3 touching_ok \ "Generic contact spacing < 3 (Mosis #5.3)" - edge4way ~(gc)/contact gc 1 ~(ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1)/metal1 0 0 \ + edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 - spacing gv1 m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2 2 touching_illegal \ + spacing gv1 m2c/m2 2 touching_illegal \ "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" -#PSC spacing poly,fp,pres,rp,pc/a,pm12c/a pc/a,pm12c/a 4 touching_ok \ +#PSC spacing poly,fp,pres,rp,pc/a pc/a 4 touching_ok \ #PSC "Poly spacing to Poly contact < 4 (Mosis #5.5.b)" - edge4way gc ~(gc)/contact 1 diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,poly,fp,pres,rp,pc/a,pm12c/a ~(gc)/contact 1 \ + edge4way gc ~(gc)/contact 1 diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,poly,fp,pres,rp,pc/a ~(gc)/contact 1 \ "Diffusion,Poly overlap of GC contact < 1 (Mosis #6.2)" active - spacing gc pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 touching_illegal \ + spacing gc pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 2 touching_illegal \ "Generic contact spacing to Poly contact,Diffusion contact < 2 (Mosis #5.3)" - spacing nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1 pdc/m1,pdm12c/m1 1 touching_illegal \ + spacing nsc/m1,nwsc/m1 pdc/m1 1 touching_illegal \ "nsc spacing to pdc < 1 (Mosis #6.3)" - spacing psc/m1,psm12c/m1 ndc/m1,ndm12c/m1 1 touching_illegal \ + spacing psc/m1 ndc/m1 1 touching_illegal \ "psc spacing to ndc < 1 (Mosis #6.3)" - spacing pdm12c/m1 pdc/m1,m2c/m1,nsm12c/m1 1 touching_illegal \ - "pdm12c spacing to pdc or m2c or nsm12c < 1 (Mosis #6.3)" - spacing psm12c/m1 psc/m1,m2c/m1 1 touching_illegal \ - "psm12c spacing to psc or m2c < 1 (Mosis #6.3)" - spacing ndm12c/m1 ndc/m1,m2c/m1,nsm12c/m1 1 touching_illegal \ - "ndm12c spacing to ndc or m2c or nsm12c < 1 (Mosis #6.3)" - spacing nsm12c/m1 nsc/m1,m2c/m1 1 touching_illegal \ - "nsm12c spacing to nsc or m2c < 1 (Mosis #6.3)" - spacing pm12c/m1 pc/m1,m2c/m1 1 touching_illegal \ - "pm12c spacing to pc or m2c < 1 (Mosis #6.3)" - spacing m123c/m2 pdm12c/m2,psm12c/m2,ndm12c/m2,nsm12c/m2,pm12c/m2,m2c/m2,m3c/m2 1 touching_illegal \ - "m123c spacing to *m12c or m2c or m3c < 1 (Mosis #6.3)" - spacing m234c/m3 m3c/m3,m4c/m3,m123c/m3 1 touching_illegal \ - "m234c spacing to m3c or m4c or m123c < 1 (Mosis #6.3)" - spacing nfet,pfet ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 touching_illegal \ + spacing nfet,pfet ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 1 touching_illegal \ "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" spacing nfet,pfet gc 2 touching_illegal \ "N-Transistor,P-Transistor spacing to Generic contact < 2 (Mosis #6.4)" - spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a pc/a,pm12c/a 1 touching_illegal \ + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a pc/a 1 touching_illegal \ "Diffusion spacing to Poly contact < 1 (Mosis #6.5.b)" - spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nfet,pfet ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 4 touching_ok \ + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,nfet,pfet ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 4 touching_ok \ "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" - spacing pc/a,pm12c/a ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 2 touching_illegal \ - "pc/a,pm12c/a spacing to ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a < 2 (Mosis #6.7)" + spacing pc/a ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 2 touching_illegal \ + "pc/a,pm12c/a spacing to ndc/a,pdc/a,psc/a,nsc/a,nwsc/a < 2 (Mosis #6.7)" - spacing m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 3 touching_ok \ + spacing m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 touching_ok \ "Metal1 spacing < 3 (Mosis #7.2)" - spacing m1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 fm1,fapm 3 touching_illegal \ + spacing m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 fm1,fapm 3 touching_illegal \ "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" spacing fm1 fm1 4 touching_ok \ "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" - edge4way gc space 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 space 1 \ + edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 - edge4way ~(m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1)/metal1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 1 ~(gc)/contact 0 0 \ + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc)/contact 0 0 \ "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact spacing gv1 gv1 3 touching_ok \ "GV1 via spacing < 3 (Mosis #8.2)" - edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 ~(gv1)/via1 1 \ + edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 ~(gv1)/via1 1 \ "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 - edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 space 1 \ + edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 - edge4way ~(m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1)/metal1 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 1 ~(gv1)/via1 0 0 \ + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gv1)/via1 0 0 \ "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 - spacing m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 3 touching_ok \ + spacing m2,rm2,m2c/m2,m3c/m2 m2,rm2,m2c/m2,m3c/m2 3 touching_ok \ "Metal2 spacing < 3 (Mosis #9.2)" - spacing m2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 fm2,fapm 3 touching_illegal \ + spacing m2,rm2,m2c/m2,m3c/m2 fm2,fapm 3 touching_illegal \ "Metal2 spacing to fill layer (fm2) < 3 (Mosis #9.2)" spacing fm2 fm2 4 touching_ok \ "Metal2 fill layer (fm2) spacing < 4 (Mosis #0)" - edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 space 1 \ + edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ "Metal2 must overlap GV1 via by 1 (Mosis #9.3)" metal2 - edge4way ~(m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2)/metal2 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 1 ~(gv1)/via1 0 0 \ + edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv1)/via1 0 0 \ "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 width glass 10 \ @@ -9461,46 +6891,46 @@ drc spacing gv2 gv2 3 touching_ok \ "GV2 via spacing < 3 (Mosis #14.2)" - spacing gv2 m3c/m2,m123c/m2,m234c/m2 2 touching_illegal \ + spacing gv2 m3c/m2 2 touching_illegal \ "GV2 via spacing to Metal3 contact < 2 (Mosis #14.2)" - edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 space 1 \ + edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ "Metal2 must overlap GV2 via by 1 (Mosis #14.3)" metal2 - edge4way ~(m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2)/metal2 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 1 ~(gv2)/via2 0 0 \ + edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv2)/via2 0 0 \ "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 - spacing m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 3 touching_ok \ + spacing m3,rm3,m3c/m3,m4c/m3 m3,rm3,m3c/m3,m4c/m3 3 touching_ok \ "Metal3 spacing < 3 (Mosis #15.2)" - spacing m3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 fm3,fapm 3 touching_illegal \ + spacing m3,rm3,m3c/m3,m4c/m3 fm3,fapm 3 touching_illegal \ "Metal3 spacing to fill layer (fm3) < 3 (Mosis #15.2)" spacing fm3 fm3 4 touching_ok \ "Metal3 fill layer (fm3) spacing < 4 (Mosis #0)" - edge4way gv2 space 1 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 space 1 \ + edge4way gv2 space 1 m3,fm3,rm3,m3c/m3,m4c/m3 space 1 \ "Metal3 must overlap GV2 via by 1 (Mosis #15.3)" metal3 - edge4way ~(m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 1 ~(gv2)/via2 0 0 \ + edge4way ~(m3,fm3,rm3,m3c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m4c/m3 1 ~(gv2)/via2 0 0 \ "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 spacing sb,pres,anres,apres sb,pres,anres,apres 4 touching_ok \ "Silicide-Block spacing < 4 (Mosis #20.2)" - spacing sb,pres,anres,apres,pres,anres,apres pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 1 touching_illegal \ + spacing sb,pres,anres,apres,pres,anres,apres pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 1 touching_illegal \ "Silicide-Block spacing to Diffusion contact,Poly contact < 1 (Mosis #20.3)" spacing sb,pres,anres,apres,pres,anres,apres gc 2 touching_illegal \ "Silicide-Block spacing to GC contact < 2 (Mosis #20.3)" - edge4way sb,pres,anres,apres space 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a)/active 0 2 \ + edge4way sb,pres,anres,apres space 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active 0 2 \ "Silicide-Block space to Diffusion < 2 (Mosis #20.4)" active - spacing sb,pres,anres,apres,pres poly,fp,pres,rp,pc/a,pm12c/a 2 touching_ok \ + spacing sb,pres,anres,apres,pres poly,fp,pres,rp,pc/a 2 touching_ok \ "Silicide-Block spacing to other Poly < 2 (Mosis #20.5)" - edge4way sb,pres,anres,apres space 2 ~(poly,fp,pres,rp,pc/a,pm12c/a)/contact sb,pres,anres,apres 2 \ + edge4way sb,pres,anres,apres space 2 ~(poly,fp,pres,rp,pc/a)/contact sb,pres,anres,apres 2 \ "Silicide-Block space to Poly < 2 (Mosis #20.5x)" contact spacing sb,pres,anres,apres,pres nfet,pfet,fet 2 touching_ok \ @@ -9515,34 +6945,34 @@ drc edge4way pres,anres,apres space/active,sb 2 sb sb 2 \ "Silicide-Block overlap of Silicide-Block polyR/activeR < 2 (Mosis #20.15)" - edge4way sb,pres,anres,apres diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 3 diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a 0 0 \ + edge4way sb,pres,anres,apres diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 3 diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 0 0 \ "Diffusion overhang of Silicide-Block < 3 (Mosis #20.17) spacing gv3 gv3 3 touching_ok \ "GV3 via spacing < 3 (Mosis #21.2)" - spacing gv3 m4c/m3,m234c/m3 2 touching_illegal \ + spacing gv3 m4c/m3 2 touching_illegal \ "GV3 via spacing to Metal4 contact < 2 (Mosis #21.2)" - edge4way gv3 space 1 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 space 1 \ + edge4way gv3 space 1 m3,fm3,rm3,m3c/m3,m4c/m3 space 1 \ "Metal3 must overlap GV3 via by 1 (Mosis #21.3)" metal3 - edge4way ~(m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m123c/m3,m234c/m3,m4c/m3 1 ~(gv3)/via3 0 0 \ + edge4way ~(m3,fm3,rm3,m3c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m4c/m3 1 ~(gv3)/via3 0 0 \ "Metal3(edge) cannot touch GV3 via (Mosis #21.3)" via3 - spacing m4,rm4,m4c/m4,m234c/m4,pad m4,rm4,m4c/m4,m234c/m4,pad 3 touching_ok \ + spacing m4,rm4,m4c/m4,pad m4,rm4,m4c/m4,pad 3 touching_ok \ "Metal4 spacing < 3 (Mosis #22.2)" - spacing m4,rm4,m4c/m4,m234c/m4,pad fm4,fapm 3 touching_illegal \ + spacing m4,rm4,m4c/m4,pad fm4,fapm 3 touching_illegal \ "Metal4 spacing to fill layer (fm4) < 3 (Mosis #22.2)" spacing fm4 fm4 4 touching_ok \ "Metal4 fill layer (fm4) spacing < 4 (Mosis #0)" - edge4way gv3 space 1 m4,fm4,rm4,m4c/m4,m234c/m4,pad space 1 \ + edge4way gv3 space 1 m4,fm4,rm4,m4c/m4,pad space 1 \ "Metal4 must overlap GV3 via by 1 (Mosis #22.3)" metal4 - edge4way ~(m4,fm4,rm4,m4c/m4,m234c/m4,pad)/metal4 m4,fm4,rm4,m4c/m4,m234c/m4,pad 1 ~(gv3)/via3 0 0 \ + edge4way ~(m4,fm4,rm4,m4c/m4,pad)/metal4 m4,fm4,rm4,m4c/m4,pad 1 ~(gv3)/via3 0 0 \ "Metal4(edge) cannot touch GV3 via (Mosis #22.3)" via3 spacing nfi nfi 4 touching_ok \ @@ -9554,10 +6984,10 @@ drc spacing nfi pfi 4 touching_illegal \ "N_field-implant spacing to P_field-implant < 4 (Mosis #35.2)" - spacing nwell,pdiff,apres,rpd,pfet,pdc/a,pdm12c/a pfi 4 touching_illegal \ + spacing nwell,pdiff,apres,rpd,pfet,pdc/a pfi 4 touching_illegal \ "N-well,P-Diffusion spacing to P_field-implant < 4 (Mosis #2.1)" - spacing pwell,ndiff,anres,rnd,nfet,ndc/a,ndm12c/a nfi 4 touching_illegal \ + spacing pwell,ndiff,anres,rnd,nfet,ndc/a nfi 4 touching_illegal \ "P-well,N-Diffusion spacing to N_field-implant < 4 (Mosis #2.1)" edge4way ~(nwell)/well nwell 4 ~(nfi)/implant nwell 4 \ @@ -9641,13 +7071,13 @@ drc edge4way rm4 space/metal4 1 prm4 0 0 \ "prm4 overhang of rmetal4 (for resistor L/W extraction) < 1 (Mosis #0)" metal4 - edge4way ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a ~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active 1 ~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active (~(ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a),ndc/a,ndm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a)/active 1 \ + edge4way ndc/a,nsc/a,nwsc/a ~(ndc/a,nsc/a,nwsc/a)/active 1 ~(ndc/a,nsc/a,nwsc/a)/active (~(ndc/a,nsc/a,nwsc/a),ndc/a,nsc/a,nwsc/a)/active 1 \ "Contact not rectangular (Magic rule)" - edge4way pdc/a,pdm12c/a,psc/a,psm12c/a ~(pdc/a,pdm12c/a,psc/a,psm12c/a)/active 1 ~(pdc/a,pdm12c/a,psc/a,psm12c/a)/active (~(pdc/a,pdm12c/a,psc/a,psm12c/a),pdc/a,pdm12c/a,psc/a,psm12c/a)/active 1 \ + edge4way pdc/a,psc/a ~(pdc/a,psc/a)/active 1 ~(pdc/a,psc/a)/active (~(pdc/a,psc/a),pdc/a,psc/a)/active 1 \ "Contact not rectangular (Magic rule)" - edge4way pc/a,pm12c/a ~(pc/a,pm12c/a)/active 1 ~(pc/a,pm12c/a)/active (~(pc/a,pm12c/a),pc/a,pm12c/a)/active 1 \ + edge4way pc/a ~(pc/a)/active 1 ~(pc/a)/active (~(pc/a),pc/a)/active 1 \ "Contact not rectangular (Magic rule)" edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ @@ -9656,33 +7086,33 @@ drc edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ "Contact not rectangular (Magic rule)" - edge4way m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 ~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 1 ~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 (~(m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1),m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1)/metal1 1 \ + edge4way m2c/m1 ~(m2c/m1)/metal1 1 ~(m2c/m1)/metal1 (~(m2c/m1),m2c/m1)/metal1 1 \ "Contact not rectangular (Magic rule)" edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ "Contact not rectangular (Magic rule)" - edge4way m3c/m2,m123c/m2,m234c/m2 ~(m3c/m2,m123c/m2,m234c/m2)/metal2 1 ~(m3c/m2,m123c/m2,m234c/m2)/metal2 (~(m3c/m2,m123c/m2,m234c/m2),m3c/m2,m123c/m2,m234c/m2)/metal2 1 \ + edge4way m3c/m2 ~(m3c/m2)/metal2 1 ~(m3c/m2)/metal2 (~(m3c/m2),m3c/m2)/metal2 1 \ "Contact not rectangular (Magic rule)" edge4way gv3 ~(gv3)/via3 1 ~(gv3)/via3 (~(gv3),gv3)/via3 1 \ "Contact not rectangular (Magic rule)" - edge4way m4c/m3,m234c/m3 ~(m4c/m3,m234c/m3)/metal3 1 ~(m4c/m3,m234c/m3)/metal3 (~(m4c/m3,m234c/m3),m4c/m3,m234c/m3)/metal3 1 \ + edge4way m4c/m3 ~(m4c/m3)/metal3 1 ~(m4c/m3)/metal3 (~(m4c/m3),m4c/m3)/metal3 1 \ "Contact not rectangular (Magic rule)" - exact_overlap gc,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,pc/a,pm12c/a,gc + exact_overlap gc,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,pc/a,gc edge4way pad ~(pad)/m4 1 ~(pad)/m4 (~(pad),pad)/m4 1 \ "Contact not rectangular (Magic rule)" - exact_overlap ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1 + exact_overlap ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1 - exact_overlap m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2 + exact_overlap m2c/m2 - exact_overlap m3c/m3,m123c/m3,m234c/m3 + exact_overlap m3c/m3 - exact_overlap m4c/m4,m234c/m4 + exact_overlap m4c/m4 exact_overlap gv1 @@ -9748,19 +7178,17 @@ lef ignore PC ignore CA - routing m1 M1 m1 met1 - routing m2 M2 m2 met2 - routing m3 M3 m3 met3 - routing m4 M4 m4 met4 + routing m1 metal1 M1 m1 met1 + routing m2 metal2 M2 m2 met2 + routing m3 metal3 M3 m3 met3 + routing m4 metal4 M4 m4 met4 - contact m2c via1 V1 v1 + contact m2c via1 via V1 v1 contact m3c via2 V2 v2 contact m4c via3 V3 v3 end -#--------------------------------------------------- - extract style TSMC0.35um(tsmc35)from:t11c cscale 1 @@ -9784,17 +7212,17 @@ extract planeorder via3 14 planeorder fill 15 - resist (ndiff,anres,rnd,ndc,ndm12c,nsd,nwsd,nsc,nwsc,nsm12c,nwsm12c)/active 3700 - resist (pdiff,apres,rpd,pdc,pdm12c,psd,psc,psm12c)/active 2800 + resist (ndiff,anres,rnd,ndc,nsd,nwsd,nsc,nwsc)/active 3700 + resist (pdiff,apres,rpd,pdc,psd,psc)/active 2800 resist (nwell)/well 1018000 resist (rnw,nwr)/active 1018000 resist (pwell)/well 1 - resist (poly,fp,rp,pc,pm12c,pc,pm12c,nfet,pfet,fet)/active 6000 + resist (poly,fp,rp,pc,pc,nfet,pfet,fet)/active 6000 resist (pres)/active 6000 - resist (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c)/metal1 80 - resist (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c,m3c,m123c,m234c)/metal2 70 - resist (m3,fm3,rm3,m3c,m123c,m234c,m4c,m4c,m234c)/metal3 80 - resist (m4,fm4,rm4,m4c,m234c,pad)/metal4 40 + resist (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c,m2c)/metal1 80 + resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 70 + resist (m3,fm3,rm3,m3c,m4c,m4c)/metal3 80 + resist (m4,fm4,rm4,m4c,pad)/metal4 40 contact ndc 4 4100 contact pdc 4 3400 @@ -9811,10 +7239,10 @@ extract areacap (rnw,nwr)/active 2.360 #ndiff -# MODEL HANDLES THIS: areacap (ndiff,ndc,ndm12c)/active 43.160 -# MODEL HANDLES THIS: overlap (ndiff,ndc,ndm12c)/active ~space/w 43.160 -# MODEL HANDLES THIS: perimc (ndiff,ndc,ndm12c)/active ~(ndiff,ndc,ndm12c,nfet,pfet,fet)/active 64.200 -# MODEL HANDLES THIS: sideoverlap (ndiff,ndc,ndm12c)/active ~(ndiff,ndc,ndm12c,nfet,pfet,fet)/active ~space/w 64.200 +# MODEL HANDLES THIS: areacap (ndiff,ndc)/active 43.160 +# MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 43.160 +# MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 64.200 +# MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 64.200 areacap (rnd,anres)/active 43.160 overlap (rnd,anres)/active ~space/w 43.160 @@ -9822,10 +7250,10 @@ extract sideoverlap (rnd,anres)/active ~(rnd,anres)/active ~space/w 64.200 #pdiff -# MODEL HANDLES THIS: areacap (pdiff,pdc,pdm12c)/active 55.880 -# MODEL HANDLES THIS: overlap (pdiff,pdc,pdm12c)/active ~space/w 55.880 -# MODEL HANDLES THIS: perimc (pdiff,pdc,pdm12c)/active ~(pdiff,pdc,pdm12c,nfet,pfet,fet)/active 81.800 -# MODEL HANDLES THIS: sideoverlap (pdiff,pdc,pdm12c)/active ~(pdiff,pdc,pdm12c,nfet,pfet,fet)/active ~space/w 81.800 +# MODEL HANDLES THIS: areacap (pdiff,pdc)/active 55.880 +# MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 55.880 +# MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 81.800 +# MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 81.800 areacap (rpd,apres)/active 55.880 overlap (rpd,apres)/active ~space/w 55.880 @@ -9835,150 +7263,150 @@ extract #rnw #poly -# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,anres,rnd,ndc,ndm12c)/active 181.800 -# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,anres,rnd,ndc,ndm12c)/active 55.400 -# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,apres,rpd,pdc,pdm12c)/active 181.160 -# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,apres,rpd,pdc,pdm12c)/active 52.200 +# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,anres,rnd,ndc)/active 181.800 +# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,anres,rnd,ndc)/active 55.400 +# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,apres,rpd,pdc)/active 181.160 +# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,apres,rpd,pdc)/active 52.200 - sidewall (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active (poly,fp,pres,rp,pc,pm12c)/active 11.331 - areacap (poly,fp,pres,rp,pc,pm12c)/active 4.074 - overlap (poly,fp,pres,rp,pc,pm12c)/active ~space/w 4.074 - perimc (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active 4.622 - sideoverlap (poly,fp,pres,rp,pc,pm12c)/active ~(poly,fp,pres,rp,pc,pm12c)/active ~space/w 4.622 + sidewall (poly,fp,pres,rp,pc)/active ~(poly,fp,pres,rp,pc)/active ~(poly,fp,pres,rp,pc)/active (poly,fp,pres,rp,pc)/active 11.331 + areacap (poly,fp,pres,rp,pc)/active 4.074 + overlap (poly,fp,pres,rp,pc)/active ~space/w 4.074 + perimc (poly,fp,pres,rp,pc)/active ~(poly,fp,pres,rp,pc)/active 4.622 + sideoverlap (poly,fp,pres,rp,pc)/active ~(poly,fp,pres,rp,pc)/active ~space/w 4.622 #poly2 #rnw #metal1 - sidewall (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 20.619 - areacap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 1.666 + sidewall (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 20.619 + areacap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 1.666 #metal1-sub blocked by ~space/a - overlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~space/w 1.666 ~space/a - perimc (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 2.226 - sideoverlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~space/w 2.226 ~space/a + overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 1.666 ~space/a + perimc (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 2.226 + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.226 ~space/a #rnw - overlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 rnw,nwr/active 1.666 - sideoverlap (m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,pdc,pdm12c,pc,pm12c,m2c,m123c)/metal1 rnw,nwr/active 2.226 + overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw,nwr/active 1.666 + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw,nwr/active 2.226 #metal1-diff blocked by - overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (ndiff,anres,rnd,ndc,ndm12c)/active 1.640 - sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (ndiff,anres,rnd,ndc,ndm12c)/active 2.226 - overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (pdiff,apres,rpd,pdc,pdm12c)/active 1.640 - sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (pdiff,apres,rpd,pdc,pdm12c)/active 2.226 + overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 1.640 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 2.226 + overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 1.640 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 2.226 #metal1-poly blocked by - overlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 1.687 - sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 2.250 - sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 2.250 + overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 1.687 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 2.250 + sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 2.250 #metal2 - sidewall (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 23.532 - areacap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 0.581 + sidewall (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m2,fm2,rm2,m2c,m3c)/metal2 23.532 + areacap (m2,fm2,rm2,m3c)/metal2 0.581 #metal2-sub blocked by - overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 ~space/w 0.581 ~space/a,~space/m1 - perimc (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.836 - sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~space/w 0.836 ~space/a,~space/m1 - overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 rnw,nwr/active 0.581 ~space/m1 - sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 rnw,nwr/active 0.836 ~space/m1 + overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 0.581 ~space/a,~space/m1 + perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 0.836 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 0.836 ~space/a,~space/m1 + overlap (m2,fm2,rm2,m3c)/metal2 rnw,nwr/active 0.581 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw,nwr/active 0.836 ~space/m1 #metal2-*diff blocked by ~space/m1 - overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (ndiff,anres,rnd,ndc,ndm12c)/active 0.720 ~space/m1 - sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (ndiff,anres,rnd,ndc,ndm12c)/active 0.836 ~space/m1 - overlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (pdiff,apres,rpd,pdc,pdm12c)/active 0.720 ~space/m1 - sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (pdiff,apres,rpd,pdc,pdm12c)/active 0.836 ~space/m1 + overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,anres,rnd,ndc)/active 0.720 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,anres,rnd,ndc)/active 0.836 ~space/m1 + overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,apres,rpd,pdc)/active 0.720 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,apres,rpd,pdc)/active 0.836 ~space/m1 #metal2-poly blocked by ~space/m1 - overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.583 ~space/m1 - sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.840 ~space/m1 - sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.840 ~space/m1 + overlap (m2,fm2,rm2,m3c)/metal2 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.583 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.840 ~space/m1 + sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 0.840 ~space/m1 #M2->M1 - overlap (m2,fm2,rm2,m3c,m123c,m234c)/metal2 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 1.844 - sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 2.432 - sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 2.432 + overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 1.844 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 2.432 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 2.432 #metal3 - sidewall (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 24.216 - areacap (m3,fm3,rm3,m4c,m234c)/metal3 0.352 + sidewall (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m3,fm3,rm3,m3c,m4c)/metal3 24.216 + areacap (m3,fm3,rm3,m4c)/metal3 0.352 #metal3-sub blocked by ~space/a,~space/m1,~space/m2 - overlap (m3,fm3,rm3,m4c,m234c)/metal3 ~space/w 0.352 ~space/a,~space/m1,~space/m2 - perimc (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.514 - sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~space/w 0.514 ~space/a,~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 ~space/w 0.352 ~space/a,~space/m1,~space/m2 + perimc (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 0.514 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 ~space/w 0.514 ~space/a,~space/m1,~space/m2 #rnw - overlap (m3,fm3,rm3,m4c,m234c)/metal3 rnw,nwr/active 0.352 ~space/m1,~space/m2 - sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 rnw,nwr/active 0.514 ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 rnw,nwr/active 0.352 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 rnw,nwr/active 0.514 ~space/m1,~space/m2 #metal3-*diff blocked by ~space/m1,~space/m2 - overlap (m3,fm3,rm3,m4c,m234c)/metal3 (ndiff,anres,rnd,ndc,ndm12c)/active 0.520 ~space/m1,~space/m2 - sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (ndiff,anres,rnd,ndc,ndm12c)/active 0.514 ~space/m1,~space/m2 - overlap (m3,fm3,rm3,m4c,m234c)/metal3 (pdiff,apres,rpd,pdc,pdm12c)/active 0.520 ~space/m1,~space/m2 - sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (pdiff,apres,rpd,pdc,pdm12c)/active 0.514 ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 (ndiff,anres,rnd,ndc)/active 0.520 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (ndiff,anres,rnd,ndc)/active 0.514 ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 (pdiff,apres,rpd,pdc)/active 0.520 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (pdiff,apres,rpd,pdc)/active 0.514 ~space/m1,~space/m2 #metal3-poly blocked by ~space/m1,~space/m2 - overlap (m3,fm3,rm3,m4c,m234c)/metal3 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.352 ~space/m1,~space/m2 - sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.516 ~space/m1,~space/m2 - sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.516 ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.352 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.516 ~space/m1,~space/m2 + sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,m4c)/metal3 0.516 ~space/m1,~space/m2 #M3->M1 #metal3-metal1 blocked by ~space/m2 - overlap (m3,fm3,rm3,m4c,m234c)/metal3 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.601 ~space/m2 - sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.864 ~space/m2 - sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 0.864 ~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 0.601 ~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 0.864 ~space/m2 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (m3,fm3,rm3,m3c,m4c)/metal3 0.864 ~space/m2 #M3->M2 - overlap (m3,fm3,rm3,m4c,m234c)/metal3 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 1.844 - sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 2.430 - sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 2.430 + overlap (m3,fm3,rm3,m4c)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 1.844 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 2.430 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,m4c)/metal3 2.430 #metal4 - sidewall (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m4,fm4,rm4,m4c,m234c,pad)/metal4 64.860 + sidewall (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (m4,fm4,rm4,m4c,pad)/metal4 64.860 areacap (m4,fm4,rm4,pad)/metal4 0.235 #metal4-sub blocked by ~space/a,~space/m1,~space/m2,~space/m3 overlap (m4,fm4,rm4,pad)/metal4 ~space/w 0.235 ~space/a,~space/m1,~space/m2,~space/m3 - perimc (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 0.802 - sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 ~space/w 0.802 ~space/a,~space/m1,~space/m2,~space/m3 + perimc (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 0.802 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 ~space/w 0.802 ~space/a,~space/m1,~space/m2,~space/m3 #rnw overlap (m4,fm4,rm4,pad)/metal4 rnw,nwr/active 0.235 ~space/m1,~space/m2,~space/m3 - sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 rnw,nwr/active 0.802 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 rnw,nwr/active 0.802 ~space/m1,~space/m2,~space/m3 #metal4-*diff blocked by ~space/m1,~space/m2,~space/m3 - overlap (m4,fm4,rm4,pad)/metal4 (ndiff,anres,rnd,ndc,ndm12c)/active 0.400 ~space/m1,~space/m2,~space/m3 - sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (ndiff,anres,rnd,ndc,ndm12c)/active 0.802 ~space/m1,~space/m2,~space/m3 - overlap (m4,fm4,rm4,pad)/metal4 (pdiff,apres,rpd,pdc,pdm12c)/active 0.400 ~space/m1,~space/m2,~space/m3 - sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (pdiff,apres,rpd,pdc,pdm12c)/active 0.802 ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (ndiff,anres,rnd,ndc)/active 0.400 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (ndiff,anres,rnd,ndc)/active 0.802 ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (pdiff,apres,rpd,pdc)/active 0.400 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (pdiff,apres,rpd,pdc)/active 0.802 ~space/m1,~space/m2,~space/m3 #metal4-poly blocked by ~space/m1,~space/m2,~space/m3 - overlap (m4,fm4,rm4,pad)/metal4 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.271 ~space/m1,~space/m2,~space/m3 - sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active 0.666 ~space/m1,~space/m2,~space/m3 - sideoverlap (poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,pm12c,nfet,pfet,fet)/active (m4,fm4,rm4,m4c,m234c,pad)/metal4 0.666 ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.271 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.666 ~space/m1,~space/m2,~space/m3 + sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m4,fm4,rm4,m4c,pad)/metal4 0.666 ~space/m1,~space/m2,~space/m3 #M4->M1 #metal4-metal1 blocked by ~space/m2,~space/m3 - overlap (m4,fm4,rm4,pad)/metal4 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 0.359 ~space/m2,~space/m3 - sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 1.038 ~space/m2,~space/m3 - sideoverlap (m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 ~(m1,fm1,rm1,ndc,ndm12c,nsc,nwsc,nsm12c,nwsm12c,pdc,pdm12c,psc,psm12c,pc,pm12c,m2c,m123c)/metal1 (m4,fm4,rm4,m4c,m234c,pad)/metal4 1.038 ~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 0.359 ~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 1.038 ~space/m2,~space/m3 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (m4,fm4,rm4,m4c,pad)/metal4 1.038 ~space/m2,~space/m3 #M4->M2 #metal4-metal2 blocked by ~space/m3 - overlap (m4,fm4,rm4,pad)/metal4 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 0.601 ~space/m3 - sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 1.698 ~space/m3 - sideoverlap (m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 ~(m2,fm2,rm2,m2c,pdm12c,ndm12c,psm12c,nsm12c,pm12c,m123c,nwsm12c,m3c,m234c)/metal2 (m4,fm4,rm4,m4c,m234c,pad)/metal4 1.698 ~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (m2,fm2,rm2,m2c,m3c)/metal2 0.601 ~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (m2,fm2,rm2,m2c,m3c)/metal2 1.698 ~space/m3 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m4,fm4,rm4,m4c,pad)/metal4 1.698 ~space/m3 #M4->M3 - overlap (m4,fm4,rm4,pad)/metal4 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 1.844 - sideoverlap (m4,fm4,rm4,m4c,m234c,pad)/metal4 ~(m4,fm4,rm4,m4c,m234c,pad)/metal4 (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 4.604 - sideoverlap (m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m123c,m234c,m4c)/metal3 (m4,fm4,rm4,m4c,m234c,pad)/metal4 4.604 + overlap (m4,fm4,rm4,pad)/metal4 (m3,fm3,rm3,m3c,m4c)/metal3 1.844 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (m3,fm3,rm3,m3c,m4c)/metal3 4.604 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m4,fm4,rm4,m4c,pad)/metal4 4.604 #metal5 @@ -9990,50 +7418,31 @@ extract #fets -# fet pfet pdiff,pdc 2 pfet Vdd! nwell 52 181 -# fet pfet pdiff,pdc 1 pfet Vdd! nwell 52 181 + fet pfet pdiff,pdc 2 pfet Vdd! nwell 52 181 + fet pfet pdiff,pdc 1 pfet Vdd! nwell 52 181 - device mosfet pfet pfet pdiff,pdc nwell $VDD 52 181 - -# fet nfet ndiff,ndc 2 nfet Gnd! pwell 55 182 -# fet nfet ndiff,ndc 1 nfet Gnd! pwell 55 182 - - device mosfet nfet nfet ndiff,ndc pwell $GND 55 182 + fet nfet ndiff,ndc 2 nfet Gnd! pwell 55 182 + fet nfet ndiff,ndc 1 nfet Gnd! pwell 55 182 fetresis pfet linear 12182 fetresis pfet saturation 12182 fetresis nfet linear 3961 fetresis nfet saturation 3961 -# fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 -# fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 -# fet nwr nwsd 2 nwellFig1bResistor Gnd! nwell,pwell 0 0 -# fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 -# fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 + fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 + fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 + fet nwr nwsd 2 nwellFig1bResistor Gnd! nwell,pwell 0 0 + fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 + fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 - device resistor None rnwell nsd,nsc - device resistor None rpoly poly,pc - device resistor None nwr nwsd - device resistor None rndiff ndiff,ndc - device resistor None rpdiff pdiff,pdc + fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 + fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 + fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 + fet rmetal4 metal4 2 metal4Resistor Gnd! nwell,pwell 0 0 -# fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 -# fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 -# fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 -# fet rmetal4 metal4 2 metal4Resistor Gnd! nwell,pwell 0 0 - - device resistor None rmetal1 *metal1 - device resistor None rmetal2 *metal2 - device resistor None rmetal3 *metal3 - device resistor None rmetal4 *metal4 - -# fet pres poly,pc 2 presResistor Gnd! nwell,pwell 0 0 -# fet anres ndiff,ndc 2 anresResistor Gnd! nwell,pwell 0 0 -# fet apres pdiff,pdc 2 apresResistor Gnd! nwell,pwell 0 0 - - device resistor None pres poly,pc - device resistor None anres ndiff,ndc - device resistor None apres pdiff,pdc + fet pres poly,pc 2 presResistor Gnd! nwell,pwell 0 0 + fet anres ndiff,ndc 2 anresResistor Gnd! nwell,pwell 0 0 + fet apres pdiff,pdc 2 apresResistor Gnd! nwell,pwell 0 0 end @@ -10048,8 +7457,8 @@ wiring end router - layer2 metal2 3 m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m123c/m2,m234c/m2,m3c/m2,m123c/m2,m234c/m2 4 poly,fp,pres,rp,ndiff,anres,rnd,nsd,nwsd,pdiff,apres,rpd,psd,m1,fm1,rm1 1 - layer1 metal1 3 m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1 3 + layer2 metal2 3 m2,fm2,rm2,m2c/m2,m3c/m2,m3c/m2 4 poly,fp,pres,rp,ndiff,anres,rnd,nsd,nwsd,pdiff,apres,rpd,psd,m1,fm1,rm1 1 + layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 contacts m2contact 4 gridspacing 8 @@ -10064,57 +7473,57 @@ end plot style colorversatec - ndiff,anres,rnd,ndc/a,ndm12c/a yellow \ + ndiff,anres,rnd,ndc/a yellow \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA - ndiff,anres,rnd,ndc/a,ndm12c/a cyan \ + ndiff,anres,rnd,ndc/a cyan \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 - nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a yellow \ + nsd,nwsd,nsc/a,nwsc/a yellow \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 - nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a cyan \ + nsd,nwsd,nsc/a,nwsc/a cyan \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 - pdiff,apres,rpd,pdc/a,pdm12c/a yellow \ + pdiff,apres,rpd,pdc/a yellow \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA - pdiff,apres,rpd,pdc/a,pdm12c/a cyan \ + pdiff,apres,rpd,pdc/a cyan \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 \ 0000 5555 0000 5555 - pdiff,apres,rpd,pdc/a,pdm12c/a magenta \ + pdiff,apres,rpd,pdc/a magenta \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 - psd,psc/a,psm12c/a yellow \ + psd,psc/a yellow \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 \ 1515 2A2A 5151 A2A2 - psd,psc/a,psm12c/a cyan \ + psd,psc/a cyan \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 \ 0000 1515 0000 5151 - psd,psc/a,psm12c/a magenta \ + psd,psc/a magenta \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 \ 2A2A 0000 A2A2 0000 - poly,fp,pres,rp,pc/a,pm12c/a magenta \ + poly,fp,pres,rp,pc/a magenta \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ 5555 AAAA 5555 AAAA \ @@ -10149,22 +7558,22 @@ style colorversatec 4949 A0A0 5252 2828 \ 9494 0A0A 2525 8282 \ 4949 A0A0 5252 2828 - m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 cyan \ + m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 cyan \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 \ AAAA 0000 AAAA 0000 - m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 cyan \ + m2,fm2,rm2,m2c/m2,m3c/m2 cyan \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 \ 0000 1111 0000 4444 - m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 magenta \ + m2,fm2,rm2,m2c/m2,m3c/m2 magenta \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 \ 0000 4444 0000 1111 - m2c/m1,pdm12c/m1,ndm12c/m1,psm12c/m1,nsm12c/m1,pm12c/m1,m123c/m1,nwsm12c/m1,gv1 black \ + m2c/m1,gv1 black \ 0000 6666 6666 0000 \ 0000 9999 9999 0000 \ 0000 6666 6666 0000 \ @@ -10199,22 +7608,22 @@ style colorversatec 0080 0000 0020 0000 \ 0008 0000 0002 0000 \ 8000 0000 2000 0000 - m3c/m2,m123c/m2,m234c/m2,gv2 black \ + m3c/m2,gv2 black \ 0100 0000 0000 0000 \ 1010 0000 0000 0000 \ 0001 0000 0000 0000 \ 1010 0000 0000 0000 - m3c/m2,m123c/m2,m234c/m2,gv2 cyan \ + m3c/m2,gv2 cyan \ 0280 0000 0820 0000 \ 2008 0000 8002 0000 \ 8002 0000 2008 0000 \ 0820 0000 0280 0000 - m3c/m2,m123c/m2,m234c/m2,gv2 magenta \ + m3c/m2,gv2 magenta \ 0100 06C0 0440 1830 \ 1010 600C 4004 8003 \ 0001 C006 4004 3018 \ 1010 0C60 0440 0380 - m3c/m2,m123c/m2,m234c/m2,gv2 black \ + m3c/m2,gv2 black \ 0820 0820 0820 0FE0 \ E00F 2008 2008 2008 \ 2008 2008 2008 E00F \ @@ -10239,7 +7648,7 @@ style colorversatec 0000 0000 0000 0000 \ 0000 E0E0 E0E0 E0E0 \ 0000 0000 0000 0000 - pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc X + pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc X style versatec pfet \ @@ -10267,12 +7676,12 @@ style versatec 0000 0000 0000 0000 \ 0808 0404 0202 0101 \ 0000 0000 0000 0000 - poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet \ + poly,fp,pres,rp,pc/a,nfet,pfet \ 0808 0400 0202 0101 \ 8080 4000 2020 1010 \ 0808 0004 0202 0101 \ 8080 0040 2020 1010 - m1,fm1,rm1,ndc/m1,ndm12c/m1,nsc/m1,nwsc/m1,nsm12c/m1,nwsm12c/m1,pdc/m1,pdm12c/m1,psc/m1,psm12c/m1,pc/m1,pm12c/m1,m2c/m1,m123c/m1 \ + m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 \ 8080 0000 0000 0000 \ 0808 0000 0000 0000 \ 8080 0000 0000 0000 \ @@ -10282,32 +7691,32 @@ style versatec 3636 3e3e 1c1c 0000 \ 0000 0000 1c1c 3e3e \ 3636 3e3e 1c1c 0000 - nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a \ + nsd,nwsd,nsc/a,nwsc/a \ 0808 1414 2222 4141 \ 8080 4040 2020 1010 \ 0808 1414 2222 4141 \ 8080 4040 2020 1010 - m2,fm2,rm2,m2c/m2,pdm12c/m2,ndm12c/m2,psm12c/m2,nsm12c/m2,pm12c/m2,m123c/m2,nwsm12c/m2,m3c/m2,m234c/m2 \ + m2,fm2,rm2,m2c/m2,m3c/m2 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 \ 0000 1111 0000 0000 - pdiff,apres,rpd,pdc/a,pdm12c/a,pfet \ + pdiff,apres,rpd,pdc/a,pfet \ 0000 0808 5555 8080 \ 0000 8080 5555 0808 \ 0000 0808 5555 8080 \ 0000 8080 5555 0808 - psd,psc/a,psm12c/a \ + psd,psc/a \ 1414 2222 0000 2222 \ 4141 2222 0000 2222 \ 1414 2222 0000 2222 \ 4141 2222 0000 2222 - ndiff,anres,rnd,ndc/a,ndm12c/a,nfet \ + ndiff,anres,rnd,ndc/a,nfet \ 0808 1010 2020 4040 \ 8080 4141 2222 1414 \ 0808 1010 2020 4040 \ 8080 4141 2222 1414 - pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc X + pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc X style gremlin pfet 9 @@ -10315,15 +7724,15 @@ style gremlin gv1 11 pwell 15 nwell 16 - poly,fp,pres,rp,pc/a,pm12c/a,nfet,pfet 19 - pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc 22 + poly,fp,pres,rp,pc/a,nfet,pfet 19 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc 22 pad,glass 23 - nsd,nwsd,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a 24 + nsd,nwsd,nsc/a,nwsc/a 24 gv1 28 - pdiff,apres,rpd,pdc/a,pdm12c/a,pfet 29 - psd,psc/a,psm12c/a 30 - ndiff,anres,rnd,ndc/a,ndm12c/a,nfet 31 - pc/a,pm12c/a,ndc/a,ndm12c/a,pdc/a,pdm12c/a,psc/a,psm12c/a,nsc/a,nwsc/a,nsm12c/a,nwsm12c/a,gc,gc,gc,gv1 X + pdiff,apres,rpd,pdc/a,pfet 29 + psd,psc/a 30 + ndiff,anres,rnd,ndc/a,nfet 31 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc,gv1 X end diff --git a/technology/scn4me_subm/tech/__init__.py b/technology/scn4m_subm/tech/__init__.py similarity index 100% rename from technology/scn4me_subm/tech/__init__.py rename to technology/scn4m_subm/tech/__init__.py diff --git a/technology/scn4me_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py similarity index 96% rename from technology/scn4me_subm/tech/tech.py rename to technology/scn4m_subm/tech/tech.py index 85285f84..a31923ca 100755 --- a/technology/scn4me_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -159,7 +159,7 @@ drc["minarea_metal1"] = 0 # 8.1 Exact size drc["minwidth_via1"] = 2*_lambda_ # 8.2 Minimum via1 spacing -drc["via1_to_via1"] = 2*_lambda_ +drc["via1_to_via1"] = 3*_lambda_ # 9.1 Minimum width drc["minwidth_metal2"] = 3*_lambda_ @@ -176,7 +176,7 @@ drc["metal2_enclosure_via2"] = _lambda_ # Not a rule drc["minarea_metal2"] = 0 -# 14.2 Exact size +# 14.1 Exact size drc["minwidth_via2"] = 2*_lambda_ # 14.2 Minimum spacing drc["via2_to_via2"] = 3*_lambda_ @@ -188,13 +188,13 @@ drc["metal3_to_metal3"] = 3*_lambda_ # 15.3 Minimum overlap of via 2 drc["metal3_extend_via2"] = _lambda_ # Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = 2*_lambda_ +drc["metal3_enclosure_via2"] = _lambda_ # Reserved for asymmetric enclosures drc["metal2_enclosure_via1"] = _lambda_ # 21.3 Minimum overlap by metal3 -drc["metal3_extend_via2"] = _lambda_ +drc["metal3_extend_via3"] = _lambda_ # Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = _lambda_ +drc["metal3_enclosure_via3"] = _lambda_ # Not a rule drc["minarea_metal3"] = 0 @@ -204,13 +204,13 @@ drc["minwidth_via3"] = 2*_lambda_ drc["via3_to_via3"] = 3*_lambda_ # 22.1 Minimum width -drc["minwidth_metal3"] = 6*_lambda_ -# 22.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 6*_lambda_ -# 22.3 Minimum overlap of via 2 -drc["metal3_extend_via2"] = 2*_lambda_ +drc["minwidth_metal4"] = 6*_lambda_ +# 22.2 Minimum spacing to metal4 +drc["metal4_to_metal4"] = 6*_lambda_ +# 22.3 Minimum overlap of via 3 +drc["metal4_extend_via3"] = 2*_lambda_ # Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = 2*_lambda_ +drc["metal4_enclosure_via3"] = 2*_lambda_ # Not a rule drc["minarea_metal3"] = 0 diff --git a/technology/scn4me_subm/tf/LICENSE b/technology/scn4m_subm/tf/LICENSE similarity index 100% rename from technology/scn4me_subm/tf/LICENSE rename to technology/scn4m_subm/tf/LICENSE diff --git a/technology/scn4me_subm/tf/README b/technology/scn4m_subm/tf/README similarity index 100% rename from technology/scn4me_subm/tf/README rename to technology/scn4m_subm/tf/README diff --git a/technology/scn4me_subm/tf/display.drf b/technology/scn4m_subm/tf/display.drf similarity index 100% rename from technology/scn4me_subm/tf/display.drf rename to technology/scn4m_subm/tf/display.drf diff --git a/technology/scn4me_subm/tf/glade_scn4me_subm.py b/technology/scn4m_subm/tf/glade_scn4me_subm.py similarity index 100% rename from technology/scn4me_subm/tf/glade_scn4me_subm.py rename to technology/scn4m_subm/tf/glade_scn4me_subm.py diff --git a/technology/scn4me_subm/tf/layers.map b/technology/scn4m_subm/tf/layers.map similarity index 100% rename from technology/scn4me_subm/tf/layers.map rename to technology/scn4m_subm/tf/layers.map diff --git a/technology/scn4me_subm/tf/mosis.tf b/technology/scn4m_subm/tf/mosis.tf similarity index 100% rename from technology/scn4me_subm/tf/mosis.tf rename to technology/scn4m_subm/tf/mosis.tf diff --git a/technology/scn4me_subm/mag_lib/.magicrc b/technology/scn4me_subm/mag_lib/.magicrc deleted file mode 100644 index 2778c5e7..00000000 --- a/technology/scn4me_subm/mag_lib/.magicrc +++ /dev/null @@ -1,5 +0,0 @@ -path sys +$::env(OPENRAM_TECH)/scn4me_subm/tech -tech load SCN4ME_SUBM.20 -noprompt -scalegrid 1 4 -set GND gnd -set VDD vdd diff --git a/technology/setup_scripts/setup_openram_scn4m_subm.py b/technology/setup_scripts/setup_openram_scn4m_subm.py new file mode 100644 index 00000000..19a4960c --- /dev/null +++ b/technology/setup_scripts/setup_openram_scn4m_subm.py @@ -0,0 +1,41 @@ +#!/usr/bin/python +""" +This type of setup script should be placed in the setup_scripts directory in the trunk +""" + +import sys +import os + +TECHNOLOGY = "scn4m_subm" + + +########################## +# CDK paths + +# os.environ["CDK_DIR"] = CDK_DIR #PDK path +# os.environ["SYSTEM_CDS_LIB_DIR"] = "{0}/cdssetup".format(CDK_DIR) +# os.environ["CDS_SITE"] = CDK_DIR +os.environ["MGC_TMPDIR"] = "/tmp" + +########################### +# OpenRAM Paths + + +try: + DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME")) +except: + OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) + DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech" +os.environ["DRCLVS_HOME"] = DRCLVS_HOME + +# try: +# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) +# except: +OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) +os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) + +########################## +# Paths required for OPENRAM to function + +LOCAL = "{0}/..".format(os.path.dirname(__file__)) +sys.path.append("{0}/{1}/tech".format(LOCAL,TECHNOLOGY)) From c9806feb01ce72d233dfcffae1e8fc11d5750679 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 12:55:10 -0700 Subject: [PATCH 07/14] Add convert script for mag to gds --- technology/scn3me_subm/mag_lib/convertall.sh | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100755 technology/scn3me_subm/mag_lib/convertall.sh diff --git a/technology/scn3me_subm/mag_lib/convertall.sh b/technology/scn3me_subm/mag_lib/convertall.sh new file mode 100755 index 00000000..f5e2482c --- /dev/null +++ b/technology/scn3me_subm/mag_lib/convertall.sh @@ -0,0 +1,14 @@ +magic -dnull -noconsole << EOF +load dff +gds write dff.gds +load cell_6t +gds write cell_6t.gds +load replica_cell_6t +gds write replica_cell_6t.gds +load sense_amp +gds write sense_amp.gds +load tri_gate +gds write tri_gate.gds +load write_driver +gds write write_driver.gds +EOF From f4389bdd8f64044485a79fd4626bb322b64f7a0e Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 14:12:24 -0700 Subject: [PATCH 08/14] Add extra track spacings in some routes. --- compiler/modules/control_logic.py | 2 +- compiler/modules/hierarchical_predecode.py | 6 +++--- technology/scn3me_subm/tech/tech.py | 2 +- technology/scn4m_subm/tech/tech.py | 4 +--- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 7055797e..78223d5f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -267,7 +267,7 @@ class control_logic(design.design): # Connect the clock rail to the other clock rail in_pos = self.ctrl_dff_inst.get_pin("clk").uc() - mid_pos = in_pos + vector(0,self.m2_pitch) + mid_pos = in_pos + vector(0,2*self.m2_pitch) rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y) self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos]) self.add_via_center(layers=("metal1","via1","metal2"), diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index d0699cc3..cec3a925 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -56,8 +56,8 @@ class hierarchical_predecode(design.design): # x offset for input inverters self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch - # x offset to NAND decoder includes the left rails, mid rails and inverters, plus an extra m2 pitch - self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 1) * self.m2_pitch + # x offset to NAND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches + self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch # x offset to output inverters self.x_off_inv_2 = self.x_off_nand + self.nand.width @@ -78,7 +78,7 @@ class hierarchical_predecode(design.design): invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)] non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)] decode_names = invert_names + non_invert_names - offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, 2*self.m1_width) + offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width) self.decode_rails = self.create_vertical_bus(layer="metal2", pitch=self.m2_pitch, offset=offset, diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index c09e109b..e6bf6da1 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -174,7 +174,7 @@ drc["metal2_enclosure_via2"] = _lambda_ # Not a rule drc["minarea_metal2"] = 0 -# 14.2 Exact size +# 14.1 Exact size drc["minwidth_via2"] = 2*_lambda_ # 14.2 Minimum spacing drc["via2_to_via2"] = 3*_lambda_ diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index a31923ca..fc7440e1 100755 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -189,8 +189,6 @@ drc["metal3_to_metal3"] = 3*_lambda_ drc["metal3_extend_via2"] = _lambda_ # Reserved for asymmetric enclosures drc["metal3_enclosure_via2"] = _lambda_ -# Reserved for asymmetric enclosures -drc["metal2_enclosure_via1"] = _lambda_ # 21.3 Minimum overlap by metal3 drc["metal3_extend_via3"] = _lambda_ # Reserved for asymmetric enclosures @@ -212,7 +210,7 @@ drc["metal4_extend_via3"] = 2*_lambda_ # Reserved for asymmetric enclosures drc["metal4_enclosure_via3"] = 2*_lambda_ # Not a rule -drc["minarea_metal3"] = 0 +drc["minarea_metal4"] = 0 ################################################### ##END DRC/LVS Rules From 4d328c576859870d5d03963fe6a8165c8aa8abe0 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 14:41:15 -0700 Subject: [PATCH 09/14] Fix hspice setuphold golden results --- compiler/tests/21_hspice_setuphold_test.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 80568196..6db67df6 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -35,10 +35,10 @@ class timing_setup_test(openram_test): data = sh.analyze(slews,slews) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'hold_times_HL': [-0.01586914], - 'hold_times_LH': [-0.01586914], - 'setup_times_HL': [0.02685547], - 'setup_times_LH': [0.03295898]} + golden_data = {'hold_times_HL': [-0.0097656], + 'hold_times_LH': [-0.0158691], + 'setup_times_HL': [0.026855499999999997], + 'setup_times_LH': [0.032959]} elif OPTS.tech_name == "scn3me_subm": golden_data = {'hold_times_HL': [-0.15625], 'hold_times_LH': [-0.1257324], From 571dca5d5f53ae52501fd3f56b4eac9b860c780a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 15:15:41 -0700 Subject: [PATCH 10/14] Hard code flatten commands for the unique id precharge array --- compiler/verify/magic.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index a07785d3..55e803b4 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -99,7 +99,10 @@ def write_netgen_script(cell_name, sp_name): f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name)) # This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass # Is there a more elegant way to add this when needed? - f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name)) + f.write("flatten class {{{0}.spice precharge_array_1}}\n".format(cell_name)) + f.write("flatten class {{{0}.spice precharge_array_2}}\n".format(cell_name)) + f.write("flatten class {{{0}.spice precharge_array_3}}\n".format(cell_name)) + f.write("flatten class {{{0}.spice precharge_array_4}}\n".format(cell_name)) f.write("property {{nfet {0}.spice}} remove as ad ps pd\n".format(cell_name)) f.write("property {{pfet {0}.spice}} remove as ad ps pd\n".format(cell_name)) f.write("property {{n {0}}} remove as ad ps pd\n".format(sp_name)) From 93ae7ebd0082acad9aa3fb5168bc479f38eba4c0 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 15:18:30 -0700 Subject: [PATCH 11/14] Specify DRC,LVS,PEX tool for scn4m --- compiler/tests/config_20_scn4m_subm.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/compiler/tests/config_20_scn4m_subm.py b/compiler/tests/config_20_scn4m_subm.py index ca112a97..5715d49f 100644 --- a/compiler/tests/config_20_scn4m_subm.py +++ b/compiler/tests/config_20_scn4m_subm.py @@ -7,3 +7,7 @@ process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" + From bf695f932a13f8783250e317e6107c118bd013c4 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 15:25:29 -0700 Subject: [PATCH 12/14] Change scn3me to scn4m in pipeline regressions --- .gitlab-ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6c8138fd..96e30d2d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,6 +1,6 @@ freepdk45: script: "/home/gitlab-runner/regress_freepdk45.sh" -scn3me_subm: - script: "/home/gitlab-runner/regress_scn3me_subm.sh" +scn4m_subm: + script: "/home/gitlab-runner/regress_scn4m_subm.sh" From e591176211a68326eea907945c0e72f5f9f9a3ef Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 15:26:03 -0700 Subject: [PATCH 13/14] Change default to scn4m --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 7a7d0098..6d5e9b63 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -59,7 +59,7 @@ def parse_args(): OPTS.tech_name = "scmos" # Alias SCMOS to AMI 0.5um if OPTS.tech_name == "scmos": - OPTS.tech_name = "scn3me_subm" + OPTS.tech_name = "scn4m_subm" return (options, args) From a58b1906adc5a25e495bff9d808b972902d00cea Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 17 Sep 2018 10:03:55 -0700 Subject: [PATCH 14/14] Convert unit tests to scn4m_subm Also, fixed isdiff for python3. --- compiler/tests/21_hspice_delay_test.py | 20 +- compiler/tests/21_hspice_setuphold_test.py | 10 +- compiler/tests/21_ngspice_delay_test.py | 20 +- compiler/tests/21_ngspice_setuphold_test.py | 10 +- .../tests/golden/sram_2_16_1_scn4m_subm.lef | 5533 +++++++++++++++++ .../tests/golden/sram_2_16_1_scn4m_subm.sp | 681 ++ .../tests/golden/sram_2_16_1_scn4m_subm.v | 47 + .../sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 318 + ...16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 318 + ...m_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 318 + compiler/tests/testutils.py | 16 +- 11 files changed, 7255 insertions(+), 36 deletions(-) create mode 100644 compiler/tests/golden/sram_2_16_1_scn4m_subm.lef create mode 100644 compiler/tests/golden/sram_2_16_1_scn4m_subm.sp create mode 100644 compiler/tests/golden/sram_2_16_1_scn4m_subm.v create mode 100644 compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib create mode 100644 compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib create mode 100644 compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 74db4757..da59c447 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -62,17 +62,17 @@ class timing_sram_test(openram_test): 'slew_lh0': [0.0236264], 'write0_power0': [0.06545659999999999], 'write1_power0': [0.057846299999999996]} - elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl0': [4.0249], - 'delay_lh0': [2.2611], - 'leakage_power': 0.0257389, + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'delay_hl0': [3.452], + 'delay_lh0': [1.3792000000000002], + 'leakage_power': 0.0257065, 'min_period': 4.688, - 'read0_power0': [24.9279], - 'read1_power0': [24.0219], - 'slew_hl0': [0.8500753999999999], - 'slew_lh0': [0.4122653], - 'write0_power0': [28.197600000000005], - 'write1_power0': [25.685]} + 'read0_power0': [15.0755], + 'read1_power0': [14.4526], + 'slew_hl0': [0.6137363], + 'slew_lh0': [0.3381045], + 'write0_power0': [16.9203], + 'write1_power0': [15.367]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 6db67df6..2969f95e 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -39,11 +39,11 @@ class timing_setup_test(openram_test): 'hold_times_LH': [-0.0158691], 'setup_times_HL': [0.026855499999999997], 'setup_times_LH': [0.032959]} - elif OPTS.tech_name == "scn3me_subm": - golden_data = {'hold_times_HL': [-0.15625], - 'hold_times_LH': [-0.1257324], - 'setup_times_HL': [0.2038574], - 'setup_times_LH': [0.2893066]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'hold_times_HL': [-0.0891113], + 'hold_times_LH': [-0.0769043], + 'setup_times_HL': [0.1184082], + 'setup_times_LH': [0.1733398]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index ca873339..cf7f096b 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -61,17 +61,17 @@ class timing_sram_test(openram_test): 'slew_lh0': [0.025474979999999998], 'write0_power0': [0.06513271999999999], 'write1_power0': [0.058057000000000004]} - elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl0': [4.221382999999999], - 'delay_lh0': [2.6459520000000003], - 'leakage_power': 0.0013865260000000001, + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'delay_hl0': [3.644147], + 'delay_lh0': [1.629815], + 'leakage_power': 0.0009299118999999999, 'min_period': 4.688, - 'read0_power0': [26.699669999999998], - 'read1_power0': [26.13123], - 'slew_hl0': [0.9821776000000001], - 'slew_lh0': [1.5791520000000001], - 'write0_power0': [30.71939], - 'write1_power0': [27.44753]} + 'read0_power0': [16.28732], + 'read1_power0': [15.75155], + 'slew_hl0': [0.6722473], + 'slew_lh0': [0.3386347], + 'write0_power0': [18.545450000000002], + 'write1_power0': [16.81084]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index df8c60de..d86fcb23 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -39,11 +39,11 @@ class timing_setup_test(openram_test): 'hold_times_LH': [-0.01586914], 'setup_times_HL': [0.02685547], 'setup_times_LH': [0.03295898]} - elif OPTS.tech_name == "scn3me_subm": - golden_data = {'hold_times_HL': [-0.15625], - 'hold_times_LH': [-0.1257324], - 'setup_times_HL': [0.2038574], - 'setup_times_LH': [0.2893066]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'hold_times_HL': [-0.08911132999999999], + 'hold_times_LH': [-0.0769043], + 'setup_times_HL': [0.1184082], + 'setup_times_LH': [0.1672363]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.lef b/compiler/tests/golden/sram_2_16_1_scn4m_subm.lef new file mode 100644 index 00000000..9d784677 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.lef @@ -0,0 +1,5533 @@ +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS +SITE MacroSite + CLASS Core ; + SIZE 148050.0 by 461850.0 ; +END MacroSite +MACRO sram_2_16_1_scn3me_subm + CLASS BLOCK ; + SIZE 148050.0 BY 461850.0 ; + SYMMETRY X Y R90 ; + SITE MacroSite ; + PIN DATA[0] + DIRECTION INOUT ; + PORT + LAYER metal2 ; + RECT 120900.0 0.0 121800.0 1800.0 ; + END + END DATA[0] + PIN DATA[1] + DIRECTION INOUT ; + PORT + LAYER metal2 ; + RECT 131100.0 0.0 132000.0 1800.0 ; + END + END DATA[1] + PIN ADDR[0] + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT 0.0 87600.0 10800.0 89100.0 ; + END + END ADDR[0] + PIN ADDR[1] + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT 0.0 77400.0 10800.0 78900.0 ; + END + END ADDR[1] + PIN ADDR[2] + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT 0.0 67200.0 10800.0 68700.0 ; + END + END ADDR[2] + PIN ADDR[3] + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT 0.0 57000.0 10800.0 58500.0 ; + END + END ADDR[3] + PIN CSb + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT -38400.0 182700.0 -36600.0 184500.0 ; + END + END CSb + PIN WEb + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT -28200.0 182700.0 -26400.0 184500.0 ; + END + END WEb + PIN OEb + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT -48600.0 182700.0 -46800.0 184500.0 ; + END + END OEb + PIN clk + DIRECTION INPUT ; + PORT + LAYER metal1 ; + RECT -10200.0 181800.0 -9000.0 185400.0 ; + END + END clk + PIN vdd + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal2 ; + RECT 4950.0 0.0 8550.0 461850.0 ; + LAYER metal2 ; + RECT 144450.0 0.0 148050.0 461850.0 ; + LAYER metal1 ; + RECT 0.0 4950.0 148050.0 8550.0 ; + LAYER metal1 ; + RECT 0.0 458250.0 148050.0 461850.0 ; + END + END vdd + PIN gnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal2 ; + RECT 0.0 0.0 3600.0 461850.0 ; + LAYER metal2 ; + RECT 139500.0 0.0 143100.0 461850.0 ; + LAYER metal1 ; + RECT 0.0 0.0 148050.0 3600.0 ; + LAYER metal1 ; + RECT 0.0 453300.0 148050.0 456900.0 ; + END + END gnd + OBS + LAYER metal1 ; + RECT 48300.0 215550.0 49200.0 216450.0 ; + RECT 48300.0 213150.0 49200.0 214050.0 ; + RECT 46950.0 215550.0 48750.0 216450.0 ; + RECT 48300.0 213600.0 49200.0 216000.0 ; + RECT 48750.0 213150.0 50700.0 214050.0 ; + RECT 100800.0 215550.0 101700.0 216450.0 ; + RECT 100800.0 211050.0 101700.0 211950.0 ; + RECT 86850.0 215550.0 101250.0 216450.0 ; + RECT 100800.0 211500.0 101700.0 216000.0 ; + RECT 101250.0 211050.0 115800.0 211950.0 ; + RECT 48300.0 229950.0 49200.0 230850.0 ; + RECT 48300.0 232350.0 49200.0 233250.0 ; + RECT 46950.0 229950.0 48750.0 230850.0 ; + RECT 48300.0 230400.0 49200.0 232800.0 ; + RECT 48750.0 232350.0 50700.0 233250.0 ; + RECT 100800.0 229950.0 101700.0 230850.0 ; + RECT 100800.0 234450.0 101700.0 235350.0 ; + RECT 86850.0 229950.0 101250.0 230850.0 ; + RECT 100800.0 230400.0 101700.0 234900.0 ; + RECT 101250.0 234450.0 115800.0 235350.0 ; + RECT 48300.0 243150.0 49200.0 244050.0 ; + RECT 48300.0 240750.0 49200.0 241650.0 ; + RECT 46950.0 243150.0 48750.0 244050.0 ; + RECT 48300.0 241200.0 49200.0 243600.0 ; + RECT 48750.0 240750.0 50700.0 241650.0 ; + RECT 100800.0 243150.0 101700.0 244050.0 ; + RECT 100800.0 238650.0 101700.0 239550.0 ; + RECT 86850.0 243150.0 101250.0 244050.0 ; + RECT 100800.0 239100.0 101700.0 243600.0 ; + RECT 101250.0 238650.0 115800.0 239550.0 ; + RECT 48300.0 257550.0 49200.0 258450.0 ; + RECT 48300.0 259950.0 49200.0 260850.0 ; + RECT 46950.0 257550.0 48750.0 258450.0 ; + RECT 48300.0 258000.0 49200.0 260400.0 ; + RECT 48750.0 259950.0 50700.0 260850.0 ; + RECT 100800.0 257550.0 101700.0 258450.0 ; + RECT 100800.0 262050.0 101700.0 262950.0 ; + RECT 86850.0 257550.0 101250.0 258450.0 ; + RECT 100800.0 258000.0 101700.0 262500.0 ; + RECT 101250.0 262050.0 115800.0 262950.0 ; + RECT 48300.0 270750.0 49200.0 271650.0 ; + RECT 48300.0 268350.0 49200.0 269250.0 ; + RECT 46950.0 270750.0 48750.0 271650.0 ; + RECT 48300.0 268800.0 49200.0 271200.0 ; + RECT 48750.0 268350.0 50700.0 269250.0 ; + RECT 100800.0 270750.0 101700.0 271650.0 ; + RECT 100800.0 266250.0 101700.0 267150.0 ; + RECT 86850.0 270750.0 101250.0 271650.0 ; + RECT 100800.0 266700.0 101700.0 271200.0 ; + RECT 101250.0 266250.0 115800.0 267150.0 ; + RECT 48300.0 285150.0 49200.0 286050.0 ; + RECT 48300.0 287550.0 49200.0 288450.0 ; + RECT 46950.0 285150.0 48750.0 286050.0 ; + RECT 48300.0 285600.0 49200.0 288000.0 ; + RECT 48750.0 287550.0 50700.0 288450.0 ; + RECT 100800.0 285150.0 101700.0 286050.0 ; + RECT 100800.0 289650.0 101700.0 290550.0 ; + RECT 86850.0 285150.0 101250.0 286050.0 ; + RECT 100800.0 285600.0 101700.0 290100.0 ; + RECT 101250.0 289650.0 115800.0 290550.0 ; + RECT 48300.0 298350.0 49200.0 299250.0 ; + RECT 48300.0 295950.0 49200.0 296850.0 ; + RECT 46950.0 298350.0 48750.0 299250.0 ; + RECT 48300.0 296400.0 49200.0 298800.0 ; + RECT 48750.0 295950.0 50700.0 296850.0 ; + RECT 100800.0 298350.0 101700.0 299250.0 ; + RECT 100800.0 293850.0 101700.0 294750.0 ; + RECT 86850.0 298350.0 101250.0 299250.0 ; + RECT 100800.0 294300.0 101700.0 298800.0 ; + RECT 101250.0 293850.0 115800.0 294750.0 ; + RECT 48300.0 312750.0 49200.0 313650.0 ; + RECT 48300.0 315150.0 49200.0 316050.0 ; + RECT 46950.0 312750.0 48750.0 313650.0 ; + RECT 48300.0 313200.0 49200.0 315600.0 ; + RECT 48750.0 315150.0 50700.0 316050.0 ; + RECT 100800.0 312750.0 101700.0 313650.0 ; + RECT 100800.0 317250.0 101700.0 318150.0 ; + RECT 86850.0 312750.0 101250.0 313650.0 ; + RECT 100800.0 313200.0 101700.0 317700.0 ; + RECT 101250.0 317250.0 115800.0 318150.0 ; + RECT 48300.0 325950.0 49200.0 326850.0 ; + RECT 48300.0 323550.0 49200.0 324450.0 ; + RECT 46950.0 325950.0 48750.0 326850.0 ; + RECT 48300.0 324000.0 49200.0 326400.0 ; + RECT 48750.0 323550.0 50700.0 324450.0 ; + RECT 100800.0 325950.0 101700.0 326850.0 ; + RECT 100800.0 321450.0 101700.0 322350.0 ; + RECT 86850.0 325950.0 101250.0 326850.0 ; + RECT 100800.0 321900.0 101700.0 326400.0 ; + RECT 101250.0 321450.0 115800.0 322350.0 ; + RECT 48300.0 340350.0 49200.0 341250.0 ; + RECT 48300.0 342750.0 49200.0 343650.0 ; + RECT 46950.0 340350.0 48750.0 341250.0 ; + RECT 48300.0 340800.0 49200.0 343200.0 ; + RECT 48750.0 342750.0 50700.0 343650.0 ; + RECT 100800.0 340350.0 101700.0 341250.0 ; + RECT 100800.0 344850.0 101700.0 345750.0 ; + RECT 86850.0 340350.0 101250.0 341250.0 ; + RECT 100800.0 340800.0 101700.0 345300.0 ; + RECT 101250.0 344850.0 115800.0 345750.0 ; + RECT 48300.0 353550.0 49200.0 354450.0 ; + RECT 48300.0 351150.0 49200.0 352050.0 ; + RECT 46950.0 353550.0 48750.0 354450.0 ; + RECT 48300.0 351600.0 49200.0 354000.0 ; + RECT 48750.0 351150.0 50700.0 352050.0 ; + RECT 100800.0 353550.0 101700.0 354450.0 ; + RECT 100800.0 349050.0 101700.0 349950.0 ; + RECT 86850.0 353550.0 101250.0 354450.0 ; + RECT 100800.0 349500.0 101700.0 354000.0 ; + RECT 101250.0 349050.0 115800.0 349950.0 ; + RECT 48300.0 367950.0 49200.0 368850.0 ; + RECT 48300.0 370350.0 49200.0 371250.0 ; + RECT 46950.0 367950.0 48750.0 368850.0 ; + RECT 48300.0 368400.0 49200.0 370800.0 ; + RECT 48750.0 370350.0 50700.0 371250.0 ; + RECT 100800.0 367950.0 101700.0 368850.0 ; + RECT 100800.0 372450.0 101700.0 373350.0 ; + RECT 86850.0 367950.0 101250.0 368850.0 ; + RECT 100800.0 368400.0 101700.0 372900.0 ; + RECT 101250.0 372450.0 115800.0 373350.0 ; + RECT 48300.0 381150.0 49200.0 382050.0 ; + RECT 48300.0 378750.0 49200.0 379650.0 ; + RECT 46950.0 381150.0 48750.0 382050.0 ; + RECT 48300.0 379200.0 49200.0 381600.0 ; + RECT 48750.0 378750.0 50700.0 379650.0 ; + RECT 100800.0 381150.0 101700.0 382050.0 ; + RECT 100800.0 376650.0 101700.0 377550.0 ; + RECT 86850.0 381150.0 101250.0 382050.0 ; + RECT 100800.0 377100.0 101700.0 381600.0 ; + RECT 101250.0 376650.0 115800.0 377550.0 ; + RECT 48300.0 395550.0 49200.0 396450.0 ; + RECT 48300.0 397950.0 49200.0 398850.0 ; + RECT 46950.0 395550.0 48750.0 396450.0 ; + RECT 48300.0 396000.0 49200.0 398400.0 ; + RECT 48750.0 397950.0 50700.0 398850.0 ; + RECT 100800.0 395550.0 101700.0 396450.0 ; + RECT 100800.0 400050.0 101700.0 400950.0 ; + RECT 86850.0 395550.0 101250.0 396450.0 ; + RECT 100800.0 396000.0 101700.0 400500.0 ; + RECT 101250.0 400050.0 115800.0 400950.0 ; + RECT 48300.0 408750.0 49200.0 409650.0 ; + RECT 48300.0 406350.0 49200.0 407250.0 ; + RECT 46950.0 408750.0 48750.0 409650.0 ; + RECT 48300.0 406800.0 49200.0 409200.0 ; + RECT 48750.0 406350.0 50700.0 407250.0 ; + RECT 100800.0 408750.0 101700.0 409650.0 ; + RECT 100800.0 404250.0 101700.0 405150.0 ; + RECT 86850.0 408750.0 101250.0 409650.0 ; + RECT 100800.0 404700.0 101700.0 409200.0 ; + RECT 101250.0 404250.0 115800.0 405150.0 ; + RECT 48300.0 423150.0 49200.0 424050.0 ; + RECT 48300.0 425550.0 49200.0 426450.0 ; + RECT 46950.0 423150.0 48750.0 424050.0 ; + RECT 48300.0 423600.0 49200.0 426000.0 ; + RECT 48750.0 425550.0 50700.0 426450.0 ; + RECT 100800.0 423150.0 101700.0 424050.0 ; + RECT 100800.0 427650.0 101700.0 428550.0 ; + RECT 86850.0 423150.0 101250.0 424050.0 ; + RECT 100800.0 423600.0 101700.0 428100.0 ; + RECT 101250.0 427650.0 115800.0 428550.0 ; + RECT 81300.0 101250.0 85800.0 102150.0 ; + RECT 78300.0 115050.0 88500.0 115950.0 ; + RECT 81300.0 156450.0 91200.0 157350.0 ; + RECT 78300.0 170250.0 93900.0 171150.0 ; + RECT 1800.0 98550.0 81300.0 99450.0 ; + RECT 1800.0 126150.0 81300.0 127050.0 ; + RECT 1800.0 153750.0 81300.0 154650.0 ; + RECT 1800.0 181350.0 81300.0 182250.0 ; + RECT 6750.0 112350.0 81300.0 113250.0 ; + RECT 6750.0 139950.0 81300.0 140850.0 ; + RECT 6750.0 167550.0 81300.0 168450.0 ; + RECT 6750.0 195150.0 81300.0 196050.0 ; + RECT 68700.0 87300.0 85800.0 88200.0 ; + RECT 68700.0 78600.0 88500.0 79500.0 ; + RECT 68700.0 66900.0 91200.0 67800.0 ; + RECT 68700.0 58200.0 93900.0 59100.0 ; + RECT 1800.0 82950.0 9900.0 83850.0 ; + RECT 1800.0 62550.0 9900.0 63450.0 ; + RECT 66300.0 50250.0 67200.0 51150.0 ; + RECT 66300.0 50700.0 67200.0 52800.0 ; + RECT 6750.0 50250.0 66750.0 51150.0 ; + RECT 104700.0 42300.0 116400.0 43200.0 ; + RECT 99300.0 37800.0 116400.0 38700.0 ; + RECT 102000.0 35400.0 116400.0 36300.0 ; + RECT 104700.0 438600.0 116400.0 439500.0 ; + RECT 107400.0 107100.0 116400.0 108000.0 ; + RECT 110100.0 205200.0 116400.0 206100.0 ; + RECT 12300.0 95250.0 13200.0 96150.0 ; + RECT 12300.0 93600.0 13200.0 95700.0 ; + RECT 12750.0 95250.0 96600.0 96150.0 ; + RECT 53850.0 431850.0 97500.0 432750.0 ; + RECT 116400.0 449700.0 146250.0 450600.0 ; + RECT 116400.0 177900.0 146250.0 178800.0 ; + RECT 116400.0 109200.0 146250.0 110100.0 ; + RECT 116400.0 96300.0 146250.0 97200.0 ; + RECT 116400.0 19500.0 146250.0 20400.0 ; + RECT 6750.0 222750.0 146250.0 223650.0 ; + RECT 6750.0 250350.0 146250.0 251250.0 ; + RECT 6750.0 277950.0 146250.0 278850.0 ; + RECT 6750.0 305550.0 146250.0 306450.0 ; + RECT 6750.0 333150.0 146250.0 334050.0 ; + RECT 6750.0 360750.0 146250.0 361650.0 ; + RECT 6750.0 388350.0 146250.0 389250.0 ; + RECT 6750.0 415950.0 146250.0 416850.0 ; + RECT 116400.0 33300.0 143100.0 34200.0 ; + RECT 116400.0 203100.0 143100.0 204000.0 ; + RECT 116400.0 105000.0 143100.0 105900.0 ; + RECT 1800.0 208950.0 57000.0 209850.0 ; + RECT 1800.0 236550.0 57000.0 237450.0 ; + RECT 1800.0 264150.0 57000.0 265050.0 ; + RECT 1800.0 291750.0 57000.0 292650.0 ; + RECT 1800.0 319350.0 57000.0 320250.0 ; + RECT 1800.0 346950.0 57000.0 347850.0 ; + RECT 1800.0 374550.0 57000.0 375450.0 ; + RECT 1800.0 402150.0 57000.0 403050.0 ; + RECT 1800.0 429750.0 57000.0 430650.0 ; + RECT 116400.0 209400.0 126600.0 223200.0 ; + RECT 116400.0 237000.0 126600.0 223200.0 ; + RECT 116400.0 237000.0 126600.0 250800.0 ; + RECT 116400.0 264600.0 126600.0 250800.0 ; + RECT 116400.0 264600.0 126600.0 278400.0 ; + RECT 116400.0 292200.0 126600.0 278400.0 ; + RECT 116400.0 292200.0 126600.0 306000.0 ; + RECT 116400.0 319800.0 126600.0 306000.0 ; + RECT 116400.0 319800.0 126600.0 333600.0 ; + RECT 116400.0 347400.0 126600.0 333600.0 ; + RECT 116400.0 347400.0 126600.0 361200.0 ; + RECT 116400.0 375000.0 126600.0 361200.0 ; + RECT 116400.0 375000.0 126600.0 388800.0 ; + RECT 116400.0 402600.0 126600.0 388800.0 ; + RECT 116400.0 402600.0 126600.0 416400.0 ; + RECT 116400.0 430200.0 126600.0 416400.0 ; + RECT 126600.0 209400.0 136800.0 223200.0 ; + RECT 126600.0 237000.0 136800.0 223200.0 ; + RECT 126600.0 237000.0 136800.0 250800.0 ; + RECT 126600.0 264600.0 136800.0 250800.0 ; + RECT 126600.0 264600.0 136800.0 278400.0 ; + RECT 126600.0 292200.0 136800.0 278400.0 ; + RECT 126600.0 292200.0 136800.0 306000.0 ; + RECT 126600.0 319800.0 136800.0 306000.0 ; + RECT 126600.0 319800.0 136800.0 333600.0 ; + RECT 126600.0 347400.0 136800.0 333600.0 ; + RECT 126600.0 347400.0 136800.0 361200.0 ; + RECT 126600.0 375000.0 136800.0 361200.0 ; + RECT 126600.0 375000.0 136800.0 388800.0 ; + RECT 126600.0 402600.0 136800.0 388800.0 ; + RECT 126600.0 402600.0 136800.0 416400.0 ; + RECT 126600.0 430200.0 136800.0 416400.0 ; + RECT 115800.0 210900.0 137400.0 212100.0 ; + RECT 115800.0 234300.0 137400.0 235500.0 ; + RECT 115800.0 238500.0 137400.0 239700.0 ; + RECT 115800.0 261900.0 137400.0 263100.0 ; + RECT 115800.0 266100.0 137400.0 267300.0 ; + RECT 115800.0 289500.0 137400.0 290700.0 ; + RECT 115800.0 293700.0 137400.0 294900.0 ; + RECT 115800.0 317100.0 137400.0 318300.0 ; + RECT 115800.0 321300.0 137400.0 322500.0 ; + RECT 115800.0 344700.0 137400.0 345900.0 ; + RECT 115800.0 348900.0 137400.0 350100.0 ; + RECT 115800.0 372300.0 137400.0 373500.0 ; + RECT 115800.0 376500.0 137400.0 377700.0 ; + RECT 115800.0 399900.0 137400.0 401100.0 ; + RECT 115800.0 404100.0 137400.0 405300.0 ; + RECT 115800.0 427500.0 137400.0 428700.0 ; + RECT 115800.0 222600.0 137400.0 223500.0 ; + RECT 115800.0 250200.0 137400.0 251100.0 ; + RECT 115800.0 277800.0 137400.0 278700.0 ; + RECT 115800.0 305400.0 137400.0 306300.0 ; + RECT 115800.0 333000.0 137400.0 333900.0 ; + RECT 115800.0 360600.0 137400.0 361500.0 ; + RECT 115800.0 388200.0 137400.0 389100.0 ; + RECT 115800.0 415800.0 137400.0 416700.0 ; + RECT 121800.0 443400.0 123000.0 450600.0 ; + RECT 119400.0 436200.0 120600.0 437400.0 ; + RECT 121800.0 436200.0 123000.0 437400.0 ; + RECT 121800.0 436200.0 123000.0 437400.0 ; + RECT 119400.0 436200.0 120600.0 437400.0 ; + RECT 119400.0 443400.0 120600.0 444600.0 ; + RECT 121800.0 443400.0 123000.0 444600.0 ; + RECT 121800.0 443400.0 123000.0 444600.0 ; + RECT 119400.0 443400.0 120600.0 444600.0 ; + RECT 121800.0 443400.0 123000.0 444600.0 ; + RECT 124200.0 443400.0 125400.0 444600.0 ; + RECT 124200.0 443400.0 125400.0 444600.0 ; + RECT 121800.0 443400.0 123000.0 444600.0 ; + RECT 121500.0 438450.0 120300.0 439650.0 ; + RECT 121800.0 448800.0 123000.0 450000.0 ; + RECT 119400.0 436200.0 120600.0 437400.0 ; + RECT 121800.0 436200.0 123000.0 437400.0 ; + RECT 119400.0 443400.0 120600.0 444600.0 ; + RECT 124200.0 443400.0 125400.0 444600.0 ; + RECT 116400.0 438600.0 126600.0 439500.0 ; + RECT 116400.0 449700.0 126600.0 450600.0 ; + RECT 132000.0 443400.0 133200.0 450600.0 ; + RECT 129600.0 436200.0 130800.0 437400.0 ; + RECT 132000.0 436200.0 133200.0 437400.0 ; + RECT 132000.0 436200.0 133200.0 437400.0 ; + RECT 129600.0 436200.0 130800.0 437400.0 ; + RECT 129600.0 443400.0 130800.0 444600.0 ; + RECT 132000.0 443400.0 133200.0 444600.0 ; + RECT 132000.0 443400.0 133200.0 444600.0 ; + RECT 129600.0 443400.0 130800.0 444600.0 ; + RECT 132000.0 443400.0 133200.0 444600.0 ; + RECT 134400.0 443400.0 135600.0 444600.0 ; + RECT 134400.0 443400.0 135600.0 444600.0 ; + RECT 132000.0 443400.0 133200.0 444600.0 ; + RECT 131700.0 438450.0 130500.0 439650.0 ; + RECT 132000.0 448800.0 133200.0 450000.0 ; + RECT 129600.0 436200.0 130800.0 437400.0 ; + RECT 132000.0 436200.0 133200.0 437400.0 ; + RECT 129600.0 443400.0 130800.0 444600.0 ; + RECT 134400.0 443400.0 135600.0 444600.0 ; + RECT 126600.0 438600.0 136800.0 439500.0 ; + RECT 126600.0 449700.0 136800.0 450600.0 ; + RECT 116400.0 438600.0 136800.0 439500.0 ; + RECT 116400.0 449700.0 136800.0 450600.0 ; + RECT 116400.0 160500.0 126600.0 209400.0 ; + RECT 126600.0 160500.0 136800.0 209400.0 ; + RECT 116400.0 205200.0 136800.0 206100.0 ; + RECT 116400.0 177900.0 136800.0 178800.0 ; + RECT 116400.0 203100.0 136800.0 204000.0 ; + RECT 116400.0 99900.0 126600.0 160500.0 ; + RECT 126600.0 99900.0 136800.0 160500.0 ; + RECT 116400.0 107100.0 136800.0 108000.0 ; + RECT 116400.0 109200.0 136800.0 110100.0 ; + RECT 116400.0 105000.0 136800.0 105900.0 ; + RECT 116400.0 39900.0 126600.0 99900.0 ; + RECT 136800.0 39900.0 126600.0 99900.0 ; + RECT 116400.0 42300.0 136800.0 43200.0 ; + RECT 116400.0 96300.0 136800.0 97200.0 ; + RECT 116400.0 39900.0 126600.0 18000.0 ; + RECT 126600.0 39900.0 136800.0 18000.0 ; + RECT 116400.0 36300.0 136800.0 35400.0 ; + RECT 116400.0 38700.0 136800.0 37800.0 ; + RECT 116400.0 20400.0 136800.0 19500.0 ; + RECT 116400.0 34200.0 136800.0 33300.0 ; + RECT 38550.0 216750.0 39450.0 217650.0 ; + RECT 38550.0 215550.0 39450.0 216450.0 ; + RECT 34500.0 216750.0 39000.0 217650.0 ; + RECT 38550.0 216000.0 39450.0 217200.0 ; + RECT 39000.0 215550.0 43500.0 216450.0 ; + RECT 38550.0 228750.0 39450.0 229650.0 ; + RECT 38550.0 229950.0 39450.0 230850.0 ; + RECT 34500.0 228750.0 39000.0 229650.0 ; + RECT 38550.0 229200.0 39450.0 230400.0 ; + RECT 39000.0 229950.0 43500.0 230850.0 ; + RECT 38550.0 244350.0 39450.0 245250.0 ; + RECT 38550.0 243150.0 39450.0 244050.0 ; + RECT 34500.0 244350.0 39000.0 245250.0 ; + RECT 38550.0 243600.0 39450.0 244800.0 ; + RECT 39000.0 243150.0 43500.0 244050.0 ; + RECT 38550.0 256350.0 39450.0 257250.0 ; + RECT 38550.0 257550.0 39450.0 258450.0 ; + RECT 34500.0 256350.0 39000.0 257250.0 ; + RECT 38550.0 256800.0 39450.0 258000.0 ; + RECT 39000.0 257550.0 43500.0 258450.0 ; + RECT 38550.0 271950.0 39450.0 272850.0 ; + RECT 38550.0 270750.0 39450.0 271650.0 ; + RECT 34500.0 271950.0 39000.0 272850.0 ; + RECT 38550.0 271200.0 39450.0 272400.0 ; + RECT 39000.0 270750.0 43500.0 271650.0 ; + RECT 38550.0 283950.0 39450.0 284850.0 ; + RECT 38550.0 285150.0 39450.0 286050.0 ; + RECT 34500.0 283950.0 39000.0 284850.0 ; + RECT 38550.0 284400.0 39450.0 285600.0 ; + RECT 39000.0 285150.0 43500.0 286050.0 ; + RECT 38550.0 299550.0 39450.0 300450.0 ; + RECT 38550.0 298350.0 39450.0 299250.0 ; + RECT 34500.0 299550.0 39000.0 300450.0 ; + RECT 38550.0 298800.0 39450.0 300000.0 ; + RECT 39000.0 298350.0 43500.0 299250.0 ; + RECT 38550.0 311550.0 39450.0 312450.0 ; + RECT 38550.0 312750.0 39450.0 313650.0 ; + RECT 34500.0 311550.0 39000.0 312450.0 ; + RECT 38550.0 312000.0 39450.0 313200.0 ; + RECT 39000.0 312750.0 43500.0 313650.0 ; + RECT 38550.0 327150.0 39450.0 328050.0 ; + RECT 38550.0 325950.0 39450.0 326850.0 ; + RECT 34500.0 327150.0 39000.0 328050.0 ; + RECT 38550.0 326400.0 39450.0 327600.0 ; + RECT 39000.0 325950.0 43500.0 326850.0 ; + RECT 38550.0 339150.0 39450.0 340050.0 ; + RECT 38550.0 340350.0 39450.0 341250.0 ; + RECT 34500.0 339150.0 39000.0 340050.0 ; + RECT 38550.0 339600.0 39450.0 340800.0 ; + RECT 39000.0 340350.0 43500.0 341250.0 ; + RECT 38550.0 354750.0 39450.0 355650.0 ; + RECT 38550.0 353550.0 39450.0 354450.0 ; + RECT 34500.0 354750.0 39000.0 355650.0 ; + RECT 38550.0 354000.0 39450.0 355200.0 ; + RECT 39000.0 353550.0 43500.0 354450.0 ; + RECT 38550.0 366750.0 39450.0 367650.0 ; + RECT 38550.0 367950.0 39450.0 368850.0 ; + RECT 34500.0 366750.0 39000.0 367650.0 ; + RECT 38550.0 367200.0 39450.0 368400.0 ; + RECT 39000.0 367950.0 43500.0 368850.0 ; + RECT 38550.0 382350.0 39450.0 383250.0 ; + RECT 38550.0 381150.0 39450.0 382050.0 ; + RECT 34500.0 382350.0 39000.0 383250.0 ; + RECT 38550.0 381600.0 39450.0 382800.0 ; + RECT 39000.0 381150.0 43500.0 382050.0 ; + RECT 38550.0 394350.0 39450.0 395250.0 ; + RECT 38550.0 395550.0 39450.0 396450.0 ; + RECT 34500.0 394350.0 39000.0 395250.0 ; + RECT 38550.0 394800.0 39450.0 396000.0 ; + RECT 39000.0 395550.0 43500.0 396450.0 ; + RECT 38550.0 409950.0 39450.0 410850.0 ; + RECT 38550.0 408750.0 39450.0 409650.0 ; + RECT 34500.0 409950.0 39000.0 410850.0 ; + RECT 38550.0 409200.0 39450.0 410400.0 ; + RECT 39000.0 408750.0 43500.0 409650.0 ; + RECT 38550.0 421950.0 39450.0 422850.0 ; + RECT 38550.0 423150.0 39450.0 424050.0 ; + RECT 34500.0 421950.0 39000.0 422850.0 ; + RECT 38550.0 422400.0 39450.0 423600.0 ; + RECT 39000.0 423150.0 43500.0 424050.0 ; + RECT 10350.0 105150.0 26700.0 106050.0 ; + RECT 12450.0 119550.0 26700.0 120450.0 ; + RECT 14550.0 132750.0 26700.0 133650.0 ; + RECT 16650.0 147150.0 26700.0 148050.0 ; + RECT 18750.0 160350.0 26700.0 161250.0 ; + RECT 20850.0 174750.0 26700.0 175650.0 ; + RECT 22950.0 187950.0 26700.0 188850.0 ; + RECT 25050.0 202350.0 26700.0 203250.0 ; + RECT 10350.0 216750.0 29100.0 217650.0 ; + RECT 18750.0 214050.0 32100.0 214950.0 ; + RECT 10350.0 228750.0 29100.0 229650.0 ; + RECT 20850.0 231450.0 32100.0 232350.0 ; + RECT 10350.0 244350.0 29100.0 245250.0 ; + RECT 22950.0 241650.0 32100.0 242550.0 ; + RECT 10350.0 256350.0 29100.0 257250.0 ; + RECT 25050.0 259050.0 32100.0 259950.0 ; + RECT 12450.0 271950.0 29100.0 272850.0 ; + RECT 18750.0 269250.0 32100.0 270150.0 ; + RECT 12450.0 283950.0 29100.0 284850.0 ; + RECT 20850.0 286650.0 32100.0 287550.0 ; + RECT 12450.0 299550.0 29100.0 300450.0 ; + RECT 22950.0 296850.0 32100.0 297750.0 ; + RECT 12450.0 311550.0 29100.0 312450.0 ; + RECT 25050.0 314250.0 32100.0 315150.0 ; + RECT 14550.0 327150.0 29100.0 328050.0 ; + RECT 18750.0 324450.0 32100.0 325350.0 ; + RECT 14550.0 339150.0 29100.0 340050.0 ; + RECT 20850.0 341850.0 32100.0 342750.0 ; + RECT 14550.0 354750.0 29100.0 355650.0 ; + RECT 22950.0 352050.0 32100.0 352950.0 ; + RECT 14550.0 366750.0 29100.0 367650.0 ; + RECT 25050.0 369450.0 32100.0 370350.0 ; + RECT 16650.0 382350.0 29100.0 383250.0 ; + RECT 18750.0 379650.0 32100.0 380550.0 ; + RECT 16650.0 394350.0 29100.0 395250.0 ; + RECT 20850.0 397050.0 32100.0 397950.0 ; + RECT 16650.0 409950.0 29100.0 410850.0 ; + RECT 22950.0 407250.0 32100.0 408150.0 ; + RECT 16650.0 421950.0 29100.0 422850.0 ; + RECT 25050.0 424650.0 32100.0 425550.0 ; + RECT 65250.0 105150.0 64350.0 106050.0 ; + RECT 65250.0 109650.0 64350.0 110550.0 ; + RECT 69450.0 105150.0 64800.0 106050.0 ; + RECT 65250.0 105600.0 64350.0 110100.0 ; + RECT 64800.0 109650.0 62250.0 110550.0 ; + RECT 80850.0 105150.0 72900.0 106050.0 ; + RECT 65250.0 119550.0 64350.0 120450.0 ; + RECT 65250.0 123450.0 64350.0 124350.0 ; + RECT 69450.0 119550.0 64800.0 120450.0 ; + RECT 65250.0 120000.0 64350.0 123900.0 ; + RECT 64800.0 123450.0 59250.0 124350.0 ; + RECT 77850.0 119550.0 72900.0 120450.0 ; + RECT 80850.0 128250.0 56250.0 129150.0 ; + RECT 77850.0 142050.0 53250.0 142950.0 ; + RECT 62250.0 106350.0 48300.0 107250.0 ; + RECT 59250.0 103650.0 45300.0 104550.0 ; + RECT 56250.0 118350.0 48300.0 119250.0 ; + RECT 59250.0 121050.0 45300.0 121950.0 ; + RECT 62250.0 133950.0 48300.0 134850.0 ; + RECT 53250.0 131250.0 45300.0 132150.0 ; + RECT 56250.0 145950.0 48300.0 146850.0 ; + RECT 53250.0 148650.0 45300.0 149550.0 ; + RECT 38850.0 106350.0 37950.0 107250.0 ; + RECT 38850.0 105150.0 37950.0 106050.0 ; + RECT 42900.0 106350.0 38400.0 107250.0 ; + RECT 38850.0 105600.0 37950.0 106800.0 ; + RECT 38400.0 105150.0 33900.0 106050.0 ; + RECT 38850.0 118350.0 37950.0 119250.0 ; + RECT 38850.0 119550.0 37950.0 120450.0 ; + RECT 42900.0 118350.0 38400.0 119250.0 ; + RECT 38850.0 118800.0 37950.0 120000.0 ; + RECT 38400.0 119550.0 33900.0 120450.0 ; + RECT 38850.0 133950.0 37950.0 134850.0 ; + RECT 38850.0 132750.0 37950.0 133650.0 ; + RECT 42900.0 133950.0 38400.0 134850.0 ; + RECT 38850.0 133200.0 37950.0 134400.0 ; + RECT 38400.0 132750.0 33900.0 133650.0 ; + RECT 38850.0 145950.0 37950.0 146850.0 ; + RECT 38850.0 147150.0 37950.0 148050.0 ; + RECT 42900.0 145950.0 38400.0 146850.0 ; + RECT 38850.0 146400.0 37950.0 147600.0 ; + RECT 38400.0 147150.0 33900.0 148050.0 ; + RECT 68700.0 110850.0 67500.0 112800.0 ; + RECT 68700.0 99000.0 67500.0 100950.0 ; + RECT 73500.0 100350.0 72300.0 98550.0 ; + RECT 73500.0 109650.0 72300.0 113250.0 ; + RECT 70800.0 100350.0 69900.0 109650.0 ; + RECT 73500.0 109650.0 72300.0 110850.0 ; + RECT 71100.0 109650.0 69900.0 110850.0 ; + RECT 71100.0 109650.0 69900.0 110850.0 ; + RECT 73500.0 109650.0 72300.0 110850.0 ; + RECT 73500.0 100350.0 72300.0 101550.0 ; + RECT 71100.0 100350.0 69900.0 101550.0 ; + RECT 71100.0 100350.0 69900.0 101550.0 ; + RECT 73500.0 100350.0 72300.0 101550.0 ; + RECT 68700.0 110250.0 67500.0 111450.0 ; + RECT 68700.0 100350.0 67500.0 101550.0 ; + RECT 72900.0 105000.0 71700.0 106200.0 ; + RECT 72900.0 105000.0 71700.0 106200.0 ; + RECT 70350.0 105150.0 69450.0 106050.0 ; + RECT 75300.0 112350.0 65700.0 113250.0 ; + RECT 75300.0 98550.0 65700.0 99450.0 ; + RECT 68700.0 114750.0 67500.0 112800.0 ; + RECT 68700.0 126600.0 67500.0 124650.0 ; + RECT 73500.0 125250.0 72300.0 127050.0 ; + RECT 73500.0 115950.0 72300.0 112350.0 ; + RECT 70800.0 125250.0 69900.0 115950.0 ; + RECT 73500.0 115950.0 72300.0 114750.0 ; + RECT 71100.0 115950.0 69900.0 114750.0 ; + RECT 71100.0 115950.0 69900.0 114750.0 ; + RECT 73500.0 115950.0 72300.0 114750.0 ; + RECT 73500.0 125250.0 72300.0 124050.0 ; + RECT 71100.0 125250.0 69900.0 124050.0 ; + RECT 71100.0 125250.0 69900.0 124050.0 ; + RECT 73500.0 125250.0 72300.0 124050.0 ; + RECT 68700.0 115350.0 67500.0 114150.0 ; + RECT 68700.0 125250.0 67500.0 124050.0 ; + RECT 72900.0 120600.0 71700.0 119400.0 ; + RECT 72900.0 120600.0 71700.0 119400.0 ; + RECT 70350.0 120450.0 69450.0 119550.0 ; + RECT 75300.0 113250.0 65700.0 112350.0 ; + RECT 75300.0 127050.0 65700.0 126150.0 ; + RECT 29700.0 110850.0 28500.0 112800.0 ; + RECT 29700.0 99000.0 28500.0 100950.0 ; + RECT 34500.0 100350.0 33300.0 98550.0 ; + RECT 34500.0 109650.0 33300.0 113250.0 ; + RECT 31800.0 100350.0 30900.0 109650.0 ; + RECT 34500.0 109650.0 33300.0 110850.0 ; + RECT 32100.0 109650.0 30900.0 110850.0 ; + RECT 32100.0 109650.0 30900.0 110850.0 ; + RECT 34500.0 109650.0 33300.0 110850.0 ; + RECT 34500.0 100350.0 33300.0 101550.0 ; + RECT 32100.0 100350.0 30900.0 101550.0 ; + RECT 32100.0 100350.0 30900.0 101550.0 ; + RECT 34500.0 100350.0 33300.0 101550.0 ; + RECT 29700.0 110250.0 28500.0 111450.0 ; + RECT 29700.0 100350.0 28500.0 101550.0 ; + RECT 33900.0 105000.0 32700.0 106200.0 ; + RECT 33900.0 105000.0 32700.0 106200.0 ; + RECT 31350.0 105150.0 30450.0 106050.0 ; + RECT 36300.0 112350.0 26700.0 113250.0 ; + RECT 36300.0 98550.0 26700.0 99450.0 ; + RECT 29700.0 114750.0 28500.0 112800.0 ; + RECT 29700.0 126600.0 28500.0 124650.0 ; + RECT 34500.0 125250.0 33300.0 127050.0 ; + RECT 34500.0 115950.0 33300.0 112350.0 ; + RECT 31800.0 125250.0 30900.0 115950.0 ; + RECT 34500.0 115950.0 33300.0 114750.0 ; + RECT 32100.0 115950.0 30900.0 114750.0 ; + RECT 32100.0 115950.0 30900.0 114750.0 ; + RECT 34500.0 115950.0 33300.0 114750.0 ; + RECT 34500.0 125250.0 33300.0 124050.0 ; + RECT 32100.0 125250.0 30900.0 124050.0 ; + RECT 32100.0 125250.0 30900.0 124050.0 ; + RECT 34500.0 125250.0 33300.0 124050.0 ; + RECT 29700.0 115350.0 28500.0 114150.0 ; + RECT 29700.0 125250.0 28500.0 124050.0 ; + RECT 33900.0 120600.0 32700.0 119400.0 ; + RECT 33900.0 120600.0 32700.0 119400.0 ; + RECT 31350.0 120450.0 30450.0 119550.0 ; + RECT 36300.0 113250.0 26700.0 112350.0 ; + RECT 36300.0 127050.0 26700.0 126150.0 ; + RECT 29700.0 138450.0 28500.0 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81300.0 167550.0 26700.0 168450.0 ; + RECT 81300.0 195150.0 26700.0 196050.0 ; + RECT 81300.0 153750.0 26700.0 154650.0 ; + RECT 81300.0 181350.0 26700.0 182250.0 ; + RECT 81300.0 208950.0 26700.0 209850.0 ; + RECT 28500.0 211350.0 29700.0 208950.0 ; + RECT 28500.0 220050.0 29700.0 223650.0 ; + RECT 33300.0 220050.0 34500.0 223650.0 ; + RECT 35700.0 221250.0 36900.0 223200.0 ; + RECT 35700.0 209400.0 36900.0 211350.0 ; + RECT 28500.0 220050.0 29700.0 221250.0 ; + RECT 30900.0 220050.0 32100.0 221250.0 ; + RECT 30900.0 220050.0 32100.0 221250.0 ; + RECT 28500.0 220050.0 29700.0 221250.0 ; + RECT 30900.0 220050.0 32100.0 221250.0 ; + RECT 33300.0 220050.0 34500.0 221250.0 ; + RECT 33300.0 220050.0 34500.0 221250.0 ; + RECT 30900.0 220050.0 32100.0 221250.0 ; + RECT 28500.0 211350.0 29700.0 212550.0 ; + RECT 30900.0 211350.0 32100.0 212550.0 ; + RECT 30900.0 211350.0 32100.0 212550.0 ; + RECT 28500.0 211350.0 29700.0 212550.0 ; + RECT 30900.0 211350.0 32100.0 212550.0 ; + RECT 33300.0 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289050.0 ; + RECT 28500.0 290250.0 29700.0 289050.0 ; + RECT 30900.0 290250.0 32100.0 289050.0 ; + RECT 33300.0 290250.0 34500.0 289050.0 ; + RECT 33300.0 290250.0 34500.0 289050.0 ; + RECT 30900.0 290250.0 32100.0 289050.0 ; + RECT 35700.0 280950.0 36900.0 279750.0 ; + RECT 35700.0 290850.0 36900.0 289650.0 ; + RECT 33300.0 287700.0 32100.0 286500.0 ; + RECT 30300.0 285000.0 29100.0 283800.0 ; + RECT 30900.0 281550.0 32100.0 280350.0 ; + RECT 33300.0 290250.0 34500.0 289050.0 ; + RECT 34500.0 285000.0 33300.0 283800.0 ; + RECT 29100.0 285000.0 30300.0 283800.0 ; + RECT 32100.0 287700.0 33300.0 286500.0 ; + RECT 33300.0 285000.0 34500.0 283800.0 ; + RECT 26700.0 278850.0 41100.0 277950.0 ; + RECT 26700.0 292650.0 41100.0 291750.0 ; + RECT 28500.0 294150.0 29700.0 291750.0 ; + RECT 28500.0 302850.0 29700.0 306450.0 ; + RECT 33300.0 302850.0 34500.0 306450.0 ; + RECT 35700.0 304050.0 36900.0 306000.0 ; + RECT 35700.0 292200.0 36900.0 294150.0 ; + RECT 28500.0 302850.0 29700.0 304050.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 28500.0 302850.0 29700.0 304050.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 33300.0 302850.0 34500.0 304050.0 ; + RECT 33300.0 302850.0 34500.0 304050.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 28500.0 294150.0 29700.0 295350.0 ; + RECT 30900.0 294150.0 32100.0 295350.0 ; + RECT 30900.0 294150.0 32100.0 295350.0 ; + RECT 28500.0 294150.0 29700.0 295350.0 ; + RECT 30900.0 294150.0 32100.0 295350.0 ; + RECT 33300.0 294150.0 34500.0 295350.0 ; + RECT 33300.0 294150.0 34500.0 295350.0 ; + RECT 30900.0 294150.0 32100.0 295350.0 ; + RECT 35700.0 303450.0 36900.0 304650.0 ; + RECT 35700.0 293550.0 36900.0 294750.0 ; + RECT 33300.0 296700.0 32100.0 297900.0 ; + RECT 30300.0 299400.0 29100.0 300600.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 33300.0 294150.0 34500.0 295350.0 ; + RECT 34500.0 299400.0 33300.0 300600.0 ; + RECT 29100.0 299400.0 30300.0 300600.0 ; + RECT 32100.0 296700.0 33300.0 297900.0 ; + RECT 33300.0 299400.0 34500.0 300600.0 ; + RECT 26700.0 305550.0 41100.0 306450.0 ; + RECT 26700.0 291750.0 41100.0 292650.0 ; + RECT 28500.0 317850.0 29700.0 320250.0 ; + RECT 28500.0 309150.0 29700.0 305550.0 ; + RECT 33300.0 309150.0 34500.0 305550.0 ; + RECT 35700.0 307950.0 36900.0 306000.0 ; + RECT 35700.0 319800.0 36900.0 317850.0 ; + RECT 28500.0 309150.0 29700.0 307950.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 28500.0 309150.0 29700.0 307950.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 33300.0 309150.0 34500.0 307950.0 ; + RECT 33300.0 309150.0 34500.0 307950.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 28500.0 317850.0 29700.0 316650.0 ; + RECT 30900.0 317850.0 32100.0 316650.0 ; + RECT 30900.0 317850.0 32100.0 316650.0 ; + RECT 28500.0 317850.0 29700.0 316650.0 ; + RECT 30900.0 317850.0 32100.0 316650.0 ; + RECT 33300.0 317850.0 34500.0 316650.0 ; + RECT 33300.0 317850.0 34500.0 316650.0 ; + RECT 30900.0 317850.0 32100.0 316650.0 ; + RECT 35700.0 308550.0 36900.0 307350.0 ; + RECT 35700.0 318450.0 36900.0 317250.0 ; + RECT 33300.0 315300.0 32100.0 314100.0 ; + RECT 30300.0 312600.0 29100.0 311400.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 33300.0 317850.0 34500.0 316650.0 ; + RECT 34500.0 312600.0 33300.0 311400.0 ; + RECT 29100.0 312600.0 30300.0 311400.0 ; + RECT 32100.0 315300.0 33300.0 314100.0 ; + RECT 33300.0 312600.0 34500.0 311400.0 ; + RECT 26700.0 306450.0 41100.0 305550.0 ; + RECT 26700.0 320250.0 41100.0 319350.0 ; + RECT 28500.0 321750.0 29700.0 319350.0 ; + RECT 28500.0 330450.0 29700.0 334050.0 ; + RECT 33300.0 330450.0 34500.0 334050.0 ; + RECT 35700.0 331650.0 36900.0 333600.0 ; + RECT 35700.0 319800.0 36900.0 321750.0 ; + RECT 28500.0 330450.0 29700.0 331650.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 28500.0 330450.0 29700.0 331650.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 33300.0 330450.0 34500.0 331650.0 ; + RECT 33300.0 330450.0 34500.0 331650.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 28500.0 321750.0 29700.0 322950.0 ; + RECT 30900.0 321750.0 32100.0 322950.0 ; + RECT 30900.0 321750.0 32100.0 322950.0 ; + RECT 28500.0 321750.0 29700.0 322950.0 ; + RECT 30900.0 321750.0 32100.0 322950.0 ; + RECT 33300.0 321750.0 34500.0 322950.0 ; + RECT 33300.0 321750.0 34500.0 322950.0 ; + RECT 30900.0 321750.0 32100.0 322950.0 ; + RECT 35700.0 331050.0 36900.0 332250.0 ; + RECT 35700.0 321150.0 36900.0 322350.0 ; + RECT 33300.0 324300.0 32100.0 325500.0 ; + RECT 30300.0 327000.0 29100.0 328200.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 33300.0 321750.0 34500.0 322950.0 ; + RECT 34500.0 327000.0 33300.0 328200.0 ; + RECT 29100.0 327000.0 30300.0 328200.0 ; + RECT 32100.0 324300.0 33300.0 325500.0 ; + RECT 33300.0 327000.0 34500.0 328200.0 ; + RECT 26700.0 333150.0 41100.0 334050.0 ; + RECT 26700.0 319350.0 41100.0 320250.0 ; + RECT 28500.0 345450.0 29700.0 347850.0 ; + RECT 28500.0 336750.0 29700.0 333150.0 ; + RECT 33300.0 336750.0 34500.0 333150.0 ; + RECT 35700.0 335550.0 36900.0 333600.0 ; + RECT 35700.0 347400.0 36900.0 345450.0 ; + RECT 28500.0 336750.0 29700.0 335550.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 28500.0 336750.0 29700.0 335550.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 33300.0 336750.0 34500.0 335550.0 ; + RECT 33300.0 336750.0 34500.0 335550.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 28500.0 345450.0 29700.0 344250.0 ; + RECT 30900.0 345450.0 32100.0 344250.0 ; + RECT 30900.0 345450.0 32100.0 344250.0 ; + RECT 28500.0 345450.0 29700.0 344250.0 ; + RECT 30900.0 345450.0 32100.0 344250.0 ; + RECT 33300.0 345450.0 34500.0 344250.0 ; + RECT 33300.0 345450.0 34500.0 344250.0 ; + RECT 30900.0 345450.0 32100.0 344250.0 ; + RECT 35700.0 336150.0 36900.0 334950.0 ; + RECT 35700.0 346050.0 36900.0 344850.0 ; + RECT 33300.0 342900.0 32100.0 341700.0 ; + RECT 30300.0 340200.0 29100.0 339000.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 33300.0 345450.0 34500.0 344250.0 ; + RECT 34500.0 340200.0 33300.0 339000.0 ; + RECT 29100.0 340200.0 30300.0 339000.0 ; + RECT 32100.0 342900.0 33300.0 341700.0 ; + RECT 33300.0 340200.0 34500.0 339000.0 ; + RECT 26700.0 334050.0 41100.0 333150.0 ; + RECT 26700.0 347850.0 41100.0 346950.0 ; + RECT 28500.0 349350.0 29700.0 346950.0 ; + RECT 28500.0 358050.0 29700.0 361650.0 ; + RECT 33300.0 358050.0 34500.0 361650.0 ; + RECT 35700.0 359250.0 36900.0 361200.0 ; + RECT 35700.0 347400.0 36900.0 349350.0 ; + RECT 28500.0 358050.0 29700.0 359250.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 28500.0 358050.0 29700.0 359250.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 33300.0 358050.0 34500.0 359250.0 ; + RECT 33300.0 358050.0 34500.0 359250.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 28500.0 349350.0 29700.0 350550.0 ; + RECT 30900.0 349350.0 32100.0 350550.0 ; + RECT 30900.0 349350.0 32100.0 350550.0 ; + RECT 28500.0 349350.0 29700.0 350550.0 ; + RECT 30900.0 349350.0 32100.0 350550.0 ; + RECT 33300.0 349350.0 34500.0 350550.0 ; + RECT 33300.0 349350.0 34500.0 350550.0 ; + RECT 30900.0 349350.0 32100.0 350550.0 ; + RECT 35700.0 358650.0 36900.0 359850.0 ; + RECT 35700.0 348750.0 36900.0 349950.0 ; + RECT 33300.0 351900.0 32100.0 353100.0 ; + RECT 30300.0 354600.0 29100.0 355800.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 33300.0 349350.0 34500.0 350550.0 ; + RECT 34500.0 354600.0 33300.0 355800.0 ; + RECT 29100.0 354600.0 30300.0 355800.0 ; + RECT 32100.0 351900.0 33300.0 353100.0 ; + RECT 33300.0 354600.0 34500.0 355800.0 ; + RECT 26700.0 360750.0 41100.0 361650.0 ; + RECT 26700.0 346950.0 41100.0 347850.0 ; + RECT 28500.0 373050.0 29700.0 375450.0 ; + RECT 28500.0 364350.0 29700.0 360750.0 ; + RECT 33300.0 364350.0 34500.0 360750.0 ; + RECT 35700.0 363150.0 36900.0 361200.0 ; + RECT 35700.0 375000.0 36900.0 373050.0 ; + RECT 28500.0 364350.0 29700.0 363150.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 28500.0 364350.0 29700.0 363150.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 33300.0 364350.0 34500.0 363150.0 ; + RECT 33300.0 364350.0 34500.0 363150.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 28500.0 373050.0 29700.0 371850.0 ; + RECT 30900.0 373050.0 32100.0 371850.0 ; + RECT 30900.0 373050.0 32100.0 371850.0 ; + RECT 28500.0 373050.0 29700.0 371850.0 ; + RECT 30900.0 373050.0 32100.0 371850.0 ; + RECT 33300.0 373050.0 34500.0 371850.0 ; + RECT 33300.0 373050.0 34500.0 371850.0 ; + RECT 30900.0 373050.0 32100.0 371850.0 ; + RECT 35700.0 363750.0 36900.0 362550.0 ; + RECT 35700.0 373650.0 36900.0 372450.0 ; + RECT 33300.0 370500.0 32100.0 369300.0 ; + RECT 30300.0 367800.0 29100.0 366600.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 33300.0 373050.0 34500.0 371850.0 ; + RECT 34500.0 367800.0 33300.0 366600.0 ; + RECT 29100.0 367800.0 30300.0 366600.0 ; + RECT 32100.0 370500.0 33300.0 369300.0 ; + RECT 33300.0 367800.0 34500.0 366600.0 ; + RECT 26700.0 361650.0 41100.0 360750.0 ; + RECT 26700.0 375450.0 41100.0 374550.0 ; + RECT 28500.0 376950.0 29700.0 374550.0 ; + RECT 28500.0 385650.0 29700.0 389250.0 ; + RECT 33300.0 385650.0 34500.0 389250.0 ; + RECT 35700.0 386850.0 36900.0 388800.0 ; + RECT 35700.0 375000.0 36900.0 376950.0 ; + RECT 28500.0 385650.0 29700.0 386850.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 28500.0 385650.0 29700.0 386850.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 33300.0 385650.0 34500.0 386850.0 ; + RECT 33300.0 385650.0 34500.0 386850.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 28500.0 376950.0 29700.0 378150.0 ; + RECT 30900.0 376950.0 32100.0 378150.0 ; + RECT 30900.0 376950.0 32100.0 378150.0 ; + RECT 28500.0 376950.0 29700.0 378150.0 ; + RECT 30900.0 376950.0 32100.0 378150.0 ; + RECT 33300.0 376950.0 34500.0 378150.0 ; + RECT 33300.0 376950.0 34500.0 378150.0 ; + RECT 30900.0 376950.0 32100.0 378150.0 ; + RECT 35700.0 386250.0 36900.0 387450.0 ; + RECT 35700.0 376350.0 36900.0 377550.0 ; + RECT 33300.0 379500.0 32100.0 380700.0 ; + RECT 30300.0 382200.0 29100.0 383400.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 33300.0 376950.0 34500.0 378150.0 ; + RECT 34500.0 382200.0 33300.0 383400.0 ; + RECT 29100.0 382200.0 30300.0 383400.0 ; + RECT 32100.0 379500.0 33300.0 380700.0 ; + RECT 33300.0 382200.0 34500.0 383400.0 ; + RECT 26700.0 388350.0 41100.0 389250.0 ; + RECT 26700.0 374550.0 41100.0 375450.0 ; + RECT 28500.0 400650.0 29700.0 403050.0 ; + RECT 28500.0 391950.0 29700.0 388350.0 ; + RECT 33300.0 391950.0 34500.0 388350.0 ; + RECT 35700.0 390750.0 36900.0 388800.0 ; + RECT 35700.0 402600.0 36900.0 400650.0 ; + RECT 28500.0 391950.0 29700.0 390750.0 ; + RECT 30900.0 391950.0 32100.0 390750.0 ; + RECT 30900.0 391950.0 32100.0 390750.0 ; + RECT 28500.0 391950.0 29700.0 390750.0 ; + RECT 30900.0 391950.0 32100.0 390750.0 ; + RECT 33300.0 391950.0 34500.0 390750.0 ; + RECT 33300.0 391950.0 34500.0 390750.0 ; + RECT 30900.0 391950.0 32100.0 390750.0 ; + RECT 28500.0 400650.0 29700.0 399450.0 ; + RECT 30900.0 400650.0 32100.0 399450.0 ; + RECT 30900.0 400650.0 32100.0 399450.0 ; + RECT 28500.0 400650.0 29700.0 399450.0 ; + RECT 30900.0 400650.0 32100.0 399450.0 ; + RECT 33300.0 400650.0 34500.0 399450.0 ; + RECT 33300.0 400650.0 34500.0 399450.0 ; + RECT 30900.0 400650.0 32100.0 399450.0 ; + RECT 35700.0 391350.0 36900.0 390150.0 ; + RECT 35700.0 401250.0 36900.0 400050.0 ; + RECT 33300.0 398100.0 32100.0 396900.0 ; + RECT 30300.0 395400.0 29100.0 394200.0 ; + RECT 30900.0 391950.0 32100.0 390750.0 ; + RECT 33300.0 400650.0 34500.0 399450.0 ; + RECT 34500.0 395400.0 33300.0 394200.0 ; + RECT 29100.0 395400.0 30300.0 394200.0 ; + RECT 32100.0 398100.0 33300.0 396900.0 ; + RECT 33300.0 395400.0 34500.0 394200.0 ; + RECT 26700.0 389250.0 41100.0 388350.0 ; + RECT 26700.0 403050.0 41100.0 402150.0 ; + RECT 28500.0 404550.0 29700.0 402150.0 ; + RECT 28500.0 413250.0 29700.0 416850.0 ; + RECT 33300.0 413250.0 34500.0 416850.0 ; + RECT 35700.0 414450.0 36900.0 416400.0 ; + RECT 35700.0 402600.0 36900.0 404550.0 ; + RECT 28500.0 413250.0 29700.0 414450.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 28500.0 413250.0 29700.0 414450.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 33300.0 413250.0 34500.0 414450.0 ; + RECT 33300.0 413250.0 34500.0 414450.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 28500.0 404550.0 29700.0 405750.0 ; + RECT 30900.0 404550.0 32100.0 405750.0 ; + RECT 30900.0 404550.0 32100.0 405750.0 ; + RECT 28500.0 404550.0 29700.0 405750.0 ; + RECT 30900.0 404550.0 32100.0 405750.0 ; + RECT 33300.0 404550.0 34500.0 405750.0 ; + RECT 33300.0 404550.0 34500.0 405750.0 ; + RECT 30900.0 404550.0 32100.0 405750.0 ; + RECT 35700.0 413850.0 36900.0 415050.0 ; + RECT 35700.0 403950.0 36900.0 405150.0 ; + RECT 33300.0 407100.0 32100.0 408300.0 ; + RECT 30300.0 409800.0 29100.0 411000.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 33300.0 404550.0 34500.0 405750.0 ; + RECT 34500.0 409800.0 33300.0 411000.0 ; + RECT 29100.0 409800.0 30300.0 411000.0 ; + RECT 32100.0 407100.0 33300.0 408300.0 ; + RECT 33300.0 409800.0 34500.0 411000.0 ; + RECT 26700.0 415950.0 41100.0 416850.0 ; + RECT 26700.0 402150.0 41100.0 403050.0 ; + RECT 28500.0 428250.0 29700.0 430650.0 ; + RECT 28500.0 419550.0 29700.0 415950.0 ; + RECT 33300.0 419550.0 34500.0 415950.0 ; + RECT 35700.0 418350.0 36900.0 416400.0 ; + RECT 35700.0 430200.0 36900.0 428250.0 ; + RECT 28500.0 419550.0 29700.0 418350.0 ; + RECT 30900.0 419550.0 32100.0 418350.0 ; + RECT 30900.0 419550.0 32100.0 418350.0 ; + RECT 28500.0 419550.0 29700.0 418350.0 ; + RECT 30900.0 419550.0 32100.0 418350.0 ; + RECT 33300.0 419550.0 34500.0 418350.0 ; + RECT 33300.0 419550.0 34500.0 418350.0 ; + RECT 30900.0 419550.0 32100.0 418350.0 ; + RECT 28500.0 428250.0 29700.0 427050.0 ; + RECT 30900.0 428250.0 32100.0 427050.0 ; + RECT 30900.0 428250.0 32100.0 427050.0 ; + RECT 28500.0 428250.0 29700.0 427050.0 ; + RECT 30900.0 428250.0 32100.0 427050.0 ; + RECT 33300.0 428250.0 34500.0 427050.0 ; + RECT 33300.0 428250.0 34500.0 427050.0 ; + RECT 30900.0 428250.0 32100.0 427050.0 ; + RECT 35700.0 418950.0 36900.0 417750.0 ; + RECT 35700.0 428850.0 36900.0 427650.0 ; + RECT 33300.0 425700.0 32100.0 424500.0 ; + RECT 30300.0 423000.0 29100.0 421800.0 ; + RECT 30900.0 419550.0 32100.0 418350.0 ; + RECT 33300.0 428250.0 34500.0 427050.0 ; + RECT 34500.0 423000.0 33300.0 421800.0 ; + RECT 29100.0 423000.0 30300.0 421800.0 ; + RECT 32100.0 425700.0 33300.0 424500.0 ; + RECT 33300.0 423000.0 34500.0 421800.0 ; + RECT 26700.0 416850.0 41100.0 415950.0 ; + RECT 26700.0 430650.0 41100.0 429750.0 ; + RECT 47700.0 221250.0 48900.0 223200.0 ; + RECT 47700.0 209400.0 48900.0 211350.0 ; + RECT 42900.0 210750.0 44100.0 208950.0 ; + RECT 42900.0 220050.0 44100.0 223650.0 ; + RECT 45600.0 210750.0 46500.0 220050.0 ; + RECT 42900.0 220050.0 44100.0 221250.0 ; + RECT 45300.0 220050.0 46500.0 221250.0 ; + RECT 45300.0 220050.0 46500.0 221250.0 ; + RECT 42900.0 220050.0 44100.0 221250.0 ; + RECT 42900.0 210750.0 44100.0 211950.0 ; + RECT 45300.0 210750.0 46500.0 211950.0 ; + RECT 45300.0 210750.0 46500.0 211950.0 ; + RECT 42900.0 210750.0 44100.0 211950.0 ; + RECT 47700.0 220650.0 48900.0 221850.0 ; + RECT 47700.0 210750.0 48900.0 211950.0 ; + RECT 43500.0 215400.0 44700.0 216600.0 ; + RECT 43500.0 215400.0 44700.0 216600.0 ; + RECT 46050.0 215550.0 46950.0 216450.0 ; + RECT 41100.0 222750.0 50700.0 223650.0 ; + RECT 41100.0 208950.0 50700.0 209850.0 ; + RECT 47700.0 225150.0 48900.0 223200.0 ; + RECT 47700.0 237000.0 48900.0 235050.0 ; + RECT 42900.0 235650.0 44100.0 237450.0 ; + RECT 42900.0 226350.0 44100.0 222750.0 ; + RECT 45600.0 235650.0 46500.0 226350.0 ; + RECT 42900.0 226350.0 44100.0 225150.0 ; + RECT 45300.0 226350.0 46500.0 225150.0 ; + RECT 45300.0 226350.0 46500.0 225150.0 ; + RECT 42900.0 226350.0 44100.0 225150.0 ; + RECT 42900.0 235650.0 44100.0 234450.0 ; + RECT 45300.0 235650.0 46500.0 234450.0 ; + RECT 45300.0 235650.0 46500.0 234450.0 ; + RECT 42900.0 235650.0 44100.0 234450.0 ; + RECT 47700.0 225750.0 48900.0 224550.0 ; + RECT 47700.0 235650.0 48900.0 234450.0 ; + RECT 43500.0 231000.0 44700.0 229800.0 ; + RECT 43500.0 231000.0 44700.0 229800.0 ; + RECT 46050.0 230850.0 46950.0 229950.0 ; + RECT 41100.0 223650.0 50700.0 222750.0 ; + RECT 41100.0 237450.0 50700.0 236550.0 ; + RECT 47700.0 248850.0 48900.0 250800.0 ; + RECT 47700.0 237000.0 48900.0 238950.0 ; + RECT 42900.0 238350.0 44100.0 236550.0 ; + RECT 42900.0 247650.0 44100.0 251250.0 ; + RECT 45600.0 238350.0 46500.0 247650.0 ; + RECT 42900.0 247650.0 44100.0 248850.0 ; + RECT 45300.0 247650.0 46500.0 248850.0 ; + RECT 45300.0 247650.0 46500.0 248850.0 ; + RECT 42900.0 247650.0 44100.0 248850.0 ; + RECT 42900.0 238350.0 44100.0 239550.0 ; + RECT 45300.0 238350.0 46500.0 239550.0 ; + RECT 45300.0 238350.0 46500.0 239550.0 ; + RECT 42900.0 238350.0 44100.0 239550.0 ; + RECT 47700.0 248250.0 48900.0 249450.0 ; + RECT 47700.0 238350.0 48900.0 239550.0 ; + RECT 43500.0 243000.0 44700.0 244200.0 ; + RECT 43500.0 243000.0 44700.0 244200.0 ; + RECT 46050.0 243150.0 46950.0 244050.0 ; + RECT 41100.0 250350.0 50700.0 251250.0 ; + RECT 41100.0 236550.0 50700.0 237450.0 ; + RECT 47700.0 252750.0 48900.0 250800.0 ; + RECT 47700.0 264600.0 48900.0 262650.0 ; + RECT 42900.0 263250.0 44100.0 265050.0 ; + RECT 42900.0 253950.0 44100.0 250350.0 ; + RECT 45600.0 263250.0 46500.0 253950.0 ; + RECT 42900.0 253950.0 44100.0 252750.0 ; + RECT 45300.0 253950.0 46500.0 252750.0 ; + RECT 45300.0 253950.0 46500.0 252750.0 ; + RECT 42900.0 253950.0 44100.0 252750.0 ; + RECT 42900.0 263250.0 44100.0 262050.0 ; + RECT 45300.0 263250.0 46500.0 262050.0 ; + RECT 45300.0 263250.0 46500.0 262050.0 ; + RECT 42900.0 263250.0 44100.0 262050.0 ; + RECT 47700.0 253350.0 48900.0 252150.0 ; + RECT 47700.0 263250.0 48900.0 262050.0 ; + RECT 43500.0 258600.0 44700.0 257400.0 ; + RECT 43500.0 258600.0 44700.0 257400.0 ; + RECT 46050.0 258450.0 46950.0 257550.0 ; + RECT 41100.0 251250.0 50700.0 250350.0 ; + RECT 41100.0 265050.0 50700.0 264150.0 ; + RECT 47700.0 276450.0 48900.0 278400.0 ; + RECT 47700.0 264600.0 48900.0 266550.0 ; + RECT 42900.0 265950.0 44100.0 264150.0 ; + RECT 42900.0 275250.0 44100.0 278850.0 ; + RECT 45600.0 265950.0 46500.0 275250.0 ; + RECT 42900.0 275250.0 44100.0 276450.0 ; + RECT 45300.0 275250.0 46500.0 276450.0 ; + RECT 45300.0 275250.0 46500.0 276450.0 ; + RECT 42900.0 275250.0 44100.0 276450.0 ; + RECT 42900.0 265950.0 44100.0 267150.0 ; + RECT 45300.0 265950.0 46500.0 267150.0 ; + RECT 45300.0 265950.0 46500.0 267150.0 ; + RECT 42900.0 265950.0 44100.0 267150.0 ; + RECT 47700.0 275850.0 48900.0 277050.0 ; + RECT 47700.0 265950.0 48900.0 267150.0 ; + RECT 43500.0 270600.0 44700.0 271800.0 ; + RECT 43500.0 270600.0 44700.0 271800.0 ; + RECT 46050.0 270750.0 46950.0 271650.0 ; + RECT 41100.0 277950.0 50700.0 278850.0 ; + RECT 41100.0 264150.0 50700.0 265050.0 ; + RECT 47700.0 280350.0 48900.0 278400.0 ; + RECT 47700.0 292200.0 48900.0 290250.0 ; + RECT 42900.0 290850.0 44100.0 292650.0 ; + RECT 42900.0 281550.0 44100.0 277950.0 ; + RECT 45600.0 290850.0 46500.0 281550.0 ; + RECT 42900.0 281550.0 44100.0 280350.0 ; + RECT 45300.0 281550.0 46500.0 280350.0 ; + RECT 45300.0 281550.0 46500.0 280350.0 ; + RECT 42900.0 281550.0 44100.0 280350.0 ; + RECT 42900.0 290850.0 44100.0 289650.0 ; + RECT 45300.0 290850.0 46500.0 289650.0 ; + RECT 45300.0 290850.0 46500.0 289650.0 ; + RECT 42900.0 290850.0 44100.0 289650.0 ; + RECT 47700.0 280950.0 48900.0 279750.0 ; + RECT 47700.0 290850.0 48900.0 289650.0 ; + RECT 43500.0 286200.0 44700.0 285000.0 ; + RECT 43500.0 286200.0 44700.0 285000.0 ; + RECT 46050.0 286050.0 46950.0 285150.0 ; + RECT 41100.0 278850.0 50700.0 277950.0 ; + RECT 41100.0 292650.0 50700.0 291750.0 ; + RECT 47700.0 304050.0 48900.0 306000.0 ; + RECT 47700.0 292200.0 48900.0 294150.0 ; + RECT 42900.0 293550.0 44100.0 291750.0 ; + RECT 42900.0 302850.0 44100.0 306450.0 ; + RECT 45600.0 293550.0 46500.0 302850.0 ; + RECT 42900.0 302850.0 44100.0 304050.0 ; + RECT 45300.0 302850.0 46500.0 304050.0 ; + RECT 45300.0 302850.0 46500.0 304050.0 ; + RECT 42900.0 302850.0 44100.0 304050.0 ; + RECT 42900.0 293550.0 44100.0 294750.0 ; + RECT 45300.0 293550.0 46500.0 294750.0 ; + RECT 45300.0 293550.0 46500.0 294750.0 ; + RECT 42900.0 293550.0 44100.0 294750.0 ; + RECT 47700.0 303450.0 48900.0 304650.0 ; + RECT 47700.0 293550.0 48900.0 294750.0 ; + RECT 43500.0 298200.0 44700.0 299400.0 ; + RECT 43500.0 298200.0 44700.0 299400.0 ; + RECT 46050.0 298350.0 46950.0 299250.0 ; + RECT 41100.0 305550.0 50700.0 306450.0 ; + RECT 41100.0 291750.0 50700.0 292650.0 ; + RECT 47700.0 307950.0 48900.0 306000.0 ; + RECT 47700.0 319800.0 48900.0 317850.0 ; + RECT 42900.0 318450.0 44100.0 320250.0 ; + RECT 42900.0 309150.0 44100.0 305550.0 ; + RECT 45600.0 318450.0 46500.0 309150.0 ; + RECT 42900.0 309150.0 44100.0 307950.0 ; + RECT 45300.0 309150.0 46500.0 307950.0 ; + RECT 45300.0 309150.0 46500.0 307950.0 ; + RECT 42900.0 309150.0 44100.0 307950.0 ; + RECT 42900.0 318450.0 44100.0 317250.0 ; + RECT 45300.0 318450.0 46500.0 317250.0 ; + RECT 45300.0 318450.0 46500.0 317250.0 ; + RECT 42900.0 318450.0 44100.0 317250.0 ; + RECT 47700.0 308550.0 48900.0 307350.0 ; + RECT 47700.0 318450.0 48900.0 317250.0 ; + RECT 43500.0 313800.0 44700.0 312600.0 ; + RECT 43500.0 313800.0 44700.0 312600.0 ; + RECT 46050.0 313650.0 46950.0 312750.0 ; + RECT 41100.0 306450.0 50700.0 305550.0 ; + RECT 41100.0 320250.0 50700.0 319350.0 ; + RECT 47700.0 331650.0 48900.0 333600.0 ; + RECT 47700.0 319800.0 48900.0 321750.0 ; + RECT 42900.0 321150.0 44100.0 319350.0 ; + RECT 42900.0 330450.0 44100.0 334050.0 ; + RECT 45600.0 321150.0 46500.0 330450.0 ; + RECT 42900.0 330450.0 44100.0 331650.0 ; + RECT 45300.0 330450.0 46500.0 331650.0 ; + RECT 45300.0 330450.0 46500.0 331650.0 ; + RECT 42900.0 330450.0 44100.0 331650.0 ; + RECT 42900.0 321150.0 44100.0 322350.0 ; + RECT 45300.0 321150.0 46500.0 322350.0 ; + RECT 45300.0 321150.0 46500.0 322350.0 ; + RECT 42900.0 321150.0 44100.0 322350.0 ; + RECT 47700.0 331050.0 48900.0 332250.0 ; + RECT 47700.0 321150.0 48900.0 322350.0 ; + RECT 43500.0 325800.0 44700.0 327000.0 ; + RECT 43500.0 325800.0 44700.0 327000.0 ; + RECT 46050.0 325950.0 46950.0 326850.0 ; + RECT 41100.0 333150.0 50700.0 334050.0 ; + RECT 41100.0 319350.0 50700.0 320250.0 ; + RECT 47700.0 335550.0 48900.0 333600.0 ; + RECT 47700.0 347400.0 48900.0 345450.0 ; + RECT 42900.0 346050.0 44100.0 347850.0 ; + RECT 42900.0 336750.0 44100.0 333150.0 ; + RECT 45600.0 346050.0 46500.0 336750.0 ; + RECT 42900.0 336750.0 44100.0 335550.0 ; + RECT 45300.0 336750.0 46500.0 335550.0 ; + RECT 45300.0 336750.0 46500.0 335550.0 ; + RECT 42900.0 336750.0 44100.0 335550.0 ; + RECT 42900.0 346050.0 44100.0 344850.0 ; + RECT 45300.0 346050.0 46500.0 344850.0 ; + RECT 45300.0 346050.0 46500.0 344850.0 ; + RECT 42900.0 346050.0 44100.0 344850.0 ; + RECT 47700.0 336150.0 48900.0 334950.0 ; + RECT 47700.0 346050.0 48900.0 344850.0 ; + RECT 43500.0 341400.0 44700.0 340200.0 ; + RECT 43500.0 341400.0 44700.0 340200.0 ; + RECT 46050.0 341250.0 46950.0 340350.0 ; + RECT 41100.0 334050.0 50700.0 333150.0 ; + RECT 41100.0 347850.0 50700.0 346950.0 ; + RECT 47700.0 359250.0 48900.0 361200.0 ; + RECT 47700.0 347400.0 48900.0 349350.0 ; + RECT 42900.0 348750.0 44100.0 346950.0 ; + RECT 42900.0 358050.0 44100.0 361650.0 ; + RECT 45600.0 348750.0 46500.0 358050.0 ; + RECT 42900.0 358050.0 44100.0 359250.0 ; + RECT 45300.0 358050.0 46500.0 359250.0 ; + RECT 45300.0 358050.0 46500.0 359250.0 ; + RECT 42900.0 358050.0 44100.0 359250.0 ; + RECT 42900.0 348750.0 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372450.0 ; + RECT 47700.0 363750.0 48900.0 362550.0 ; + RECT 47700.0 373650.0 48900.0 372450.0 ; + RECT 43500.0 369000.0 44700.0 367800.0 ; + RECT 43500.0 369000.0 44700.0 367800.0 ; + RECT 46050.0 368850.0 46950.0 367950.0 ; + RECT 41100.0 361650.0 50700.0 360750.0 ; + RECT 41100.0 375450.0 50700.0 374550.0 ; + RECT 47700.0 386850.0 48900.0 388800.0 ; + RECT 47700.0 375000.0 48900.0 376950.0 ; + RECT 42900.0 376350.0 44100.0 374550.0 ; + RECT 42900.0 385650.0 44100.0 389250.0 ; + RECT 45600.0 376350.0 46500.0 385650.0 ; + RECT 42900.0 385650.0 44100.0 386850.0 ; + RECT 45300.0 385650.0 46500.0 386850.0 ; + RECT 45300.0 385650.0 46500.0 386850.0 ; + RECT 42900.0 385650.0 44100.0 386850.0 ; + RECT 42900.0 376350.0 44100.0 377550.0 ; + RECT 45300.0 376350.0 46500.0 377550.0 ; + RECT 45300.0 376350.0 46500.0 377550.0 ; + RECT 42900.0 376350.0 44100.0 377550.0 ; + RECT 47700.0 386250.0 48900.0 387450.0 ; + RECT 47700.0 376350.0 48900.0 377550.0 ; + RECT 43500.0 381000.0 44700.0 382200.0 ; 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RECT 78450.0 229950.0 79350.0 230850.0 ; + RECT 74400.0 228750.0 78900.0 229650.0 ; + RECT 78450.0 229200.0 79350.0 230400.0 ; + RECT 78900.0 229950.0 83400.0 230850.0 ; + RECT 53850.0 243150.0 59400.0 244050.0 ; + RECT 61950.0 244350.0 62850.0 245250.0 ; + RECT 61950.0 243150.0 62850.0 244050.0 ; + RECT 61950.0 244050.0 62850.0 244800.0 ; + RECT 62400.0 244350.0 69000.0 245250.0 ; + RECT 69000.0 244350.0 70200.0 245250.0 ; + RECT 78450.0 244350.0 79350.0 245250.0 ; + RECT 78450.0 243150.0 79350.0 244050.0 ; + RECT 74400.0 244350.0 78900.0 245250.0 ; + RECT 78450.0 243600.0 79350.0 244800.0 ; + RECT 78900.0 243150.0 83400.0 244050.0 ; + RECT 53850.0 257550.0 59400.0 258450.0 ; + RECT 61950.0 256350.0 62850.0 257250.0 ; + RECT 61950.0 257550.0 62850.0 258450.0 ; + RECT 61950.0 256800.0 62850.0 258450.0 ; + RECT 62400.0 256350.0 69000.0 257250.0 ; + RECT 69000.0 256350.0 70200.0 257250.0 ; + RECT 78450.0 256350.0 79350.0 257250.0 ; + RECT 78450.0 257550.0 79350.0 258450.0 ; + RECT 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68400.0 226350.0 69600.0 222750.0 ; + RECT 73200.0 226350.0 74400.0 222750.0 ; + RECT 75600.0 225150.0 76800.0 223200.0 ; + RECT 75600.0 237000.0 76800.0 235050.0 ; + RECT 68400.0 226350.0 69600.0 225150.0 ; + RECT 70800.0 226350.0 72000.0 225150.0 ; + RECT 70800.0 226350.0 72000.0 225150.0 ; + RECT 68400.0 226350.0 69600.0 225150.0 ; + RECT 70800.0 226350.0 72000.0 225150.0 ; + RECT 73200.0 226350.0 74400.0 225150.0 ; + RECT 73200.0 226350.0 74400.0 225150.0 ; + RECT 70800.0 226350.0 72000.0 225150.0 ; + RECT 68400.0 235050.0 69600.0 233850.0 ; + RECT 70800.0 235050.0 72000.0 233850.0 ; + RECT 70800.0 235050.0 72000.0 233850.0 ; + RECT 68400.0 235050.0 69600.0 233850.0 ; + RECT 70800.0 235050.0 72000.0 233850.0 ; + RECT 73200.0 235050.0 74400.0 233850.0 ; + RECT 73200.0 235050.0 74400.0 233850.0 ; + RECT 70800.0 235050.0 72000.0 233850.0 ; + RECT 75600.0 225750.0 76800.0 224550.0 ; + RECT 75600.0 235650.0 76800.0 234450.0 ; + RECT 73200.0 232500.0 72000.0 231300.0 ; + RECT 70200.0 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88800.0 234450.0 ; + RECT 83400.0 231000.0 84600.0 229800.0 ; + RECT 83400.0 231000.0 84600.0 229800.0 ; + RECT 85950.0 230850.0 86850.0 229950.0 ; + RECT 81000.0 223650.0 90600.0 222750.0 ; + RECT 81000.0 237450.0 90600.0 236550.0 ; + RECT 53250.0 229800.0 54450.0 231000.0 ; + RECT 55200.0 232200.0 56400.0 233400.0 ; + RECT 72000.0 231300.0 70800.0 232500.0 ; + RECT 63600.0 248850.0 64800.0 250800.0 ; + RECT 63600.0 237000.0 64800.0 238950.0 ; + RECT 58800.0 238350.0 60000.0 236550.0 ; + RECT 58800.0 247650.0 60000.0 251250.0 ; + RECT 61500.0 238350.0 62400.0 247650.0 ; + RECT 58800.0 247650.0 60000.0 248850.0 ; + RECT 61200.0 247650.0 62400.0 248850.0 ; + RECT 61200.0 247650.0 62400.0 248850.0 ; + RECT 58800.0 247650.0 60000.0 248850.0 ; + RECT 58800.0 238350.0 60000.0 239550.0 ; + RECT 61200.0 238350.0 62400.0 239550.0 ; + RECT 61200.0 238350.0 62400.0 239550.0 ; + RECT 58800.0 238350.0 60000.0 239550.0 ; + RECT 63600.0 248250.0 64800.0 249450.0 ; + RECT 63600.0 238350.0 64800.0 239550.0 ; + RECT 59400.0 243000.0 60600.0 244200.0 ; + RECT 59400.0 243000.0 60600.0 244200.0 ; + RECT 61950.0 243150.0 62850.0 244050.0 ; + RECT 57000.0 250350.0 66600.0 251250.0 ; + RECT 57000.0 236550.0 66600.0 237450.0 ; + RECT 68400.0 238950.0 69600.0 236550.0 ; + RECT 68400.0 247650.0 69600.0 251250.0 ; + RECT 73200.0 247650.0 74400.0 251250.0 ; + RECT 75600.0 248850.0 76800.0 250800.0 ; + RECT 75600.0 237000.0 76800.0 238950.0 ; + RECT 68400.0 247650.0 69600.0 248850.0 ; + RECT 70800.0 247650.0 72000.0 248850.0 ; + RECT 70800.0 247650.0 72000.0 248850.0 ; + RECT 68400.0 247650.0 69600.0 248850.0 ; + RECT 70800.0 247650.0 72000.0 248850.0 ; + RECT 73200.0 247650.0 74400.0 248850.0 ; + RECT 73200.0 247650.0 74400.0 248850.0 ; + RECT 70800.0 247650.0 72000.0 248850.0 ; + RECT 68400.0 238950.0 69600.0 240150.0 ; + RECT 70800.0 238950.0 72000.0 240150.0 ; + RECT 70800.0 238950.0 72000.0 240150.0 ; + RECT 68400.0 238950.0 69600.0 240150.0 ; + RECT 70800.0 238950.0 72000.0 240150.0 ; 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82800.0 247650.0 84000.0 248850.0 ; + RECT 82800.0 238350.0 84000.0 239550.0 ; + RECT 85200.0 238350.0 86400.0 239550.0 ; + RECT 85200.0 238350.0 86400.0 239550.0 ; + RECT 82800.0 238350.0 84000.0 239550.0 ; + RECT 87600.0 248250.0 88800.0 249450.0 ; + RECT 87600.0 238350.0 88800.0 239550.0 ; + RECT 83400.0 243000.0 84600.0 244200.0 ; + RECT 83400.0 243000.0 84600.0 244200.0 ; + RECT 85950.0 243150.0 86850.0 244050.0 ; + RECT 81000.0 250350.0 90600.0 251250.0 ; + RECT 81000.0 236550.0 90600.0 237450.0 ; + RECT 53250.0 243000.0 54450.0 244200.0 ; + RECT 55200.0 240600.0 56400.0 241800.0 ; + RECT 72000.0 241500.0 70800.0 242700.0 ; + RECT 63600.0 252750.0 64800.0 250800.0 ; + RECT 63600.0 264600.0 64800.0 262650.0 ; + RECT 58800.0 263250.0 60000.0 265050.0 ; + RECT 58800.0 253950.0 60000.0 250350.0 ; + RECT 61500.0 263250.0 62400.0 253950.0 ; + RECT 58800.0 253950.0 60000.0 252750.0 ; + RECT 61200.0 253950.0 62400.0 252750.0 ; + RECT 61200.0 253950.0 62400.0 252750.0 ; + RECT 58800.0 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68400.0 275250.0 69600.0 276450.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 68400.0 275250.0 69600.0 276450.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 73200.0 275250.0 74400.0 276450.0 ; + RECT 73200.0 275250.0 74400.0 276450.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 68400.0 266550.0 69600.0 267750.0 ; + RECT 70800.0 266550.0 72000.0 267750.0 ; + RECT 70800.0 266550.0 72000.0 267750.0 ; + RECT 68400.0 266550.0 69600.0 267750.0 ; + RECT 70800.0 266550.0 72000.0 267750.0 ; + RECT 73200.0 266550.0 74400.0 267750.0 ; + RECT 73200.0 266550.0 74400.0 267750.0 ; + RECT 70800.0 266550.0 72000.0 267750.0 ; + RECT 75600.0 275850.0 76800.0 277050.0 ; + RECT 75600.0 265950.0 76800.0 267150.0 ; + RECT 73200.0 269100.0 72000.0 270300.0 ; + RECT 70200.0 271800.0 69000.0 273000.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 73200.0 266550.0 74400.0 267750.0 ; + RECT 74400.0 271800.0 73200.0 273000.0 ; + RECT 69000.0 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90600.0 278850.0 ; + RECT 81000.0 264150.0 90600.0 265050.0 ; + RECT 53250.0 270600.0 54450.0 271800.0 ; + RECT 55200.0 268200.0 56400.0 269400.0 ; + RECT 72000.0 269100.0 70800.0 270300.0 ; + RECT 63600.0 280350.0 64800.0 278400.0 ; + RECT 63600.0 292200.0 64800.0 290250.0 ; + RECT 58800.0 290850.0 60000.0 292650.0 ; + RECT 58800.0 281550.0 60000.0 277950.0 ; + RECT 61500.0 290850.0 62400.0 281550.0 ; + RECT 58800.0 281550.0 60000.0 280350.0 ; + RECT 61200.0 281550.0 62400.0 280350.0 ; + RECT 61200.0 281550.0 62400.0 280350.0 ; + RECT 58800.0 281550.0 60000.0 280350.0 ; + RECT 58800.0 290850.0 60000.0 289650.0 ; + RECT 61200.0 290850.0 62400.0 289650.0 ; + RECT 61200.0 290850.0 62400.0 289650.0 ; + RECT 58800.0 290850.0 60000.0 289650.0 ; + RECT 63600.0 280950.0 64800.0 279750.0 ; + RECT 63600.0 290850.0 64800.0 289650.0 ; + RECT 59400.0 286200.0 60600.0 285000.0 ; + RECT 59400.0 286200.0 60600.0 285000.0 ; + RECT 61950.0 286050.0 62850.0 285150.0 ; + RECT 57000.0 278850.0 66600.0 277950.0 ; + RECT 57000.0 292650.0 66600.0 291750.0 ; + RECT 68400.0 290250.0 69600.0 292650.0 ; + RECT 68400.0 281550.0 69600.0 277950.0 ; + RECT 73200.0 281550.0 74400.0 277950.0 ; + RECT 75600.0 280350.0 76800.0 278400.0 ; + RECT 75600.0 292200.0 76800.0 290250.0 ; + RECT 68400.0 281550.0 69600.0 280350.0 ; + RECT 70800.0 281550.0 72000.0 280350.0 ; + RECT 70800.0 281550.0 72000.0 280350.0 ; + RECT 68400.0 281550.0 69600.0 280350.0 ; + RECT 70800.0 281550.0 72000.0 280350.0 ; + RECT 73200.0 281550.0 74400.0 280350.0 ; + RECT 73200.0 281550.0 74400.0 280350.0 ; + RECT 70800.0 281550.0 72000.0 280350.0 ; + RECT 68400.0 290250.0 69600.0 289050.0 ; + RECT 70800.0 290250.0 72000.0 289050.0 ; + RECT 70800.0 290250.0 72000.0 289050.0 ; + RECT 68400.0 290250.0 69600.0 289050.0 ; + RECT 70800.0 290250.0 72000.0 289050.0 ; + RECT 73200.0 290250.0 74400.0 289050.0 ; + RECT 73200.0 290250.0 74400.0 289050.0 ; + RECT 70800.0 290250.0 72000.0 289050.0 ; + RECT 75600.0 280950.0 76800.0 279750.0 ; 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82800.0 290850.0 84000.0 289650.0 ; + RECT 87600.0 280950.0 88800.0 279750.0 ; + RECT 87600.0 290850.0 88800.0 289650.0 ; + RECT 83400.0 286200.0 84600.0 285000.0 ; + RECT 83400.0 286200.0 84600.0 285000.0 ; + RECT 85950.0 286050.0 86850.0 285150.0 ; + RECT 81000.0 278850.0 90600.0 277950.0 ; + RECT 81000.0 292650.0 90600.0 291750.0 ; + RECT 53250.0 285000.0 54450.0 286200.0 ; + RECT 55200.0 287400.0 56400.0 288600.0 ; + RECT 72000.0 286500.0 70800.0 287700.0 ; + RECT 63600.0 304050.0 64800.0 306000.0 ; + RECT 63600.0 292200.0 64800.0 294150.0 ; + RECT 58800.0 293550.0 60000.0 291750.0 ; + RECT 58800.0 302850.0 60000.0 306450.0 ; + RECT 61500.0 293550.0 62400.0 302850.0 ; + RECT 58800.0 302850.0 60000.0 304050.0 ; + RECT 61200.0 302850.0 62400.0 304050.0 ; + RECT 61200.0 302850.0 62400.0 304050.0 ; + RECT 58800.0 302850.0 60000.0 304050.0 ; + RECT 58800.0 293550.0 60000.0 294750.0 ; + RECT 61200.0 293550.0 62400.0 294750.0 ; + RECT 61200.0 293550.0 62400.0 294750.0 ; + RECT 58800.0 293550.0 60000.0 294750.0 ; + RECT 63600.0 303450.0 64800.0 304650.0 ; + RECT 63600.0 293550.0 64800.0 294750.0 ; + RECT 59400.0 298200.0 60600.0 299400.0 ; + RECT 59400.0 298200.0 60600.0 299400.0 ; + RECT 61950.0 298350.0 62850.0 299250.0 ; + RECT 57000.0 305550.0 66600.0 306450.0 ; + RECT 57000.0 291750.0 66600.0 292650.0 ; + RECT 68400.0 294150.0 69600.0 291750.0 ; + RECT 68400.0 302850.0 69600.0 306450.0 ; + RECT 73200.0 302850.0 74400.0 306450.0 ; + RECT 75600.0 304050.0 76800.0 306000.0 ; + RECT 75600.0 292200.0 76800.0 294150.0 ; + RECT 68400.0 302850.0 69600.0 304050.0 ; + RECT 70800.0 302850.0 72000.0 304050.0 ; + RECT 70800.0 302850.0 72000.0 304050.0 ; + RECT 68400.0 302850.0 69600.0 304050.0 ; + RECT 70800.0 302850.0 72000.0 304050.0 ; + RECT 73200.0 302850.0 74400.0 304050.0 ; + RECT 73200.0 302850.0 74400.0 304050.0 ; + RECT 70800.0 302850.0 72000.0 304050.0 ; + RECT 68400.0 294150.0 69600.0 295350.0 ; + RECT 70800.0 294150.0 72000.0 295350.0 ; + RECT 70800.0 294150.0 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70800.0 309150.0 72000.0 307950.0 ; + RECT 73200.0 309150.0 74400.0 307950.0 ; + RECT 73200.0 309150.0 74400.0 307950.0 ; + RECT 70800.0 309150.0 72000.0 307950.0 ; + RECT 68400.0 317850.0 69600.0 316650.0 ; + RECT 70800.0 317850.0 72000.0 316650.0 ; + RECT 70800.0 317850.0 72000.0 316650.0 ; + RECT 68400.0 317850.0 69600.0 316650.0 ; + RECT 70800.0 317850.0 72000.0 316650.0 ; + RECT 73200.0 317850.0 74400.0 316650.0 ; + RECT 73200.0 317850.0 74400.0 316650.0 ; + RECT 70800.0 317850.0 72000.0 316650.0 ; + RECT 75600.0 308550.0 76800.0 307350.0 ; + RECT 75600.0 318450.0 76800.0 317250.0 ; + RECT 73200.0 315300.0 72000.0 314100.0 ; + RECT 70200.0 312600.0 69000.0 311400.0 ; + RECT 70800.0 309150.0 72000.0 307950.0 ; + RECT 73200.0 317850.0 74400.0 316650.0 ; + RECT 74400.0 312600.0 73200.0 311400.0 ; + RECT 69000.0 312600.0 70200.0 311400.0 ; + RECT 72000.0 315300.0 73200.0 314100.0 ; + RECT 73200.0 312600.0 74400.0 311400.0 ; + RECT 66600.0 306450.0 81000.0 305550.0 ; + RECT 66600.0 320250.0 81000.0 319350.0 ; + RECT 87600.0 307950.0 88800.0 306000.0 ; + RECT 87600.0 319800.0 88800.0 317850.0 ; + RECT 82800.0 318450.0 84000.0 320250.0 ; + RECT 82800.0 309150.0 84000.0 305550.0 ; + RECT 85500.0 318450.0 86400.0 309150.0 ; + RECT 82800.0 309150.0 84000.0 307950.0 ; + RECT 85200.0 309150.0 86400.0 307950.0 ; + RECT 85200.0 309150.0 86400.0 307950.0 ; + RECT 82800.0 309150.0 84000.0 307950.0 ; + RECT 82800.0 318450.0 84000.0 317250.0 ; + RECT 85200.0 318450.0 86400.0 317250.0 ; + RECT 85200.0 318450.0 86400.0 317250.0 ; + RECT 82800.0 318450.0 84000.0 317250.0 ; + RECT 87600.0 308550.0 88800.0 307350.0 ; + RECT 87600.0 318450.0 88800.0 317250.0 ; + RECT 83400.0 313800.0 84600.0 312600.0 ; + RECT 83400.0 313800.0 84600.0 312600.0 ; + RECT 85950.0 313650.0 86850.0 312750.0 ; + RECT 81000.0 306450.0 90600.0 305550.0 ; + RECT 81000.0 320250.0 90600.0 319350.0 ; + RECT 53250.0 312600.0 54450.0 313800.0 ; + RECT 55200.0 315000.0 56400.0 316200.0 ; + RECT 72000.0 314100.0 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83400.0 325800.0 84600.0 327000.0 ; + RECT 85950.0 325950.0 86850.0 326850.0 ; + RECT 81000.0 333150.0 90600.0 334050.0 ; + RECT 81000.0 319350.0 90600.0 320250.0 ; + RECT 53250.0 325800.0 54450.0 327000.0 ; + RECT 55200.0 323400.0 56400.0 324600.0 ; + RECT 72000.0 324300.0 70800.0 325500.0 ; + RECT 63600.0 335550.0 64800.0 333600.0 ; + RECT 63600.0 347400.0 64800.0 345450.0 ; + RECT 58800.0 346050.0 60000.0 347850.0 ; + RECT 58800.0 336750.0 60000.0 333150.0 ; + RECT 61500.0 346050.0 62400.0 336750.0 ; + RECT 58800.0 336750.0 60000.0 335550.0 ; + RECT 61200.0 336750.0 62400.0 335550.0 ; + RECT 61200.0 336750.0 62400.0 335550.0 ; + RECT 58800.0 336750.0 60000.0 335550.0 ; + RECT 58800.0 346050.0 60000.0 344850.0 ; + RECT 61200.0 346050.0 62400.0 344850.0 ; + RECT 61200.0 346050.0 62400.0 344850.0 ; + RECT 58800.0 346050.0 60000.0 344850.0 ; + RECT 63600.0 336150.0 64800.0 334950.0 ; + RECT 63600.0 346050.0 64800.0 344850.0 ; + RECT 59400.0 341400.0 60600.0 340200.0 ; + RECT 59400.0 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70800.0 400650.0 72000.0 399450.0 ; + RECT 73200.0 400650.0 74400.0 399450.0 ; + RECT 73200.0 400650.0 74400.0 399450.0 ; + RECT 70800.0 400650.0 72000.0 399450.0 ; + RECT 75600.0 391350.0 76800.0 390150.0 ; + RECT 75600.0 401250.0 76800.0 400050.0 ; + RECT 73200.0 398100.0 72000.0 396900.0 ; + RECT 70200.0 395400.0 69000.0 394200.0 ; + RECT 70800.0 391950.0 72000.0 390750.0 ; + RECT 73200.0 400650.0 74400.0 399450.0 ; + RECT 74400.0 395400.0 73200.0 394200.0 ; + RECT 69000.0 395400.0 70200.0 394200.0 ; + RECT 72000.0 398100.0 73200.0 396900.0 ; + RECT 73200.0 395400.0 74400.0 394200.0 ; + RECT 66600.0 389250.0 81000.0 388350.0 ; + RECT 66600.0 403050.0 81000.0 402150.0 ; + RECT 87600.0 390750.0 88800.0 388800.0 ; + RECT 87600.0 402600.0 88800.0 400650.0 ; + RECT 82800.0 401250.0 84000.0 403050.0 ; + RECT 82800.0 391950.0 84000.0 388350.0 ; + RECT 85500.0 401250.0 86400.0 391950.0 ; + RECT 82800.0 391950.0 84000.0 390750.0 ; + RECT 85200.0 391950.0 86400.0 390750.0 ; + RECT 85200.0 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RECT 128100.0 15750.0 131700.0 16650.0 ; + RECT 131250.0 16200.0 132150.0 18000.0 ; + RECT 53400.0 430200.0 54300.0 432300.0 ; + RECT 116400.0 209400.0 126600.0 223200.0 ; + RECT 116400.0 237000.0 126600.0 223200.0 ; + RECT 116400.0 237000.0 126600.0 250800.0 ; + RECT 116400.0 264600.0 126600.0 250800.0 ; + RECT 116400.0 264600.0 126600.0 278400.0 ; + RECT 116400.0 292200.0 126600.0 278400.0 ; + RECT 116400.0 292200.0 126600.0 306000.0 ; + RECT 116400.0 319800.0 126600.0 306000.0 ; + RECT 116400.0 319800.0 126600.0 333600.0 ; + RECT 116400.0 347400.0 126600.0 333600.0 ; + RECT 116400.0 347400.0 126600.0 361200.0 ; + RECT 116400.0 375000.0 126600.0 361200.0 ; + RECT 116400.0 375000.0 126600.0 388800.0 ; + RECT 116400.0 402600.0 126600.0 388800.0 ; + RECT 116400.0 402600.0 126600.0 416400.0 ; + RECT 116400.0 430200.0 126600.0 416400.0 ; + RECT 126600.0 209400.0 136800.0 223200.0 ; + RECT 126600.0 237000.0 136800.0 223200.0 ; + RECT 126600.0 237000.0 136800.0 250800.0 ; + RECT 126600.0 264600.0 136800.0 250800.0 ; + RECT 126600.0 264600.0 136800.0 278400.0 ; + RECT 126600.0 292200.0 136800.0 278400.0 ; + RECT 126600.0 292200.0 136800.0 306000.0 ; + RECT 126600.0 319800.0 136800.0 306000.0 ; + RECT 126600.0 319800.0 136800.0 333600.0 ; + RECT 126600.0 347400.0 136800.0 333600.0 ; + RECT 126600.0 347400.0 136800.0 361200.0 ; + RECT 126600.0 375000.0 136800.0 361200.0 ; + RECT 126600.0 375000.0 136800.0 388800.0 ; + RECT 126600.0 402600.0 136800.0 388800.0 ; + RECT 126600.0 402600.0 136800.0 416400.0 ; + RECT 126600.0 430200.0 136800.0 416400.0 ; + RECT 119400.0 210000.0 120600.0 433800.0 ; + RECT 122400.0 208800.0 123600.0 432600.0 ; + RECT 129600.0 210000.0 130800.0 433800.0 ; + RECT 132600.0 208800.0 133800.0 432600.0 ; + RECT 115800.0 208800.0 117000.0 432600.0 ; + RECT 126000.0 208800.0 127200.0 432600.0 ; + RECT 136200.0 208800.0 137400.0 432600.0 ; + RECT 119400.0 436200.0 120600.0 437400.0 ; + RECT 121800.0 436200.0 123450.0 437400.0 ; + RECT 119400.0 443400.0 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24900.0 122100.0 18000.0 ; + RECT 131100.0 24900.0 132300.0 18000.0 ; + RECT 120900.0 39900.0 122100.0 38400.0 ; + RECT 131100.0 39900.0 132300.0 38400.0 ; + RECT 9900.0 99000.0 10800.0 430200.0 ; + RECT 12000.0 99000.0 12900.0 430200.0 ; + RECT 14100.0 99000.0 15000.0 430200.0 ; + RECT 16200.0 99000.0 17100.0 430200.0 ; + RECT 18300.0 99000.0 19200.0 430200.0 ; + RECT 20400.0 99000.0 21300.0 430200.0 ; + RECT 22500.0 99000.0 23400.0 430200.0 ; + RECT 24600.0 99000.0 25500.0 430200.0 ; + RECT 56700.0 99000.0 55800.0 152400.0 ; + RECT 53700.0 99000.0 52800.0 152400.0 ; + RECT 62700.0 99000.0 61800.0 152400.0 ; + RECT 59700.0 99000.0 58800.0 152400.0 ; + RECT 46350.0 106350.0 45450.0 107250.0 ; + RECT 43950.0 106350.0 43050.0 107250.0 ; + RECT 46350.0 106800.0 45450.0 109650.0 ; + RECT 45900.0 106350.0 43500.0 107250.0 ; + RECT 43950.0 102150.0 43050.0 106800.0 ; + RECT 46500.0 109650.0 45300.0 110850.0 ; + RECT 44100.0 100950.0 42900.0 102150.0 ; + RECT 42900.0 106200.0 44100.0 107400.0 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42900.0 147000.0 44100.0 145800.0 ; + RECT 61650.0 109500.0 62850.0 110700.0 ; + RECT 80250.0 105000.0 81450.0 106200.0 ; + RECT 58650.0 123300.0 59850.0 124500.0 ; + RECT 77250.0 119400.0 78450.0 120600.0 ; + RECT 80250.0 128100.0 81450.0 129300.0 ; + RECT 55650.0 128100.0 56850.0 129300.0 ; + RECT 77250.0 141900.0 78450.0 143100.0 ; + RECT 52650.0 141900.0 53850.0 143100.0 ; + RECT 61650.0 106200.0 62850.0 107400.0 ; + RECT 58650.0 103500.0 59850.0 104700.0 ; + RECT 55650.0 118200.0 56850.0 119400.0 ; + RECT 58650.0 120900.0 59850.0 122100.0 ; + RECT 61650.0 133800.0 62850.0 135000.0 ; + RECT 52650.0 131100.0 53850.0 132300.0 ; + RECT 55650.0 145800.0 56850.0 147000.0 ; + RECT 52650.0 148500.0 53850.0 149700.0 ; + RECT 81300.0 99000.0 80400.0 152400.0 ; + RECT 78300.0 99000.0 77400.0 152400.0 ; + RECT 56700.0 154200.0 55800.0 207600.0 ; + RECT 53700.0 154200.0 52800.0 207600.0 ; + RECT 62700.0 154200.0 61800.0 207600.0 ; + RECT 59700.0 154200.0 58800.0 207600.0 ; + RECT 46350.0 161550.0 45450.0 162450.0 ; + RECT 43950.0 161550.0 43050.0 162450.0 ; + RECT 46350.0 162000.0 45450.0 164850.0 ; + RECT 45900.0 161550.0 43500.0 162450.0 ; + RECT 43950.0 157350.0 43050.0 162000.0 ; + RECT 46500.0 164850.0 45300.0 166050.0 ; + RECT 44100.0 156150.0 42900.0 157350.0 ; + RECT 42900.0 161400.0 44100.0 162600.0 ; + RECT 46350.0 174450.0 45450.0 173550.0 ; + RECT 43950.0 174450.0 43050.0 173550.0 ; + RECT 46350.0 174000.0 45450.0 171150.0 ; + RECT 45900.0 174450.0 43500.0 173550.0 ; + RECT 43950.0 178650.0 43050.0 174000.0 ; + RECT 46500.0 171150.0 45300.0 169950.0 ; + RECT 44100.0 179850.0 42900.0 178650.0 ; + RECT 42900.0 174600.0 44100.0 173400.0 ; + RECT 46350.0 189150.0 45450.0 190050.0 ; + RECT 43950.0 189150.0 43050.0 190050.0 ; + RECT 46350.0 189600.0 45450.0 192450.0 ; + RECT 45900.0 189150.0 43500.0 190050.0 ; + RECT 43950.0 184950.0 43050.0 189600.0 ; + RECT 46500.0 192450.0 45300.0 193650.0 ; + RECT 44100.0 183750.0 42900.0 184950.0 ; + RECT 42900.0 189000.0 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202200.0 ; + RECT 52650.0 203700.0 53850.0 204900.0 ; + RECT 81300.0 154200.0 80400.0 207600.0 ; + RECT 78300.0 154200.0 77400.0 207600.0 ; + RECT 31050.0 216750.0 31950.0 217650.0 ; + RECT 33450.0 216750.0 34350.0 217650.0 ; + RECT 31050.0 217200.0 31950.0 220050.0 ; + RECT 31500.0 216750.0 33900.0 217650.0 ; + RECT 33450.0 212550.0 34350.0 217200.0 ; + RECT 30900.0 220050.0 32100.0 221250.0 ; + RECT 33300.0 211350.0 34500.0 212550.0 ; + RECT 34500.0 216600.0 33300.0 217800.0 ; + RECT 31050.0 229650.0 31950.0 228750.0 ; + RECT 33450.0 229650.0 34350.0 228750.0 ; + RECT 31050.0 229200.0 31950.0 226350.0 ; + RECT 31500.0 229650.0 33900.0 228750.0 ; + RECT 33450.0 233850.0 34350.0 229200.0 ; + RECT 30900.0 226350.0 32100.0 225150.0 ; + RECT 33300.0 235050.0 34500.0 233850.0 ; + RECT 34500.0 229800.0 33300.0 228600.0 ; + RECT 31050.0 244350.0 31950.0 245250.0 ; + RECT 33450.0 244350.0 34350.0 245250.0 ; + RECT 31050.0 244800.0 31950.0 247650.0 ; + RECT 31500.0 244350.0 33900.0 245250.0 ; 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72000.0 241500.0 70800.0 242700.0 ; + RECT 70950.0 257250.0 71850.0 256350.0 ; + RECT 73350.0 257250.0 74250.0 256350.0 ; + RECT 70950.0 256800.0 71850.0 253950.0 ; + RECT 71400.0 257250.0 73800.0 256350.0 ; + RECT 73350.0 261450.0 74250.0 256800.0 ; + RECT 70800.0 253950.0 72000.0 252750.0 ; + RECT 73200.0 262650.0 74400.0 261450.0 ; + RECT 74400.0 257400.0 73200.0 256200.0 ; + RECT 53250.0 257400.0 54450.0 258600.0 ; + RECT 55200.0 259800.0 56400.0 261000.0 ; + RECT 72000.0 258900.0 70800.0 260100.0 ; + RECT 70950.0 271950.0 71850.0 272850.0 ; + RECT 73350.0 271950.0 74250.0 272850.0 ; + RECT 70950.0 272400.0 71850.0 275250.0 ; + RECT 71400.0 271950.0 73800.0 272850.0 ; + RECT 73350.0 267750.0 74250.0 272400.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 73200.0 266550.0 74400.0 267750.0 ; + RECT 74400.0 271800.0 73200.0 273000.0 ; + RECT 53250.0 270600.0 54450.0 271800.0 ; + RECT 55200.0 268200.0 56400.0 269400.0 ; + RECT 72000.0 269100.0 70800.0 270300.0 ; + RECT 70950.0 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269850.0 ; + RECT -34050.0 241800.0 -35550.0 272550.0 ; + RECT -29250.0 241800.0 -30750.0 275250.0 ; + RECT -41850.0 241800.0 -43350.0 267150.0 ; + RECT -21450.0 241800.0 -22950.0 267150.0 ; + RECT -16050.0 223500.0 -17550.0 283350.0 ; + RECT -22050.0 283350.0 -23550.0 307200.0 ; + RECT -24750.0 280650.0 -26250.0 310200.0 ; + RECT -48600.0 182700.0 -46800.0 184500.0 ; + RECT -38400.0 182700.0 -36600.0 184500.0 ; + RECT -28200.0 182700.0 -26400.0 184500.0 ; + RECT -49500.0 242700.0 -51300.0 240900.0 ; + RECT -49500.0 281550.0 -51300.0 279750.0 ; + RECT -46050.0 241500.0 -47850.0 239700.0 ; + RECT -46050.0 270750.0 -47850.0 268950.0 ; + RECT -33900.0 242700.0 -35700.0 240900.0 ; + RECT -33900.0 273450.0 -35700.0 271650.0 ; + RECT -29100.0 242700.0 -30900.0 240900.0 ; + RECT -29100.0 276150.0 -30900.0 274350.0 ; + RECT -41700.0 242700.0 -43500.0 240900.0 ; + RECT -41700.0 268050.0 -43500.0 266250.0 ; + RECT -21300.0 242700.0 -23100.0 240900.0 ; + RECT -21300.0 268050.0 -23100.0 266250.0 ; + RECT -15900.0 224400.0 -17700.0 222600.0 ; + RECT -15900.0 284250.0 -17700.0 282450.0 ; + RECT -21900.0 308100.0 -23700.0 306300.0 ; + RECT -21900.0 284250.0 -23700.0 282450.0 ; + RECT -24600.0 311100.0 -26400.0 309300.0 ; + RECT -24600.0 281550.0 -26400.0 279750.0 ; + RECT -36600.0 182700.0 -38400.0 184500.0 ; + RECT -26400.0 182700.0 -28200.0 184500.0 ; + RECT -46800.0 182700.0 -48600.0 184500.0 ; + RECT 111000.0 321600.0 109200.0 323400.0 ; + RECT -3000.0 321750.0 -4800.0 323550.0 ; + RECT 108300.0 341400.0 106500.0 343200.0 ; + RECT -3000.0 341550.0 -4800.0 343350.0 ; + RECT 102900.0 301800.0 101100.0 303600.0 ; + RECT -3000.0 301950.0 -4800.0 303750.0 ; + RECT 100200.0 318900.0 98400.0 320700.0 ; + RECT -3000.0 319050.0 -4800.0 320850.0 ; + RECT 105600.0 282450.0 103800.0 284250.0 ; + RECT -3000.0 282600.0 -4800.0 284400.0 ; + RECT 97500.0 263550.0 95700.0 265350.0 ; + RECT -3000.0 263700.0 -4800.0 265500.0 ; + RECT 7650.0 277050.0 5850.0 278850.0 ; + RECT -3000.0 277200.0 -4800.0 279000.0 ; + END + END sram_2_16_1_scn3me_subm +END LIBRARY diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.sp b/compiler/tests/golden/sram_2_16_1_scn4m_subm.sp new file mode 100644 index 00000000..258b4464 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.sp @@ -0,0 +1,681 @@ +* OpenRAM generated memory. +* User: mrg +.global vdd gnd +*master-slave flip-flop with both output and inverted ouput + +.subckt ms_flop din dout dout_bar clk vdd gnd +xmaster din mout mout_bar clk clk_bar vdd gnd dlatch +xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch +.ends flop + +.subckt dlatch din dout dout_bar clk clk_bar vdd gnd +*clk inverter +mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1 +mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1 + +*transmission gate 1 +mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1 +mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1 + +*foward inverter +mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1 +mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1 + +*backward inverter +mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1 +mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1 + +*transmission gate 2 +mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1 +mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1 +.ends dlatch + + +.SUBCKT inv_nmos11 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos11 + +.SUBCKT inv_pmos12 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS inv_pmos12 + +.SUBCKT pinv A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos11 +Xpinv_pmos Z A vdd vdd inv_pmos12 +.ENDS pinv + +.SUBCKT nand_2_nmos13 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos13 + +.SUBCKT nand_2_nmos24 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos24 + +.SUBCKT nand_2_pmos15 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos15 + +.SUBCKT nand_2_pmos26 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos26 + +.SUBCKT nand2 A B Z vdd gnd +Xnmos1 Z A net1 gnd nand_2_nmos13 +Xnmos2 net1 B gnd gnd nand_2_nmos24 +Xpmos1 vdd A Z vdd nand_2_pmos15 +Xpmos2 Z B vdd vdd nand_2_pmos26 +.ENDS nand2 + +.SUBCKT nand_3_nmos17 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos17 + +.SUBCKT nand_3_nmos28 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos28 + +.SUBCKT nand_3_nmos39 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos39 + +.SUBCKT nand_3_pmos110 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos110 + +.SUBCKT nand_3_pmos211 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos211 + +.SUBCKT nand_3_pmos312 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos312 + +.SUBCKT NAND3 A B C Z vdd gnd +Xnmos1 net2 A gnd gnd nand_3_nmos17 +Xnmos2 net1 B net2 gnd nand_3_nmos28 +Xnmos3 Z C net1 gnd nand_3_nmos39 +Xpmos1 Z A vdd vdd nand_3_pmos110 +Xpmos2 vdd B Z vdd nand_3_pmos211 +Xpmos3 Z C vdd vdd nand_3_pmos312 +.ENDS NAND3 + +.SUBCKT inv_nmos113 D G S B +Mnmos D G S B n m=4 w=1.2u l=0.6u +.ENDS inv_nmos113 + +.SUBCKT inv_pmos114 D G S B +Mpmos D G S B p m=4 w=2.4u l=0.6u +.ENDS inv_pmos114 + +.SUBCKT pinv4 A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos113 +Xpinv_pmos Z A vdd vdd inv_pmos114 +.ENDS pinv4 + +.SUBCKT nor_2_nmos123 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos123 + +.SUBCKT nor_2_nmos224 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos224 + +.SUBCKT nor_2_pmos125 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos125 + +.SUBCKT nor_2_pmos226 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos226 + +.SUBCKT nor2 A B Z vdd gnd +Xnmos1 Z A gnd gnd nor_2_nmos123 +Xnmos2 Z B gnd gnd nor_2_nmos224 +Xpmos1 vdd A net1 vdd nor_2_pmos125 +Xpmos2 net1 B Z vdd nor_2_pmos226 +.ENDS nor2 + +.SUBCKT msf_control DATA[0] DATA[1] DATA[2] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] data_in[2] data_in_bar[2] clk vdd gnd +XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop +XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop +XXdff2 DATA[2] data_in[2] data_in_bar[2] clk vdd gnd ms_flop +.ENDS msf_control + +*********************** "cell_6t" ****************************** +.SUBCKT replica_cell_6t bl br wl vdd gnd +M_1 gnd net_2 vdd vdd p W='0.9u' L=1.2u +M_2 net_2 gnd vdd vdd p W='0.9u' L=1.2u +M_3 br wl net_2 gnd n W='1.2u' L=0.6u +M_4 bl wl gnd gnd n W='1.2u' L=0.6u +M_5 net_2 gnd gnd gnd n W='2.4u' L=0.6u +M_6 gnd net_2 gnd gnd n W='2.4u' L=0.6u +.ENDS $ replica_cell_6t + +*********************** "cell_6t" ****************************** +.SUBCKT cell_6t bl br wl vdd gnd +M_1 net_1 net_2 vdd vdd p W='0.9u' L=1.2u +M_2 net_2 net_1 vdd vdd p W='0.9u' L=1.2u +M_3 br wl net_2 gnd n W='1.2u' L=0.6u +M_4 bl wl net_1 gnd n W='1.2u' L=0.6u +M_5 net_2 net_1 gnd gnd n W='2.4u' L=0.6u +M_6 net_1 net_2 gnd gnd n W='2.4u' L=0.6u +.ENDS $ cell_6t + +.SUBCKT bitline_load bl[0] br[0] wl[0] wl[1] vdd gnd +Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t +Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t +.ENDS bitline_load + +.SUBCKT inv_nmos127 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos127 + +.SUBCKT inv_pmos128 D G S B +Mpmos D G S B p m=1 w=3.6u l=0.6u +.ENDS inv_pmos128 + +.SUBCKT delay_chain_inv A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos127 +Xpinv_pmos Z A vdd vdd inv_pmos128 +.ENDS delay_chain_inv + +.SUBCKT delay_chain clk_in clk_out vdd gnd +Xinv_chain0 clk_in s1 vdd gnd delay_chain_inv +Xinv_chain1 s1 s2 vdd gnd delay_chain_inv +Xinv_chain2 s2 s3 vdd gnd delay_chain_inv +Xinv_chain3 s3 clk_out vdd gnd delay_chain_inv +.ENDS delay_chain + +.SUBCKT inv_nmos129 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos129 + +.SUBCKT inv_pmos130 D G S B +Mpmos D G S B p m=1 w=3.6u l=0.6u +.ENDS inv_pmos130 + +.SUBCKT RBL_inv A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos129 +Xpinv_pmos Z A vdd vdd inv_pmos130 +.ENDS RBL_inv + +.SUBCKT nor_2_nmos139 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos139 + +.SUBCKT nor_2_nmos240 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos240 + +.SUBCKT nor_2_pmos141 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos141 + +.SUBCKT nor_2_pmos242 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos242 + +.SUBCKT replica_bitline_nor2 A B Z vdd gnd +Xnmos1 Z A gnd gnd nor_2_nmos139 +Xnmos2 Z B gnd gnd nor_2_nmos240 +Xpmos1 vdd A net1 vdd nor_2_pmos141 +Xpmos2 net1 B Z vdd nor_2_pmos242 +.ENDS replica_bitline_nor2 + +.SUBCKT access_tx43 D G S B +Mpmos D G S B p m=1 w=1.2u l=0.6u +.ENDS access_tx43 + +.SUBCKT replica_bitline en out vdd gnd +XBL_inv bl[0] out vdd gnd RBL_inv +XBL_access_tx vdd delayed_en bl[0] vdd access_tx43 +Xdelay_chain en delayed_en vdd gnd delay_chain +Xbitcell bl[0] br[0] delayed_en vdd gnd replica_cell_6t +Xload bl[0] br[0] gnd gnd vdd gnd bitline_load +.ENDS replica_bitline + +.SUBCKT control_logic CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd +Xmsf_control CSb WEb OEb CS_bar CS WE_bar WE OE_bar OE clk vdd gnd msf_control +Xclk_inverter clk clk_bar vdd gnd pinv4 +Xnor2 clk OE_bar tri_en vdd gnd nor2 +Xnand2_tri_en OE clk_bar tri_en_bar vdd gnd nand2 +Xreplica_bitline rblk pre_s_en vdd gnd replica_bitline +Xinv_s_en1 pre_s_en_bar s_en vdd gnd pinv +Xinv_s_en2 pre_s_en pre_s_en_bar vdd gnd pinv +XNAND3_rblk_bar clk_bar OE CS rblk_bar vdd gnd NAND3 +XNAND3_w_en_bar clk_bar WE CS w_en_bar vdd gnd NAND3 +Xinv_rblk rblk_bar rblk vdd gnd pinv +Xinv_w_en w_en_bar pre_w_en vdd gnd pinv +Xinv_w_en1 pre_w_en pre_w_en1 vdd gnd pinv +Xinv_w_en2 pre_w_en1 w_en vdd gnd pinv +.ENDS control_logic + +.SUBCKT bitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd +Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t +Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t +Xbit_r2_c0 bl[0] br[0] wl[2] vdd gnd cell_6t +Xbit_r3_c0 bl[0] br[0] wl[3] vdd gnd cell_6t +Xbit_r4_c0 bl[0] br[0] wl[4] vdd gnd cell_6t +Xbit_r5_c0 bl[0] br[0] wl[5] vdd gnd cell_6t +Xbit_r6_c0 bl[0] br[0] wl[6] vdd gnd cell_6t +Xbit_r7_c0 bl[0] br[0] wl[7] vdd gnd cell_6t +Xbit_r8_c0 bl[0] br[0] wl[8] vdd gnd cell_6t +Xbit_r9_c0 bl[0] br[0] wl[9] vdd gnd cell_6t +Xbit_r10_c0 bl[0] br[0] wl[10] vdd gnd cell_6t +Xbit_r11_c0 bl[0] br[0] wl[11] vdd gnd cell_6t +Xbit_r12_c0 bl[0] br[0] wl[12] vdd gnd cell_6t +Xbit_r13_c0 bl[0] br[0] wl[13] vdd gnd cell_6t +Xbit_r14_c0 bl[0] br[0] wl[14] vdd gnd cell_6t +Xbit_r15_c0 bl[0] br[0] wl[15] vdd gnd cell_6t +Xbit_r0_c1 bl[1] br[1] wl[0] vdd gnd cell_6t +Xbit_r1_c1 bl[1] br[1] wl[1] vdd gnd cell_6t +Xbit_r2_c1 bl[1] br[1] wl[2] vdd gnd cell_6t +Xbit_r3_c1 bl[1] br[1] wl[3] vdd gnd cell_6t +Xbit_r4_c1 bl[1] br[1] wl[4] vdd gnd cell_6t +Xbit_r5_c1 bl[1] br[1] wl[5] vdd gnd cell_6t +Xbit_r6_c1 bl[1] br[1] wl[6] vdd gnd cell_6t +Xbit_r7_c1 bl[1] br[1] wl[7] vdd gnd cell_6t +Xbit_r8_c1 bl[1] br[1] wl[8] vdd gnd cell_6t +Xbit_r9_c1 bl[1] br[1] wl[9] vdd gnd cell_6t +Xbit_r10_c1 bl[1] br[1] wl[10] vdd gnd cell_6t +Xbit_r11_c1 bl[1] br[1] wl[11] vdd gnd cell_6t +Xbit_r12_c1 bl[1] br[1] wl[12] vdd gnd cell_6t +Xbit_r13_c1 bl[1] br[1] wl[13] vdd gnd cell_6t +Xbit_r14_c1 bl[1] br[1] wl[14] vdd gnd cell_6t +Xbit_r15_c1 bl[1] br[1] wl[15] vdd gnd cell_6t +.ENDS bitcell_array + +.SUBCKT lower_pmos44 D G S B +Mpmos D G S B p m=1 w=1.2u l=0.6u +.ENDS lower_pmos44 + +.SUBCKT upper_pmos45 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS upper_pmos45 + +.SUBCKT precharge_cell bl br clk vdd +Xlower_pmos bl clk br vdd lower_pmos44 +Xupper_pmos1 bl clk vdd vdd upper_pmos45 +Xupper_pmos2 br clk vdd vdd upper_pmos45 +.ENDS precharge_cell + +.SUBCKT precharge_array bl[0] br[0] bl[1] br[1] clk vdd +Xpre_column_0 bl[0] br[0] clk vdd precharge_cell +Xpre_column_1 bl[1] br[1] clk vdd precharge_cell +.ENDS precharge_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout sclk vdd gnd +M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u +M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u +M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u +M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u +M_5 bl sclk dout vdd p W='7.2*1u' L=0.6u +M_6 br sclk net_1 vdd p W='7.2*1u' L=0.6u +M_7 net_2 sclk gnd gnd n W='2.7*1u' L=0.6u +.ENDS sense_amp + + +.SUBCKT sense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] sclk vdd gnd +Xsa_d0 bl[0] br[0] data_out[0] sclk vdd gnd sense_amp +Xsa_d1 bl[1] br[1] data_out[1] sclk vdd gnd sense_amp +.ENDS sense_amp_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br wen vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +M_1 net_3 din gnd gnd n W='1.2*1u' L=0.6u +M_2 net_3 din vdd vdd p W='2.1*1u' L=0.6u + +**** 2input nand gate follwed by inverter to drive BL ****** +M_3 net_2 wen net_7 gnd n W='2.1*1u' L=0.6u +M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u +M_5 net_2 wen vdd vdd p W='2.1*1u' L=0.6u +M_6 net_2 din vdd vdd p W='2.1*1u' L=0.6u + + +M_7 net_1 net_2 vdd vdd p W='2.1*1u' L=0.6u +M_8 net_1 net_2 gnd gnd n W='1.2*1u' L=0.6u + +**** 2input nand gate follwed by inverter to drive BR****** + +M_9 net_4 wen vdd vdd p W='2.1*1u' L=0.6u +M_10 net_4 wen net_8 gnd n W='2.1*1u' L=0.6u +M_11 net_8 net_3 gnd gnd n W='2.1*1u' L=0.6u +M_12 net_4 net_3 vdd vdd p W='2.1*1u' L=0.6u + +M_13 net_6 net_4 vdd vdd p W='2.1*1u' L=0.6u +M_14 net_6 net_4 gnd gnd n W='1.2*1u' L=0.6u + +************************************************ + +M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u +M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u +M_17 net_5 wen gnd gnd n W='3.6*1u' L=0.6u + + + +.ENDS $ write_driver + + +.SUBCKT write_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] wen vdd gnd +XXwrite_driver0 data_in[0] bl[0] br[0] wen vdd gnd write_driver +XXwrite_driver1 data_in[1] bl[1] br[1] wen vdd gnd write_driver +.ENDS write_driver_array + +.SUBCKT inv_nmos147 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos147 + +.SUBCKT inv_pmos148 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS inv_pmos148 + +.SUBCKT INVERTER A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos147 +Xpinv_pmos Z A vdd vdd inv_pmos148 +.ENDS INVERTER + +.SUBCKT nand_2_nmos149 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos149 + +.SUBCKT nand_2_nmos250 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos250 + +.SUBCKT nand_2_pmos151 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos151 + +.SUBCKT nand_2_pmos252 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos252 + +.SUBCKT NAND2 A B Z vdd gnd +Xnmos1 Z A net1 gnd nand_2_nmos149 +Xnmos2 net1 B gnd gnd nand_2_nmos250 +Xpmos1 vdd A Z vdd nand_2_pmos151 +Xpmos2 Z B vdd vdd nand_2_pmos252 +.ENDS NAND2 + +.SUBCKT nand_2_nmos159 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos159 + +.SUBCKT nand_2_nmos260 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos260 + +.SUBCKT nand_2_pmos161 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos161 + +.SUBCKT nand_2_pmos262 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos262 + +.SUBCKT a_nand_2 A B Z vdd gnd +Xnmos1 Z A net1 gnd nand_2_nmos159 +Xnmos2 net1 B gnd gnd nand_2_nmos260 +Xpmos1 vdd A Z vdd nand_2_pmos161 +Xpmos2 Z B vdd vdd nand_2_pmos262 +.ENDS a_nand_2 + +.SUBCKT inv_nmos163 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos163 + +.SUBCKT inv_pmos164 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS inv_pmos164 + +.SUBCKT a_inv_1 A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos163 +Xpinv_pmos Z A vdd vdd inv_pmos164 +.ENDS a_inv_1 + +.SUBCKT pre2x4 A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd +XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1 +XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1 +XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1 +XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1 +XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1 +XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1 +XXpre2x4_nand[0] A[0] A[1] Z[3] vdd gnd a_nand_2 +XXpre2x4_nand[1] B[0] A[1] Z[2] vdd gnd a_nand_2 +XXpre2x4_nand[2] A[0] B[1] Z[1] vdd gnd a_nand_2 +XXpre2x4_nand[3] B[0] B[1] Z[0] vdd gnd a_nand_2 +.ENDS pre2x4 + +.SUBCKT nand_3_nmos165 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos165 + +.SUBCKT nand_3_nmos266 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos266 + +.SUBCKT nand_3_nmos367 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos367 + +.SUBCKT nand_3_pmos168 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos168 + +.SUBCKT nand_3_pmos269 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos269 + +.SUBCKT nand_3_pmos370 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos370 + +.SUBCKT a_nand_3 A B C Z vdd gnd +Xnmos1 net2 A gnd gnd nand_3_nmos165 +Xnmos2 net1 B net2 gnd nand_3_nmos266 +Xnmos3 Z C net1 gnd nand_3_nmos367 +Xpmos1 Z A vdd vdd nand_3_pmos168 +Xpmos2 vdd B Z vdd nand_3_pmos269 +Xpmos3 Z C vdd vdd nand_3_pmos370 +.ENDS a_nand_3 + +.SUBCKT pre3x8 A[0] A[1] A[2] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] vdd gnd +XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1 +XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1 +XXpre2x4_inv[2] A[2] B[2] vdd gnd a_inv_1 +XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1 +XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1 +XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1 +XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1 +XXpre2x4_nand_inv[4] Z[4] out[4] vdd gnd a_inv_1 +XXpre2x4_nand_inv[5] Z[5] out[5] vdd gnd a_inv_1 +XXpre2x4_nand_inv[6] Z[6] out[6] vdd gnd a_inv_1 +XXpre2x4_nand_inv[7] Z[7] out[7] vdd gnd a_inv_1 +XXpre3x8_nand[0] A[0] A[1] A[2] Z[7] vdd gnd a_nand_3 +XXpre3x8_nand[1] A[0] A[1] B[2] Z[6] vdd gnd a_nand_3 +XXpre3x8_nand[2] A[0] B[1] A[2] Z[5] vdd gnd a_nand_3 +XXpre3x8_nand[3] A[0] B[1] B[2] Z[4] vdd gnd a_nand_3 +XXpre3x8_nand[4] B[0] A[1] A[2] Z[3] vdd gnd a_nand_3 +XXpre3x8_nand[5] B[0] A[1] B[2] Z[2] vdd gnd a_nand_3 +XXpre3x8_nand[6] B[0] B[1] A[2] Z[1] vdd gnd a_nand_3 +XXpre3x8_nand[7] B[0] B[1] B[2] Z[0] vdd gnd a_nand_3 +.ENDS pre3x8 + +.SUBCKT hierarchical_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd +Xpre[0] A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd pre2x4 +Xpre[1] A[2] A[3] out[4] out[5] out[6] out[7] vdd gnd pre2x4 +XNAND2_[0] out[0] out[4] Z[0] vdd gnd NAND2 +XNAND2_[1] out[0] out[5] Z[1] vdd gnd NAND2 +XNAND2_[2] out[0] out[6] Z[2] vdd gnd NAND2 +XNAND2_[3] out[0] out[7] Z[3] vdd gnd NAND2 +XNAND2_[4] out[1] out[4] Z[4] vdd gnd NAND2 +XNAND2_[5] out[1] out[5] Z[5] vdd gnd NAND2 +XNAND2_[6] out[1] out[6] Z[6] vdd gnd NAND2 +XNAND2_[7] out[1] out[7] Z[7] vdd gnd NAND2 +XNAND2_[8] out[2] out[4] Z[8] vdd gnd NAND2 +XNAND2_[9] out[2] out[5] Z[9] vdd gnd NAND2 +XNAND2_[10] out[2] out[6] Z[10] vdd gnd NAND2 +XNAND2_[11] out[2] out[7] Z[11] vdd gnd NAND2 +XNAND2_[12] out[3] out[4] Z[12] vdd gnd NAND2 +XNAND2_[13] out[3] out[5] Z[13] vdd gnd NAND2 +XNAND2_[14] out[3] out[6] Z[14] vdd gnd NAND2 +XNAND2_[15] out[3] out[7] Z[15] vdd gnd NAND2 +XINVERTER_[0] Z[0] decode_out[0] vdd gnd INVERTER +XINVERTER_[1] Z[1] decode_out[1] vdd gnd INVERTER +XINVERTER_[2] Z[2] decode_out[2] vdd gnd INVERTER +XINVERTER_[3] Z[3] decode_out[3] vdd gnd INVERTER +XINVERTER_[4] Z[4] decode_out[4] vdd gnd INVERTER +XINVERTER_[5] Z[5] decode_out[5] vdd gnd INVERTER +XINVERTER_[6] Z[6] decode_out[6] vdd gnd INVERTER +XINVERTER_[7] Z[7] decode_out[7] vdd gnd INVERTER +XINVERTER_[8] Z[8] decode_out[8] vdd gnd INVERTER +XINVERTER_[9] Z[9] decode_out[9] vdd gnd INVERTER +XINVERTER_[10] Z[10] decode_out[10] vdd gnd INVERTER +XINVERTER_[11] Z[11] decode_out[11] vdd gnd INVERTER +XINVERTER_[12] Z[12] decode_out[12] vdd gnd INVERTER +XINVERTER_[13] Z[13] decode_out[13] vdd gnd INVERTER +XINVERTER_[14] Z[14] decode_out[14] vdd gnd INVERTER +XINVERTER_[15] Z[15] decode_out[15] vdd gnd INVERTER +.ENDS hierarchical_decoder + +.SUBCKT msf_address ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] addr_clk vdd gnd +XXdff0 ADDR[0] A[0] A_bar[0] addr_clk vdd gnd ms_flop +XXdff1 ADDR[1] A[1] A_bar[1] addr_clk vdd gnd ms_flop +XXdff2 ADDR[2] A[2] A_bar[2] addr_clk vdd gnd ms_flop +XXdff3 ADDR[3] A[3] A_bar[3] addr_clk vdd gnd ms_flop +.ENDS msf_address + +.SUBCKT msf_data_in DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk vdd gnd +XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop +XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop +.ENDS msf_data_in + +.SUBCKT msf_data_out data_out[0] data_out[1] tri_in[0] tri_in_bar[0] tri_in[1] tri_in_bar[1] sclk vdd gnd +XXdff0 data_out[0] tri_in[0] tri_in_bar[0] sclk vdd gnd ms_flop +XXdff1 data_out[1] tri_in[1] tri_in_bar[1] sclk vdd gnd ms_flop +.ENDS msf_data_out +*********************** tri_gate ****************************** + +.SUBCKT tri_gate in out en en_bar vdd gnd + +M_1 net_2 in_inv gnd gnd n W='1.2*1u' L=0.6u +M_2 net_3 in_inv vdd vdd p W='2.4*1u' L=0.6u +M_3 out en_bar net_3 vdd p W='2.4*1u' L=0.6u +M_4 out en net_2 gnd n W='1.2*1u' L=0.6u +M_5 in_inv in vdd vdd p W='2.4*1u' L=0.6u +M_6 in_inv in gnd gnd n W='1.2*1u' L=0.6u + + +.ENDS + +.SUBCKT tri_gate_array tri_in[0] tri_in[1] DATA[0] DATA[1] en en_bar vdd gnd +XXtri_gate0 tri_in[0] DATA[0] en en_bar vdd gnd tri_gate +XXtri_gate1 tri_in[1] DATA[1] en en_bar vdd gnd tri_gate +.ENDS tri_gate_array + +.SUBCKT wordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd +XWordline_driver_inv_clk0 clk clk_bar[0] vdd gnd INVERTER +XWordline_driver_nand0 decode_out[0] clk_bar[0] net[0] vdd gnd NAND2 +XWordline_driver_inv0 net[0] wl[0] vdd gnd INVERTER +XWordline_driver_inv_clk1 clk clk_bar[1] vdd gnd INVERTER +XWordline_driver_nand1 decode_out[1] clk_bar[1] net[1] vdd gnd NAND2 +XWordline_driver_inv1 net[1] wl[1] vdd gnd INVERTER +XWordline_driver_inv_clk2 clk clk_bar[2] vdd gnd INVERTER +XWordline_driver_nand2 decode_out[2] clk_bar[2] net[2] vdd gnd NAND2 +XWordline_driver_inv2 net[2] wl[2] vdd gnd INVERTER +XWordline_driver_inv_clk3 clk clk_bar[3] vdd gnd INVERTER +XWordline_driver_nand3 decode_out[3] clk_bar[3] net[3] vdd gnd NAND2 +XWordline_driver_inv3 net[3] wl[3] vdd gnd INVERTER +XWordline_driver_inv_clk4 clk clk_bar[4] vdd gnd INVERTER +XWordline_driver_nand4 decode_out[4] clk_bar[4] net[4] vdd gnd NAND2 +XWordline_driver_inv4 net[4] wl[4] vdd gnd INVERTER +XWordline_driver_inv_clk5 clk clk_bar[5] vdd gnd INVERTER +XWordline_driver_nand5 decode_out[5] clk_bar[5] net[5] vdd gnd NAND2 +XWordline_driver_inv5 net[5] wl[5] vdd gnd INVERTER +XWordline_driver_inv_clk6 clk clk_bar[6] vdd gnd INVERTER +XWordline_driver_nand6 decode_out[6] clk_bar[6] net[6] vdd gnd NAND2 +XWordline_driver_inv6 net[6] wl[6] vdd gnd INVERTER +XWordline_driver_inv_clk7 clk clk_bar[7] vdd gnd INVERTER +XWordline_driver_nand7 decode_out[7] clk_bar[7] net[7] vdd gnd NAND2 +XWordline_driver_inv7 net[7] wl[7] vdd gnd INVERTER +XWordline_driver_inv_clk8 clk clk_bar[8] vdd gnd INVERTER +XWordline_driver_nand8 decode_out[8] clk_bar[8] net[8] vdd gnd NAND2 +XWordline_driver_inv8 net[8] wl[8] vdd gnd INVERTER +XWordline_driver_inv_clk9 clk clk_bar[9] vdd gnd INVERTER +XWordline_driver_nand9 decode_out[9] clk_bar[9] net[9] vdd gnd NAND2 +XWordline_driver_inv9 net[9] wl[9] vdd gnd INVERTER +XWordline_driver_inv_clk10 clk clk_bar[10] vdd gnd INVERTER +XWordline_driver_nand10 decode_out[10] clk_bar[10] net[10] vdd gnd NAND2 +XWordline_driver_inv10 net[10] wl[10] vdd gnd INVERTER +XWordline_driver_inv_clk11 clk clk_bar[11] vdd gnd INVERTER +XWordline_driver_nand11 decode_out[11] clk_bar[11] net[11] vdd gnd NAND2 +XWordline_driver_inv11 net[11] wl[11] vdd gnd INVERTER +XWordline_driver_inv_clk12 clk clk_bar[12] vdd gnd INVERTER +XWordline_driver_nand12 decode_out[12] clk_bar[12] net[12] vdd gnd NAND2 +XWordline_driver_inv12 net[12] wl[12] vdd gnd INVERTER +XWordline_driver_inv_clk13 clk clk_bar[13] vdd gnd INVERTER +XWordline_driver_nand13 decode_out[13] clk_bar[13] net[13] vdd gnd NAND2 +XWordline_driver_inv13 net[13] wl[13] vdd gnd INVERTER +XWordline_driver_inv_clk14 clk clk_bar[14] vdd gnd INVERTER +XWordline_driver_nand14 decode_out[14] clk_bar[14] net[14] vdd gnd NAND2 +XWordline_driver_inv14 net[14] wl[14] vdd gnd INVERTER +XWordline_driver_inv_clk15 clk clk_bar[15] vdd gnd INVERTER +XWordline_driver_nand15 decode_out[15] clk_bar[15] net[15] vdd gnd NAND2 +XWordline_driver_inv15 net[15] wl[15] vdd gnd INVERTER +.ENDS wordline_driver + +.SUBCKT inv_nmos181 D G S B +Mnmos D G S B n m=4 w=1.2u l=0.6u +.ENDS inv_nmos181 + +.SUBCKT inv_pmos182 D G S B +Mpmos D G S B p m=4 w=2.4u l=0.6u +.ENDS inv_pmos182 + +.SUBCKT pinv4x A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos181 +Xpinv_pmos Z A vdd vdd inv_pmos182 +.ENDS pinv4x + +.SUBCKT nor_2_nmos195 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos195 + +.SUBCKT nor_2_nmos296 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos296 + +.SUBCKT nor_2_pmos197 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos197 + +.SUBCKT nor_2_pmos298 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos298 + +.SUBCKT NOR2 A B Z vdd gnd +Xnmos1 Z A gnd gnd nor_2_nmos195 +Xnmos2 Z B gnd gnd nor_2_nmos296 +Xpmos1 vdd A net1 vdd nor_2_pmos197 +Xpmos2 net1 B Z vdd nor_2_pmos298 +.ENDS NOR2 + +.SUBCKT test_bank1 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd +Xbitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd bitcell_array +Xprecharge_array bl[0] br[0] bl[1] br[1] clk_bar vdd precharge_array +Xsense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] s_en vdd gnd sense_amp_array +Xwrite_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] w_en vdd gnd write_driver_array +Xdata_in_flop_array DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk_bar vdd gnd msf_data_in +Xtrigate_data_array data_out[0] data_out[1] DATA[0] DATA[1] tri_en tri_en_bar vdd gnd tri_gate_array +Xaddress_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd hierarchical_decoder +Xwordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd wordline_driver +Xaddress_flop_array ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] clk vdd gnd msf_address +.ENDS test_bank1 + +.SUBCKT testsram DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] CSb WEb OEb clk vdd gnd +Xbank0 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd test_bank1 +Xcontrol CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd control_logic +.ENDS testsram diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v new file mode 100644 index 00000000..de4c077c --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v @@ -0,0 +1,47 @@ +// OpenRAM SRAM model +// Words: 16 +// Word size: 2 + +module sram_2_16_1_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk); + + parameter DATA_WIDTH = 2 ; + parameter ADDR_WIDTH = 4 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + parameter DELAY = 3 ; + + inout [DATA_WIDTH-1:0] DATA; + input [ADDR_WIDTH-1:0] ADDR; + input CSb; // active low chip select + input WEb; // active low write control + input OEb; // active output enable + input clk; // clock + + reg [DATA_WIDTH-1:0] data_out ; + reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Tri-State Buffer control + // output : When WEb = 1, oeb = 0, csb = 0 + assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz; + + // Memory Write Block + // Write Operation : When WEb = 0, CSb = 0 + always @ (posedge clk) + begin : MEM_WRITE + if ( !CSb && !WEb ) begin + mem[ADDR] = DATA; + $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA); + end + end + + + // Memory Read Block + // Read Operation : When WEb = 1, CSb = 0 + always @ (posedge clk) + begin : MEM_READ + if (!CSb && WEb) begin + data_out <= #(DELAY) mem[ADDR]; + $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]); + end + end + +endmodule diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib new file mode 100644 index 00000000..89f40320 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -0,0 +1,318 @@ +library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 60176.520000000004; + + leakage_power () { + when : "CSb0"; + value : 0.000175; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk; + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + timing(){ + timing_sense : non_unate; + related_pin : "clk"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + cell_fall(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + rise_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + fall_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk & !WEb0"; + rise_power(scalar){ + values("11.3007276371"); + } + fall_power(scalar){ + values("11.3007276371"); + } + } + internal_power(){ + when : "!CSb0 & !clk & WEb0"; + rise_power(scalar){ + values("11.3007276371"); + } + fall_power(scalar){ + values("11.3007276371"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + } +} diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib new file mode 100644 index 00000000..89f40320 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -0,0 +1,318 @@ +library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 60176.520000000004; + + leakage_power () { + when : "CSb0"; + value : 0.000175; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk; + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + timing(){ + timing_sense : non_unate; + related_pin : "clk"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + cell_fall(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + rise_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + fall_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk & !WEb0"; + rise_power(scalar){ + values("11.3007276371"); + } + fall_power(scalar){ + values("11.3007276371"); + } + } + internal_power(){ + when : "!CSb0 & !clk & WEb0"; + rise_power(scalar){ + values("11.3007276371"); + } + fall_power(scalar){ + values("11.3007276371"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + } +} diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib new file mode 100644 index 00000000..8509fc30 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -0,0 +1,318 @@ +library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 60176.520000000004; + + leakage_power () { + when : "CSb0"; + value : 0.025716199999999998; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk; + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095"); + } + } + timing(){ + timing_sense : non_unate; + related_pin : "clk"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("1.277, 1.297, 1.475",\ + "1.28, 1.3, 1.479",\ + "1.347, 1.367, 1.545"); + } + cell_fall(CELL_TABLE) { + values("3.217, 3.281, 3.71",\ + "3.22, 3.285, 3.714",\ + "3.261, 3.325, 3.75"); + } + rise_transition(CELL_TABLE) { + values("0.122, 0.164, 0.579",\ + "0.122, 0.164, 0.578",\ + "0.122, 0.164, 0.58"); + } + fall_transition(CELL_TABLE) { + values("0.363, 0.396, 0.958",\ + "0.363, 0.396, 0.957",\ + "0.366, 0.399, 0.951"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095"); + } + } + } + + pin(clk){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk & !WEb0"; + rise_power(scalar){ + values("9.141838916666668"); + } + fall_power(scalar){ + values("9.141838916666668"); + } + } + internal_power(){ + when : "!CSb0 & !clk & WEb0"; + rise_power(scalar){ + values("8.304491694444444"); + } + fall_power(scalar){ + values("8.304491694444444"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk; + rise_constraint(scalar) { + values("2.344"); + } + fall_constraint(scalar) { + values("2.344"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk; + rise_constraint(scalar) { + values("4.688"); + } + fall_constraint(scalar) { + values("4.688"); + } + } + } + } +} diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index e1c02f45..79333318 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -225,17 +225,21 @@ class openram_test(unittest.TestCase): check = filecmp.cmp(filename1,filename2) if not check: debug.error("MISMATCH file1={0} file2={1}".format(filename1,filename2)) - f1 = open(filename1,"r") - s1 = f1.readlines().decode('utf-8') + f1 = open(filename1,mode="r",encoding='utf-8') + s1 = f1.readlines() f1.close() - f2 = open(filename2,"r").decode('utf-8') + f2 = open(filename2,mode="r",encoding='utf-8') s2 = f2.readlines() f2.close() mismatches=0 - for line in difflib.unified_diff(s1, s2): + for line in list(difflib.unified_diff(s1, s2)): mismatches += 1 - self.error("DIFF LINES:",line) - if mismatches>10: + if mismatches==0: + print("DIFF LINES:") + + if mismatches<11: + print(line.rstrip('\n')) + else: return False return False else: