mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-07 03:20:39 +02:00
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
This commit is contained in:
Michael Timothy Grimes
@@ -205,7 +205,7 @@ class bank(design.design):
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def add_modules(self):
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""" Create all the modules using the class loader """
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mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver",
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mod_list = ["bitcell", "decoder", "wordline_driver",
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"bitcell_array", "sense_amp_array", "precharge_array",
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"column_mux_array", "write_driver_array",
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"dff", "bank_select"]
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@@ -282,7 +282,7 @@ class control_logic(design.design):
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# Connect the clock rail to the other clock rail
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in_pos = self.ctrl_dff_inst.get_pin("clk").uc()
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mid_pos = in_pos + vector(0,self.m2_pitch)
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mid_pos = in_pos + vector(0,2*self.m2_pitch)
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rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y)
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self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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@@ -21,6 +21,25 @@ class dff(design.design):
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self.height = dff.height
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self.pin_map = dff.pin_map
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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from tech import spice
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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power_leak = spice["msflop_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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from tech import spice, parameter
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c_load = load
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c_para = spice["flop_para_cap"]#ff
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transition_prob = spice["flop_transition_prob"]
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return transition_prob*(c_load + c_para)
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def analytical_delay(self, slew, load = 0.0):
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# dont know how to calculate this now, use constant in tech file
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from tech import spice
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@@ -56,8 +56,8 @@ class hierarchical_predecode(design.design):
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# x offset for input inverters
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self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch
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# x offset to NAND decoder includes the left rails, mid rails and inverters, plus an extra m2 pitch
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self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 1) * self.m2_pitch
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# x offset to NAND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches
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self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch
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# x offset to output inverters
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self.x_off_inv_2 = self.x_off_nand + self.nand.width
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@@ -78,7 +78,7 @@ class hierarchical_predecode(design.design):
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invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)]
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non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)]
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decode_names = invert_names + non_invert_names
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offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, 2*self.m1_width)
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offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width)
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self.decode_rails = self.create_vertical_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=offset,
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@@ -1,50 +0,0 @@
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import globals
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import design
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from math import log
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import design
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from tech import GDS,layer
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import utils
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class ms_flop(design.design):
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"""
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Memory address flip-flop
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"""
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pin_names = ["din", "dout", "dout_bar", "clk", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("ms_flop", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "ms_flop", GDS["unit"], layer["boundary"])
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def __init__(self, name="ms_flop"):
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design.design.__init__(self, name)
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self.width = ms_flop.width
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self.height = ms_flop.height
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self.pin_map = ms_flop.pin_map
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def analytical_delay(self, slew, load = 0.0):
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# dont know how to calculate this now, use constant in tech file
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from tech import spice
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result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
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return result
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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from tech import spice
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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power_leak = spice["msflop_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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from tech import spice, parameter
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c_load = load
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c_para = spice["flop_para_cap"]#ff
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transition_prob = spice["flop_transition_prob"]
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return transition_prob*(c_load + c_para)
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@@ -1,136 +0,0 @@
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import debug
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import design
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from tech import drc
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from math import log
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from vector import vector
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from globals import OPTS
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class ms_flop_array(design.design):
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"""
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An Array of D-Flipflops used for to store Data_in & Data_out of
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Write_driver & Sense_amp, address inputs of column_mux &
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hierdecoder
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"""
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def __init__(self, columns, word_size, name=""):
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self.columns = columns
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self.word_size = word_size
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if name=="":
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name = "flop_array_c{0}_w{1}".format(columns,word_size)
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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self.words_per_row = int(self.columns / self.word_size)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_ms_flop_array()
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def create_layout(self):
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self.width = self.columns * self.ms.width
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self.height = self.ms.height
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self.place_ms_flop_array()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_modules(self):
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from importlib import reload
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c = reload(__import__(OPTS.ms_flop))
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self.mod_ms_flop = getattr(c, OPTS.ms_flop)
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self.ms = self.mod_ms_flop("ms_flop")
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self.add_mod(self.ms)
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def add_pins(self):
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for i in range(self.word_size):
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self.add_pin("din[{0}]".format(i))
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for i in range(self.word_size):
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self.add_pin("dout[{0}]".format(i))
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self.add_pin("dout_bar[{0}]".format(i))
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self.add_pin("clk")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_ms_flop_array(self):
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self.ms_inst={}
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for i in range(0,self.columns,self.words_per_row):
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name = "Xdff{0}".format(i)
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index = int(i/self.words_per_row)
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self.ms_inst[index]=self.add_inst(name=name,
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mod=self.ms)
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self.connect_inst(["din[{0}]".format(index),
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"dout[{0}]".format(index),
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"dout_bar[{0}]".format(index),
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"clk",
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"vdd", "gnd"])
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def place_ms_flop_array(self):
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for i in range(0,self.columns,self.words_per_row):
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index = int(i/self.words_per_row)
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if (i % 2 == 0 or self.words_per_row>1):
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base = vector(i*self.ms.width,0)
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mirror = "R0"
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else:
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base = vector((i+1)*self.ms.width,0)
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mirror = "MY"
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self.ms_inst[index].place(offset=base,
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mirror=mirror)
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def add_layout_pins(self):
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for i in range(self.word_size):
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# Route both supplies
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for n in ["vdd", "gnd"]:
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for supply_pin in self.ms_inst[i].get_pins(n):
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pin_pos = supply_pin.center()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin_pos)
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self.add_layout_pin_rect_center(text=n,
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layer="metal3",
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offset=pin_pos)
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din_pins = self.ms_inst[i].get_pins("din")
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for din_pin in din_pins:
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self.add_layout_pin(text="din[{}]".format(i),
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layer=din_pin.layer,
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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dout_pin = self.ms_inst[i].get_pin("dout")
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self.add_layout_pin(text="dout[{}]".format(i),
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layer="metal2",
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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doutbar_pin = self.ms_inst[i].get_pin("dout_bar")
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self.add_layout_pin(text="dout_bar[{}]".format(i),
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layer="metal2",
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offset=doutbar_pin.ll(),
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width=doutbar_pin.width(),
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height=doutbar_pin.height())
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# Continous clk rail along with label.
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self.add_layout_pin(text="clk",
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layer="metal1",
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offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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def analytical_delay(self, slew, load=0.0):
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return self.ms.analytical_delay(slew=slew, load=load)
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@@ -23,7 +23,7 @@ class multibank(design.design):
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def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""):
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mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver",
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mod_list = ["tri_gate", "bitcell", "decoder", "wordline_driver",
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"bitcell_array", "sense_amp_array", "precharge_array",
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"column_mux_array", "write_driver_array", "tri_gate_array",
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"dff", "bank_select"]
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