Add boundary to every module and pgate for visual debug.

2026-08-31 10:15:46 +02:00 · 2019-06-03 15:27:37 -07:00
parent 1268a7927b
commit fc12ea24e9
23 changed files with 35 additions and 10 deletions
@@ -53,6 +53,7 @@ class dff_inv(design.design):
        self.add_wires()
        self.add_layout_pins()
        
+        self.add_boundary()
        self.DRC_LVS()
        
    def add_pins(self):