From fc12ea24e9292d1d94432bd656d91d6440d266ff Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 27 May 2019 16:32:38 -0700 Subject: [PATCH] Add boundary to every module and pgate for visual debug. --- compiler/base/hierarchy_layout.py | 7 +++++++ compiler/bitcells/pbitcell.py | 6 +----- compiler/modules/bank.py | 1 + compiler/modules/bank_select.py | 1 + compiler/modules/bitcell_array.py | 2 ++ compiler/modules/control_logic.py | 3 ++- compiler/modules/delay_chain.py | 3 ++- compiler/modules/dff_array.py | 1 + compiler/modules/dff_buf.py | 1 + compiler/modules/dff_buf_array.py | 1 + compiler/modules/dff_inv.py | 1 + compiler/modules/dff_inv_array.py | 1 + compiler/modules/hierarchical_decoder.py | 1 + compiler/modules/hierarchical_predecode2x4.py | 1 + compiler/modules/hierarchical_predecode3x8.py | 1 + compiler/modules/precharge_array.py | 1 + compiler/modules/replica_bitline.py | 1 + compiler/modules/sense_amp_array.py | 1 + compiler/modules/single_level_column_mux_array.py | 1 + compiler/modules/tri_gate_array.py | 1 + compiler/modules/wordline_driver.py | 1 + compiler/modules/write_driver_array.py | 1 + compiler/pgates/pgate.py | 7 ++++--- 23 files changed, 35 insertions(+), 10 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e8c1b0b9..2972ecf8 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -879,6 +879,13 @@ class layout(): Wrapper to create a horizontal channel route """ self.create_channel_route(netlist, offset, layer_stack, pitch, vertical=False) + + def add_boundary(self): + """ Add boundary for debugging dimensions """ + self.add_rect(layer="boundary", + offset=vector(0,0), + height=self.height, + width=self.width) def add_enclosure(self, insts, layer="nwell"): """ Add a layer that surrounds the given instances. Useful diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index c9eb3f58..3f0a6073 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -36,6 +36,7 @@ class pbitcell(design.design): self.create_netlist() # We must always create the bitcell layout because some transistor sizes in the other netlists depend on it self.create_layout() + self.add_boundary() def create_netlist(self): self.add_pins() @@ -260,11 +261,6 @@ class pbitcell(design.design): self.height = self.topmost_ypos - self.botmost_ypos self.center_ypos = 0.5*(self.topmost_ypos + self.botmost_ypos) - # Add this boundary for visual debug - self.add_rect(layer="boundary", - offset=vector(self.leftmost_xpos,self.botmost_ypos), - height=self.height, - width=self.width) def create_storage(self): """ diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index a854c40b..e7ec2967 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -47,6 +47,7 @@ class bank(design.design): if not OPTS.netlist_only: debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.") self.create_layout() + self.add_boundary() def create_netlist(self): diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index ac866456..41588e70 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -42,6 +42,7 @@ class bank_select(design.design): self.place_instances() self.route_instances() + self.add_boundary() self.DRC_LVS() diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index f2ab77ac..0bc4011c 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -68,6 +68,8 @@ class bitcell_array(design.design): self.add_layout_pins() + self.add_boundary() + self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 0bf309a6..3c6e31b4 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -67,6 +67,7 @@ class control_logic(design.design): self.place_instances() self.route_all() #self.add_lvs_correspondence_points() + self.add_boundary() self.DRC_LVS() @@ -969,4 +970,4 @@ class control_logic(design.design): total_cin += self.wl_en_driver.get_cin() if self.port_type == 'rw': total_cin +=self.and2.get_cin() - return total_cin \ No newline at end of file + return total_cin diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index 188efffa..99b5875b 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -52,8 +52,9 @@ class delay_chain(design.design): self.place_inverters() self.route_inverters() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() - + def add_pins(self): """ Add the pins of the delay chain""" self.add_pin("in") diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 8b03fe19..53e6b0ba 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -44,6 +44,7 @@ class dff_array(design.design): self.place_dff_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 42e86bc0..d113cd14 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -55,6 +55,7 @@ class dff_buf(design.design): self.place_instances() self.route_wires() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index dfd38760..8b107f04 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -49,6 +49,7 @@ class dff_buf_array(design.design): self.height = self.rows * self.dff.height self.place_dff_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 2f831570..7eecfc68 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -53,6 +53,7 @@ class dff_inv(design.design): self.add_wires() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 3ae50a08..c8743722 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -49,6 +49,7 @@ class dff_inv_array(design.design): self.place_dff_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 1eac268d..b316e631 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -54,6 +54,7 @@ class hierarchical_decoder(design.design): self.route_predecode_rails() self.route_vdd_gnd() self.offset_all_coordinates() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index 938196d3..1efdae20 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -47,6 +47,7 @@ class hierarchical_predecode2x4(hierarchical_predecode): self.place_output_inverters() self.place_nand_array() self.route() + self.add_boundary() self.DRC_LVS() def get_nand_input_line_combination(self): diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index 77d9ce01..85069202 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -52,6 +52,7 @@ class hierarchical_predecode3x8(hierarchical_predecode): self.place_output_inverters() self.place_nand_array() self.route() + self.add_boundary() self.DRC_LVS() def get_nand_input_line_combination(self): diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index f88938c8..fa19d3d5 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -51,6 +51,7 @@ class precharge_array(design.design): self.place_insts() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index acd1f5d0..1371bb68 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -49,6 +49,7 @@ class replica_bitline(design.design): self.width = self.replica_column_inst.rx() - self.delay_chain_inst.lx() + self.m2_pitch self.height = max(self.replica_column_inst.uy(), self.delay_chain_inst.uy()) + self.m3_pitch + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 4dfa03ad..81b2218d 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -50,6 +50,7 @@ class sense_amp_array(design.design): self.place_sense_amp_array() self.add_layout_pins() self.route_rails() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 435f0cbe..e7a72856 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -52,6 +52,7 @@ class single_level_column_mux_array(design.design): self.add_layout_pins() self.add_enclosure(self.mux_inst, "pwell") + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index e3eb42cb..54760572 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -41,6 +41,7 @@ class tri_gate_array(design.design): self.place_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_modules(self): diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index dbef0417..f81cdd1a 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -44,6 +44,7 @@ class wordline_driver(design.design): self.route_layout() self.route_vdd_gnd() self.offset_all_coordinates() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 27da84b0..c2ceb386 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -50,6 +50,7 @@ class write_driver_array(design.design): self.place_write_array() self.add_layout_pins() + self.add_boundary() self.DRC_LVS() def add_pins(self): diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 57b73a21..40c04cb6 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -31,17 +31,18 @@ class pgate(design.design): self.create_netlist() if not OPTS.netlist_only: self.create_layout() + self.add_boundary() self.DRC_LVS() - def create_netlist(): + def create_netlist(self): """ Pure virtual function """ debug.error("Must over-ride create_netlist.",-1) - def create_layout(): + def create_layout(self): """ Pure virtual function """ debug.error("Must over-ride create_layout.",-1) - + def connect_pin_to_rail(self,inst,pin,supply): """ Connects a ptx pin to a supply rail. """ source_pin = inst.get_pin(pin)