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Merge multiple cell_name fix.

This commit is contained in:
mrg 2020-11-18 16:27:28 -08:00
parent 8c72d3f2e7
commit fbed738b4a
4 changed files with 21 additions and 19 deletions
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6
compiler/base/design.py
View File

@ -28,11 +28,11 @@ class design(hierarchy_design):
# depending on the number of ports. # depending on the number of ports.
if name in props.names: if name in props.names:
if type(name) is list: if type(props.names[name]) is list:
num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports - 1
cell_name = props.names[name][num_ports] cell_name = props.names[name][num_ports]
else: else:
cell_name = props.name[name] cell_name = props.names[name]
elif not cell_name: elif not cell_name:
cell_name = name cell_name = name

16
compiler/base/hierarchy_design.py
View File

@ -21,22 +21,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
name_map = [] name_map = []
def __init__(self, name, cell_name): def __init__(self, name, cell_name):
self.gds_file = OPTS.openram_tech + "gds_lib/" + cell_name + ".gds"
self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp"
# If we have a separate lvs directory, then all the lvs files
# should be in there (all or nothing!)
try:
lvs_subdir = tech.lvs_lib
except AttributeError:
lvs_subdir = "lvs_lib"
lvs_dir = OPTS.openram_tech + lvs_subdir + "/"
if os.path.exists(lvs_dir):
self.lvs_file = lvs_dir + cell_name + ".sp"
else:
self.lvs_file = self.sp_file
self.drc_errors = "skipped" self.drc_errors = "skipped"
self.lvs_errors = "skipped" self.lvs_errors = "skipped"

2
compiler/base/hierarchy_layout.py
View File

@ -36,6 +36,8 @@ class layout():
self.name = name self.name = name
self.cell_name = cell_name self.cell_name = cell_name
self.gds_file = OPTS.openram_tech + "gds_lib/" + cell_name + ".gds"
self.width = None self.width = None
self.height = None self.height = None
self.bounding_box = None self.bounding_box = None

16
compiler/base/hierarchy_spice.py
View File

@ -10,6 +10,7 @@ import re
import os import os
import math import math
import tech import tech
from globals import OPTS
from pprint import pformat from pprint import pformat
from delay_data import delay_data from delay_data import delay_data
from wire_spice_model import wire_spice_model from wire_spice_model import wire_spice_model
@ -32,6 +33,21 @@ class spice():
self.name = name self.name = name
self.cell_name = cell_name self.cell_name = cell_name
self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp"
# If we have a separate lvs directory, then all the lvs files
# should be in there (all or nothing!)
try:
lvs_subdir = tech.lvs_lib
except AttributeError:
lvs_subdir = "lvs_lib"
lvs_dir = OPTS.openram_tech + lvs_subdir + "/"
if os.path.exists(lvs_dir):
self.lvs_file = lvs_dir + cell_name + ".sp"
else:
self.lvs_file = self.sp_file
self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"] self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
# Holds subckts/mods for this module # Holds subckts/mods for this module
self.mods = [] self.mods = []