From fbe3032246885783caa68d7823224489583b1da8 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Thu, 26 May 2022 12:18:47 -0700 Subject: [PATCH] add case for single spare col spare_wen_dff i/o --- compiler/sram/sram_base.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index f6782597..6feda56f 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -688,7 +688,10 @@ class sram_base(design, verilog, lef): inputs = [] outputs = [] for bit in range(self.num_spare_cols): - inputs.append("spare_wen{}[{}]".format(port, bit)) + if self.num_spare_cols == 1: + inputs.append("spare_wen{0}".format(port)) + else: + inputs.append("spare_wen{0}[{1}]".format(port, bit)) outputs.append("bank_spare_wen{}_{}".format(port, bit)) self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)