mirror of https://github.com/VLSIDA/OpenRAM.git
Fix hspice delay golden results
This commit is contained in:
parent
d77bba3af2
commit
f84dc3cadc
|
|
@ -64,16 +64,16 @@ class timing_sram_test(openram_test):
|
||||||
'write0_power': [0.40809259999999997],
|
'write0_power': [0.40809259999999997],
|
||||||
'write1_power': [0.4078904]}
|
'write1_power': [0.4078904]}
|
||||||
elif OPTS.tech_name == "scn4m_subm":
|
elif OPTS.tech_name == "scn4m_subm":
|
||||||
golden_data = {'delay_hl': [1.3911],
|
golden_data = {'delay_hl': [1.4333000000000002],
|
||||||
'delay_lh': [1.3911],
|
'delay_lh': [1.4333000000000002],
|
||||||
'leakage_power': 0.0278488,
|
'leakage_power': 0.0271847,
|
||||||
'min_period': 2.812,
|
'min_period': 2.891,
|
||||||
'read0_power': [22.1183],
|
'read0_power': [15.714200000000002],
|
||||||
'read1_power': [21.4388],
|
'read1_power': [14.9848],
|
||||||
'slew_hl': [0.7397553],
|
'slew_hl': [0.6819276999999999],
|
||||||
'slew_lh': [0.7397553],
|
'slew_lh': [0.6819276999999999],
|
||||||
'write0_power': [19.4103],
|
'write0_power': [13.9658],
|
||||||
'write1_power': [20.1167]}
|
'write1_power': [14.8422]}
|
||||||
else:
|
else:
|
||||||
self.assertTrue(False) # other techs fail
|
self.assertTrue(False) # other techs fail
|
||||||
# Check if no too many or too few results
|
# Check if no too many or too few results
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue