diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index 7592186c..d412d42f 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -64,16 +64,16 @@ class timing_sram_test(openram_test):
                            'write0_power': [0.40809259999999997],
                            'write1_power': [0.4078904]}
         elif OPTS.tech_name == "scn4m_subm":
-            golden_data = {'delay_hl': [1.3911],
-                         'delay_lh': [1.3911],
-                         'leakage_power': 0.0278488,
-                         'min_period': 2.812,
-                         'read0_power': [22.1183],
-                         'read1_power': [21.4388],
-                         'slew_hl': [0.7397553],
-                         'slew_lh': [0.7397553],
-                         'write0_power': [19.4103],
-                         'write1_power': [20.1167]}
+            golden_data = {'delay_hl': [1.4333000000000002],
+                           'delay_lh': [1.4333000000000002],
+                           'leakage_power': 0.0271847,
+                           'min_period': 2.891,
+                           'read0_power': [15.714200000000002],
+                           'read1_power': [14.9848],
+                           'slew_hl': [0.6819276999999999],
+                           'slew_lh': [0.6819276999999999],
+                           'write0_power': [13.9658],
+                           'write1_power': [14.8422]}
         else:
             self.assertTrue(False) # other techs fail
         # Check if no too many or too few results