mirror of https://github.com/VLSIDA/OpenRAM.git
First draft of naive channel route in hierarchy_layout. It doesn't implement horizontal conflicts or try to minimize the number of channels.
This commit is contained in:
Matt Guthaus
parent
48d3b25b74
commit
f7a2766c29
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@ -636,6 +636,181 @@ class layout(lef.lef):
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offset=bus_pos,
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rotate=90)
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def add_horizontal_trunk_route(self, pins, trunk_offset,
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layer_stack=("metal1", "via1", "metal2"),
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pitch=None):
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"""
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Create a trunk route for all pins with the the trunk located at the given y offset.
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"""
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if not pitch:
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pitch = self.m1_pitch
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max_x = max([pin.center().x for pin in pins])
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min_x = min([pin.center().x for pin in pins])
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half_minwidth = 0.5*drc["minwidth_{}".format(layer_stack[0])]
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# if we are less than a pitch, just create a non-preferred layer jog
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if max_x-min_x < pitch:
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# Add the horizontal trunk on the vertical layer!
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self.add_path(layer_stack[2],[vector(min_x-half_minwidth,trunk_offset.y), vector(max_x+half_minwidth,trunk_offset.y)])
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# Route each pin to the trunk
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for pin in pins:
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# No bend needed here
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mid = vector(pin.center().x, trunk_offset.y)
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self.add_path(layer_stack[2], [pin.center(), mid])
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else:
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# Add the horizontal trunk
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self.add_path(layer_stack[0],[vector(min_x,trunk_offset.y), vector(max_x,trunk_offset.y)])
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trunk_mid = vector(0.5*(max_x+min_x),trunk_offset.y)
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# Route each pin to the trunk
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for pin in pins:
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# Bend to the center of the trunk so it adds a via automatically
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mid = vector(pin.center().x, trunk_offset.y)
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self.add_wire(layer_stack, [pin.center(), mid, trunk_mid])
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def add_vertical_trunk_route(self, pins, trunk_offset,
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layer_stack=("metal1", "via1", "metal2"),
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pitch=None):
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"""
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Create a trunk route for all pins with the the trunk located at the given x offset.
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"""
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if not pitch:
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pitch = self.m2_pitch
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max_y = max([pin.center().y for pin in pins])
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min_y = min([pin.center().y for pin in pins])
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# Add the vertical trunk
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half_minwidth = 0.5*drc["minwidth_{}".format(layer_stack[2])]
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# if we are less than a pitch, just create a non-preferred layer jog
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if max_y-min_y < pitch:
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# Add the horizontal trunk on the vertical layer!
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self.add_path(layer_stack[0],[vector(trunk_offset.x,min_y-half_minwidth), vector(trunk_offset.x,max_y+half_minwidth)])
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# Route each pin to the trunk
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for pin in pins:
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# No bend needed here
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mid = vector(trunk_offset.x, pin.center().y)
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self.add_path(layer_stack[0], [pin.center(), mid])
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else:
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# Add the vertical trunk
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self.add_path(layer_stack[2],[vector(trunk_offset.x,min_y), vector(trunk_offset.x,max_y)])
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trunk_mid = vector(trunk_offset.x,0.5*(max_y+min_y),)
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# Route each pin to the trunk
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for pin in pins:
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# Bend to the center of the trunk so it adds a via automatically
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mid = vector(trunk_offset.x, pin.center().y)
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self.add_wire(layer_stack, [pin.center(), mid, trunk_mid])
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def create_channel_route(self, route_map, bottom_inst, top_inst, offset,
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layer_stack=("metal1", "via1", "metal2"), pitch=None,
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vertical=False):
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"""
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This is a simple channel route for one-to-one connections that
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will jog the top route whenever there is a conflict. It does NOT
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try to minimize the number of tracks -- instead, it picks an order to avoid the vertical
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conflicts between pins.
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"""
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if not pitch and vertical:
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pitch = self.m2_pitch
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elif not pitch and not vertical:
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pitch = self.m1_pitch
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# FIXME: Must extend this to a horizontal conflict graph too if we want to minimize the
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# number of tracks!
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# Initialize the vertical conflict graph (vcg) and make a list of all pins
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vcg = {}
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all_pins = {}
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for (top_name, bot_name) in route_map:
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vcg[top_name] = []
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vcg[bot_name] = []
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top_pin = top_inst.get_pin(top_name)
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bot_pin = bottom_inst.get_pin(bot_name)
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all_pins[top_name]=top_pin
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all_pins[bot_name]=bot_pin
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# Find the vertical pin conflicts
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for (top_name, bot_name) in route_map:
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top_pin = all_pins[top_name]
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bot_pin = all_pins[bot_name]
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if abs(top_pin.center().x-bot_pin.center().x) < pitch:
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# The edges only go from top to bottom
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# since we will order tracks bottom up
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vcg[top_name].append(bot_name)
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# This is the starting offset of the first trunk
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if vertical:
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half_minwidth = 0.5*drc["minwidth_{}".format(layer_stack[2])]
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offset = offset + vector(half_minwidth,0)
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else:
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half_minwidth = 0.5*drc["minwidth_{}".format(layer_stack[0])]
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offset = offset + vector(0,half_minwidth)
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# list of routes to do
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while vcg:
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# get a route from conflict graph with empty fanout set
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route_pin=None
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for route_pin,conflicts in vcg.items():
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if len(conflicts)==0:
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# Remove the pin from the keys
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vcg.pop(route_pin,None)
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# Remove the pin from all conflicts
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# This is O(n^2), so maybe optimize it.
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for pin,conflicts in vcg.items():
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if pin in conflicts:
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conflicts.remove(route_pin)
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vcg[pin]=conflicts
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break
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#print("Routing:",route_pin)
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# Get the connected pins from the routing map
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for pin_connections in route_map:
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if route_pin in pin_connections:
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break
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#print("Routing:",pin_connections)
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# Remove the other pins from the conflict graph too
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for pin in pin_connections:
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vcg.pop(pin,None)
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# Create a list of the pins rather than a list of the names
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pin_list = [all_pins[pin_name] for pin_name in pin_connections]
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# Add the trunk route and move up to next track
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if vertical:
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self.add_vertical_trunk_route(pin_list, offset, layer_stack, pitch)
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offset += vector(pitch,0)
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else:
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self.add_horizontal_trunk_route(pin_list, offset, layer_stack, pitch)
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offset += vector(0,pitch)
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def create_vertical_channel_route(self, route_map, left_inst, right_inst, offset,
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layer_stack=("metal1", "via1", "metal2"),
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pitch=None):
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"""
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Wrapper to create a vertical channel route
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"""
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self.create_channel_route(route_map, left_inst, right_inst, offset,
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layer_stack, pitch, vertical=True)
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def create_horizontal_channel_route(self, route_map, top_inst, bottom_inst, offset,
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layer_stack=("metal1", "via1", "metal2"),
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pitch=None):
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"""
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Wrapper to create a horizontal channel route
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"""
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self.create_channel_route(route_map, top_inst, bottom_inst, offset,
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layer_stack, pitch, vertical=False)
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def add_enclosure(self, insts, layer="nwell"):
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""" Add a layer that surrounds the given instances. Useful
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for creating wells, for example. Doesn't check for minimum widths or
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@ -38,7 +38,7 @@ class sram_1bank(sram_base):
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control_pos.y + self.control_logic.height + self.m1_pitch)
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self.add_row_addr_dff(row_addr_pos)
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data_gap = -self.m2_pitch*(self.word_size+1)
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data_gap = -self.m1_pitch*(self.word_size+1)
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# Add the column address below the bank under the control
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# Keep it aligned with the data flops
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@ -174,23 +174,14 @@ class sram_1bank(sram_base):
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def route_data_dff(self):
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""" Connect the output of the data flops to the write driver """
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# Create a horizontal bus
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bus_names = ["data[{}]".format(x) for x in range(self.word_size)]
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data_bus_offsets = self.create_horizontal_bus(layer="metal1",
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pitch=self.m1_pitch,
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offset=self.data_dff_inst.ul() + vector(0, self.m1_pitch),
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names=bus_names,
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length=self.data_dff_inst.width)
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# This is where the channel will start (y-dimension at least)
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offset = self.data_dff_inst.ul() + vector(0, self.m1_pitch)
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dff_names = ["dout[{}]".format(x) for x in range(self.word_size)]
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data_dff_map = zip(dff_names, bus_names)
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self.connect_horizontal_bus(data_dff_map, self.data_dff_inst, data_bus_offsets)
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bank_names = ["bank_din[{}]".format(x) for x in range(self.word_size)]
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data_bank_map = zip(bank_names, bus_names)
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self.connect_horizontal_bus(data_bank_map, self.bank_inst, data_bus_offsets)
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route_map = list(zip(bank_names, dff_names))
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self.create_horizontal_channel_route(route_map, self.data_dff_inst, self.bank_inst, offset)
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