mirror of https://github.com/VLSIDA/OpenRAM.git
Route to top of NMOS to prevent poly overlap nmos
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@ -79,8 +79,8 @@ class pgate(design.design):
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debug.check(nmos_gate_pin.ll().x == pmos_gate_pin.ll().x,
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debug.check(nmos_gate_pin.ll().x == pmos_gate_pin.ll().x,
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"Connecting unaligned gates not supported. See unaligned_gates.gds.")
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"Connecting unaligned gates not supported. See unaligned_gates.gds.")
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# Pick point on the left of NMOS and connect down to PMOS
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# Pick point on the left of NMOS and up to PMOS
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nmos_gate_pos = nmos_gate_pin.ll() + vector(0.5 * self.poly_width, 0)
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nmos_gate_pos = nmos_gate_pin.ul() + vector(0.5 * self.poly_width, 0)
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pmos_gate_pos = vector(nmos_gate_pos.x, pmos_gate_pin.bc().y)
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pmos_gate_pos = vector(nmos_gate_pos.x, pmos_gate_pin.bc().y)
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self.add_path("poly", [nmos_gate_pos, pmos_gate_pos])
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self.add_path("poly", [nmos_gate_pos, pmos_gate_pos])
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