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OpenRAM
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Convert to new modules format

This commit is contained in:
Bugra Onal 2022-08-10 16:34:49 -07:00
parent 623c1ac02f
commit f743b1f068
2 changed files with 3 additions and 8 deletions
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7
compiler/modules/sram.py
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@ -40,11 +40,6 @@ class sram():
self.s = sram(name, sram_config) self.s = sram(name, sram_config)
if self.num_banks != 1:
from sram_multibank import sram_multibank
mb = sram_multibank(self.s)
mb.verilog_write()
self.s.create_netlist() self.s.create_netlist()
if not OPTS.netlist_only: if not OPTS.netlist_only:
self.s.create_layout() self.s.create_layout()
@ -64,7 +59,7 @@ class sram():
def verilog_write(self, name): def verilog_write(self, name):
if self.num_banks != 1: if self.num_banks != 1:
self.s.verilog_write(name[:-2] + '_1bank.v') self.s.verilog_write(name[:-2] + '_1bank.v')
from sram_multibank import sram_multibank from .sram_multibank import sram_multibank
mb = sram_multibank(self.s) mb = sram_multibank(self.s)
mb.verilog_write(name) mb.verilog_write(name)
else: else:

4
compiler/modules/sram_multibank.py
View File

@ -1,4 +1,4 @@
from template import template from .template import template
from globals import OPTS from globals import OPTS
import os import os
from math import ceil, log from math import ceil, log
@ -29,7 +29,7 @@ class sram_multibank:
} }
def verilog_write(self, name): def verilog_write(self, name):
template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "sram/sram_multibank_template.v") template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "modules/sram_multibank_template.v")
t = template(template_filename, self.dict) t = template(template_filename, self.dict)
t.write(name) t.write(name)
with open(name, 'r') as f: with open(name, 'r') as f: