From f743b1f068efaac5f0c4279df61a3c00153a3aed Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Wed, 10 Aug 2022 16:34:49 -0700 Subject: [PATCH] Convert to new modules format --- compiler/modules/sram.py | 7 +------ compiler/modules/sram_multibank.py | 4 ++-- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/compiler/modules/sram.py b/compiler/modules/sram.py index 67715789..07acb807 100644 --- a/compiler/modules/sram.py +++ b/compiler/modules/sram.py @@ -40,11 +40,6 @@ class sram(): self.s = sram(name, sram_config) - if self.num_banks != 1: - from sram_multibank import sram_multibank - mb = sram_multibank(self.s) - mb.verilog_write() - self.s.create_netlist() if not OPTS.netlist_only: self.s.create_layout() @@ -64,7 +59,7 @@ class sram(): def verilog_write(self, name): if self.num_banks != 1: self.s.verilog_write(name[:-2] + '_1bank.v') - from sram_multibank import sram_multibank + from .sram_multibank import sram_multibank mb = sram_multibank(self.s) mb.verilog_write(name) else: diff --git a/compiler/modules/sram_multibank.py b/compiler/modules/sram_multibank.py index 43195260..087f9e9d 100644 --- a/compiler/modules/sram_multibank.py +++ b/compiler/modules/sram_multibank.py @@ -1,4 +1,4 @@ -from template import template +from .template import template from globals import OPTS import os from math import ceil, log @@ -29,7 +29,7 @@ class sram_multibank: } def verilog_write(self, name): - template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "sram/sram_multibank_template.v") + template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "modules/sram_multibank_template.v") t = template(template_filename, self.dict) t.write(name) with open(name, 'r') as f: