Fix predecoder offset after relocating bank offset

compiler/modules/bank.py

@@ -75,6 +75,11 @@ class bank(design.design):
         self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1)
         self.bank_array_ur = self.bitcell_array_inst.ur()
         self.bank_array_ul = self.bitcell_array_inst.ul()
+
+        # These are used for other placements (e.g. address flops)
+        self.predecoder_top = self.port_address[0].predecoder_height + self.port_address_inst[0].by()
+        self.predecoder_bottom = self.port_address_inst[0].by()
+
         self.DRC_LVS()
 
     def add_pins(self):
@@ -227,7 +232,6 @@ class bank(design.design):
         x_offset = self.m2_gap + self.port_address[port].width
         self.port_address_offsets[port] = vector(-x_offset,
                                                  self.main_bitcell_array_bottom)
-        self.predecoder_height = self.port_address[port].predecoder_height + self.port_address_offsets[port].y
 
         # LOWER LEFT QUADRANT
         # Place the col decoder left aligned with wordline driver

compiler/sram/sram_1bank.py

@@ -120,8 +120,9 @@ class sram_1bank(sram_base):
         port = 0
         # The row address bits are placed above the control logic aligned on the right.
         x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width
-        # It is above the control logic but below the top of the bitcell array
-        y_offset = max(self.control_logic_insts[port].uy(), self.bank.predecoder_height)
+        # It is above the control logic and the predecoder array
+        y_offset = max(self.control_logic_insts[port].uy(), self.bank.predecoder_top)
+
         self.row_addr_pos[port] = vector(x_offset, y_offset)
         self.row_addr_dff_insts[port].place(self.row_addr_pos[port])
 
@@ -130,7 +131,7 @@ class sram_1bank(sram_base):
             # The row address bits are placed above the control logic aligned on the left.
             x_offset = self.control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width
             # If it can be placed above the predecoder and below the control logic, do it
-            y_offset = self.bank.bank_array_ll.y
+            y_offset = self.bank.predecoder_bottom
             self.row_addr_pos[port] = vector(x_offset, y_offset)
             self.row_addr_dff_insts[port].place(self.row_addr_pos[port], mirror="XY")