mirror of https://github.com/VLSIDA/OpenRAM.git
fix minimum pinv sizing
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@ -332,7 +332,7 @@ class pgate(design.design):
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debug.error("invalid tx type")
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debug.error("invalid tx type")
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bins = bins[0:bisect_left(bins, target_width) + 1]
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bins = bins[0:bisect_left(bins, target_width) + 1]
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if len(bins) == 1:
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if len(bins) == 1:
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selected_bins = (bins[0], math.ceil(target_width / bins[0]))
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scaled_bins = [(bins[0], math.ceil(target_width / bins[0]))]
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else:
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else:
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scaled_bins = []
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scaled_bins = []
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scaled_bins.append((bins[-1], 1))
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scaled_bins.append((bins[-1], 1))
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