From f5804e1cbff61242de4eaf8c735ab0fc52aefff3 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 16 Jul 2019 11:53:20 -0700 Subject: [PATCH] Flatten bitcell array for LVS symmetries. --- technology/scn4m_subm/mag_lib/setup.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/technology/scn4m_subm/mag_lib/setup.tcl b/technology/scn4m_subm/mag_lib/setup.tcl index f2567d7d..95e7dbea 100644 --- a/technology/scn4m_subm/mag_lib/setup.tcl +++ b/technology/scn4m_subm/mag_lib/setup.tcl @@ -6,6 +6,7 @@ equate class {-circuit1 pfet} {-circuit2 p} flatten class {-circuit1 dummy_cell_6t} flatten class {-circuit1 dummy_cell_1rw_1r} flatten class {-circuit1 dummy_cell_1w_1r} +flatten class {-circuit1 bitcell_array_0} flatten class {-circuit1 pbitcell_0} flatten class {-circuit1 pbitcell_1} property {-circuit1 nfet} remove as ad ps pd