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Update riscv unit test

This commit is contained in:
mrg 2020-09-30 08:50:58 -07:00
parent b147e8485c
commit f4e6a8895b
3 changed files with 12 additions and 9 deletions
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8
compiler/modules/bank.py
View File

@ -374,15 +374,15 @@ class bank(design.design):
port=port)) port=port))
self.add_mod(self.port_address[port]) self.add_mod(self.port_address[port])
total_cols = self.num_cols + self.num_spare_cols
try: try:
local_array_size = OPTS.local_array_size local_array_size = OPTS.local_array_size
except AttributeError: except AttributeError:
#local_array_size = ceil(sqrt(self.num_cols + self.num_spare_cols)) local_array_size = 0
local_array_size = ceil(sqrt(self.num_cols + self.num_spare_cols))
if local_array_size > 0: if local_array_size > 0:
# Find the even multiple that satisfies the fanout with equal sized local arrays # Find the even multiple that satisfies the fanout with equal sized local arrays
total_cols = self.num_cols + self.num_spare_cols
num_lb = floor(total_cols / local_array_size) num_lb = floor(total_cols / local_array_size)
final_size = total_cols - num_lb * local_array_size final_size = total_cols - num_lb * local_array_size
cols = [local_array_size] * (num_lb - 1) cols = [local_array_size] * (num_lb - 1)
@ -393,7 +393,7 @@ class bank(design.design):
rows=self.num_rows) rows=self.num_rows)
else: else:
self.bitcell_array = factory.create(module_type="replica_bitcell_array", self.bitcell_array = factory.create(module_type="replica_bitcell_array",
cols=self.num_cols + self.num_spare_cols, cols=total_cols,
rows=self.num_rows) rows=self.num_rows)
self.add_mod(self.bitcell_array) self.add_mod(self.bitcell_array)

8
compiler/tests/50_riscv_func_test.py
View File

@ -22,13 +22,15 @@ class riscv_func_test(openram_test):
def runTest(self): def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file) globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
globals.setup_bitcell() globals.setup_bitcell()
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.local_array_size = 16
# This is a hack to reload the characterizer __init__ with the spice version # This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload from importlib import reload

5
compiler/tests/50_riscv_phys_test.py
View File

@ -28,8 +28,9 @@ class riscv_phys_test(openram_test):
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
globals.setup_bitcell() globals.setup_bitcell()
OPTS.route_supplies=False OPTS.route_supplies = False
OPTS.perimeter_pins=False OPTS.perimeter_pins = False
OPTS.local_array_size = 16
c = sram_config(word_size=32, c = sram_config(word_size=32,
write_size=8, write_size=8,