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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 01:24:39 +02:00
Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases.
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@@ -30,7 +30,11 @@ class sense_amp_array(design.design):
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def create_layout(self):
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self.height = self.amp.height
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self.width = self.amp.width * self.word_size * self.words_per_row
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if self.bitcell.width > self.amp.width:
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self.width = self.bitcell.width * self.word_size * self.words_per_row
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else:
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self.width = self.amp.width * self.word_size * self.words_per_row
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self.place_sense_amp_array()
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self.add_layout_pins()
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@@ -53,6 +57,10 @@ class sense_amp_array(design.design):
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self.amp = self.mod_sense_amp("sense_amp")
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self.add_mod(self.amp)
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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self.add_mod(self.bitcell)
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def create_sense_amp_array(self):
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self.local_insts = []
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@@ -68,7 +76,10 @@ class sense_amp_array(design.design):
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def place_sense_amp_array(self):
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amp_spacing = self.amp.width * self.words_per_row
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if self.bitcell.width > self.amp.width:
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amp_spacing = self.bitcell.width * self.words_per_row
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else:
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amp_spacing = self.amp.width * self.words_per_row
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for i in range(0,self.word_size):
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amp_position = vector(amp_spacing * i, 0)
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self.local_insts[i].place(amp_position)
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@@ -30,7 +30,12 @@ class write_driver_array(design.design):
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self.create_write_array()
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def create_layout(self):
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self.width = self.columns * self.driver.width
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if self.bitcell.width > self.driver.width:
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self.width = self.columns * self.bitcell.width
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else:
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self.width = self.columns * self.driver.width
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self.height = self.driver.height
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self.place_write_array()
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@@ -53,6 +58,11 @@ class write_driver_array(design.design):
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self.mod_write_driver = getattr(c, OPTS.write_driver)
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self.driver = self.mod_write_driver("write_driver")
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self.add_mod(self.driver)
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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self.add_mod(self.bitcell)
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def create_write_array(self):
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self.driver_insts = {}
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@@ -69,9 +79,14 @@ class write_driver_array(design.design):
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def place_write_array(self):
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if self.bitcell.width > self.driver.width:
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driver_spacing = self.bitcell.width
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else:
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driver_spacing = self.driver.width
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for i in range(0,self.columns,self.words_per_row):
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index = int(i/self.words_per_row)
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base = vector(i * self.driver.width,0)
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base = vector(i * driver_spacing,0)
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self.driver_insts[index].place(base)
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