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Getting single bank to work reliably. Removed tri_gate from bank

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for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
This commit is contained in:
Matt Guthaus
2018-07-13 14:45:46 -07:00
parent 834fbac8de
commit f3ae29fe0b
7 changed files with 181 additions and 97 deletions
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compiler/tests/testutils.py
+4 -4
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@@ -32,14 +32,14 @@ class openram_test(unittest.TestCase):
a.gds_write(tempgds)
import verify
result=verify.run_drc(a.get_name(), tempgds)
result=verify.run_drc(a.name, tempgds)
if result != 0:
self.fail("DRC failed: {}".format(a.get_name()))
self.fail("DRC failed: {}".format(a.name))
result=verify.run_lvs(a.get_name(), tempgds, tempspice, final_verification)
result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
if result != 0:
self.fail("LVS mismatch: {}".format(a.get_name()))
self.fail("LVS mismatch: {}".format(a.name))
if OPTS.purge_temp:
self.cleanup()